TWI690039B - Electronic package and manufacturing method thereof - Google Patents

Abstract

This invention provides an electronic package and a manufacturing method thereof, in which an electronic component is disposed on a carrier by the manner of flip chip, and the electronic component is covered by an encapsulation layer. In addition, part of the material of the encapsulation layer, part of the material of the electronic component, and part of the material of the carrier are removed by the leveling operation to reduce the overall thickness of the electronic package.

Description

Electronic package and its manufacturing method

The invention relates to a semiconductor packaging process, in particular to an electronic package and its manufacturing method.

There are many technologies currently used in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (Multi-Chip Module, abbreviation) MCM) and other flip-chip packaging processes, or integrate the three-dimensional stacking of chips into a three-dimensional integrated circuit (3D IC) chip stacking process.

As shown in FIG. 1, the conventional quad flat no leads (QFN) type semiconductor package 1 is a semiconductor chip 11 which is flip-chip mounted on a chip through a plurality of solder bumps 110 On the lead frame 10, the semiconductor chip 11, the lead frame 10 and the solder bump 110 are coated with the encapsulant 12 and then cut to make the side surface and bottom surface of each lead 100 of the lead frame 10 ( Bottom Surface) exposes the encapsulating gel 12, and the bottom surface of each of the guide pins 100 is flush with the bottom surface of the encapsulating gel 12.

On the other hand, in order to meet the requirement of thinning, the thickness d of the semiconductor wafer 11 needs to be reduced first, and then the semiconductor wafer 11 is placed on the lead frame 10.

However, under the requirement of a multi-contact (I/O) quantity and a small package size, especially the overall thickness t of the semiconductor package 1 is less than 0.3 mm, the thickness d required by the semiconductor chip 11 is extremely small, so When the semiconductor chip 11 is placed on the lead frame 10, it is easy to be pressed to cause a crack, which results in poor reliability of the semiconductor package 1.

Therefore, how to overcome the above-mentioned problems of the conventional technology has become an urgent problem to be solved at present.

In view of the lack of the above-mentioned conventional technology, the present invention provides an electronic package including: a carrier having a plurality of leads; an electronic component coupled to the carrier and electrically connecting the plurality of leads; and a package A layer is formed on the carrier and encapsulates the electronic component, wherein the encapsulation layer defines opposite first and second surfaces, and one surface of the electronic component is flush with the first surface of the encapsulation layer And the guide pin is flush with the second surface of the packaging layer.

The invention also provides a method for manufacturing an electronic package, which comprises: combining an electronic component on a carrier with a plurality of leads, and making the electronic component electrically connected to the plurality of leads; forming a packaging layer on the carrier To wrap the electronic component with the encapsulation layer; and remove part of the material of the encapsulation layer, part of the material of the electronic component and part of the material of the carrier, so that the encapsulation layer defines the opposite first surface and second surface , So that a surface of the electronic component is flush with the first surface of the packaging layer, and a surface of the guide pin is flush with the second surface of the packaging layer.

In the foregoing manufacturing method, some materials of the encapsulation layer, some materials of the electronic component and some materials of the carrier are removed by grinding.

In the aforesaid manufacturing method, the complex includes cutting orders.

In the aforementioned electronic package and its manufacturing method, the carrier is a lead frame.

In the aforementioned electronic package and its manufacturing method, the electronic component has opposing active surfaces and non-active surfaces, the electronic component is provided on the guide pin with a plurality of conductive bumps on the active surface, and the non-active surface is flush The first surface of the encapsulation layer.

In the aforementioned electronic package and its manufacturing method, the encapsulation layer defines a side surface adjacent to the first surface and the second surface, and a part of the surface of the lead pin is exposed to the side surface of the encapsulation layer.

In the aforementioned electronic package and its manufacturing method, the electronic component is exposed on the first surface of the packaging layer.

In the aforementioned electronic package and its manufacturing method, the compound includes an insulating layer disposed on the second surface of the package layer, which has a plurality of openings exposing the lead pins.

In the aforementioned electronic package and its manufacturing method, it further includes an action member disposed on the first surface of the electronic component and the packaging layer. It also includes an insulating layer disposed on the second surface of the encapsulation layer, which has a plurality of openings exposing the lead pins. For example, the material of the acting member is the same as the material of the insulating layer. Alternatively, the material of the acting part is a polymer as a protective layer.

It can be seen from the above that in the electronic package of the present invention and its manufacturing method, the first surface of the packaging layer is flush with the upper surface of the electronic component, and the second surface of the packaging layer is flush with the lower surface of the guide pin to reduce The thickness of the carrier and the thickness of the encapsulation layer, compared with the conventional technology, the overall thickness of the electronic package obtained by the manufacturing method of the present invention can meet the requirements of thinning, and can avoid the chipping of the electronic component.

1‧‧‧Semiconductor package

10‧‧‧ Lead frame

100,200‧‧‧lead

11‧‧‧Semiconductor chip

110‧‧‧Solder bump

12‧‧‧Packing colloid

2‧‧‧Electronic package

20‧‧‧Carrier

20a‧‧‧First side

20b‧‧‧Second side

21‧‧‧Electronic components

21a‧‧‧action surface

21b‧‧‧non-acting surface

210‧‧‧electrode pad

211‧‧‧conductive bump

22‧‧‧Encapsulation layer

22a‧‧‧First surface

22b‧‧‧Second surface

22c‧‧‧Side

23‧‧‧Insulation

230‧‧‧opening

24‧‧‧Function piece

A‧‧‧Chip placement department

B‧‧‧External Department

d,h,h1,h2,r,t‧‧‧thickness

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package.

2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

The following describes the implementation of the present invention by specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structure, ratio, size, etc. shown in the drawings of this specification are only used to match the content disclosed in the specification, for those who are familiar with this skill to understand and read, not to limit the implementation of the present invention The limited conditions do not have technical significance. Any modification of structure, change of proportional relationship or adjustment of size should still fall within the scope of the invention without affecting the efficacy and the purpose of the invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "first", "second", "upper", "lower" and "one" cited in this specification are only for the convenience of description, not to limit the invention. The scope of implementation, changes or adjustments in their relative relationship, without substantial changes in the technical content, shall also be regarded as the scope of the invention.

2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A, a carrier 20 having a first side 20a and a second side 20b opposite to each other is provided.

In this embodiment, the carrier 20 is a lead frame, which includes a plurality of phase-separated guide pins 200, wherein the guide pins 200 define an adjacent crystal placement portion A and an external portion B, and the The crystal placement portion A is closer to the middle region than the circumscribed portion B.

As shown in FIG. 2B, at least one electronic component 21 is combined on the first side 20a of the carrier 20. Next, an encapsulation layer 22 is formed on the first side 20a of the carrier 20 to cover the electronic component 21 and expose the second side 20b of the carrier 20.

The electronic component 21 is an active component, a passive component, or a combination of both. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the electronic component 21 is a semiconductor chip, which has an opposing active surface 21a and a non-active surface 21b, and the active surface 21a has a plurality of electrode pads 210, so that the electronic component 21 is joined by a plurality of these The conductive bumps 211 (such as solder material or other conductive materials) of the electrode pad 210 are mounted on the crystal placement portion A of the lead pins 200 by flip chip method, so that the electronic component 21 is electrically connected to the lead pins 200.

Furthermore, the material forming the encapsulation layer 22 is polyimide (PI), dry film, dry film, epoxy, molding compound, or other suitable insulating materials.

As shown in FIG. 2C, part of the material of the encapsulation layer 22, part of the material of the electronic component 21 and part of the material of the carrier 20 (second side 20b) are removed to make the non-active surface 21b of the electronic component 21 It is exposed to the encapsulation layer 22, and the second side 20b of the carrier 20 is still exposed to the encapsulation layer 22.

In this embodiment, part of the material of the packaging layer 22 and the non-function of the electronic component 21 are removed along the predetermined removal areas L above and below as shown in FIG. 2B by leveling operations (such as grinding) The partial material of the surface 21b and the partial material of the second side 20b of the carrier 20 define the opposite first surface 22a and the second surface 22b of the encapsulation layer 22 so that the non-active surface 21b of the electronic component 21 is aligned The first surface 22a of the encapsulation layer 22 is leveled, and the guide pins 200 (or the second side 20b of the carrier 20) are flush with the second surface 22b of the encapsulation layer 22.

As shown in FIG. 2D, the singulation operation is performed along the cutting path S shown in FIG. 2C to obtain the electronic package 2 whose lead pins 200 are exposed on the side surface 22c of the packaging layer 22.

In this embodiment, the electronic package 2 is a quad flat no-lead (QFN) type, and the bottom surface and the side surfaces of the lead pins 200 are flush with the second surface 22b and the side surface 22c of the packaging layer 22, so that For subsequent formation of solder material (such as a solder ball) on the exposed surfaces of the guide pins 200 for connection to an electronic device such as a circuit board or another circuit board (not shown).

Furthermore, an insulating layer 23, such as a solder mask, can be formed on the second side 20b of the carrier 20 and the second surface 22b of the encapsulation layer 22 as required, which forms a plurality of exposed portions of the guide pin 200 opening The hole 230 is used to form a solder material (such as a solder ball) on the lead pins 200 exposed in the openings 230 (figure omitted).

In addition, an action member 24 such as a film, a heat dissipation material, or other structures may be disposed on the first surface 22a of the encapsulation layer 22 and the non-acting surface 21b of the electronic element 21 to protect the electronic element 21 or provide the Heat dissipation of the electronic component 21. For example, the material of the acting member 24 may use a polymer as a protective layer; or, the material of the acting member 24 and the insulating layer 23 may be the same.

Therefore, the manufacturing method of the present invention removes part of the material of the encapsulation layer 22, part of the material of the electronic component 21 and part of the material of the second side 20b of the carrier 20 by leveling to reduce the carrier The thickness h1 of 20 and the thickness h2 of the packaging layer 22 (as shown in FIG. 2C), so compared to the conventional technology, the overall thickness h of the electronic package 2 obtained by the manufacturing method of the present invention (as shown in FIG. 2D ) Can meet the requirements of thinning, for example, the overall thickness h is only 0.135mm.

Furthermore, the manufacturing method of the present invention is to first place the electronic component 21 on the carrier 20, and then wrap the electronic component 21 with the encapsulation layer 22, so as to remove part of the material of the encapsulation layer 22 and the electronic component 21 part of the non-acting surface 21b material, the encapsulation layer 22 can be dispersed Compared with the conventional technology, the manufacturing method of the present invention can not only reduce the thickness r of the electronic component 21, but also avoid the problem of cracking of the electronic component 21.

The present invention further provides an electronic package 2 including: a carrier 20, an electronic component 21 and a packaging layer 22.

The carrier 20 is a lead frame, which includes a plurality of guide pins 200 separated by phases.

The electronic component 21 is coupled to the carrier 20 and electrically connected to the lead 200.

The encapsulation layer 22 is formed on the carrier 20 and covers the electronic component 21, wherein the encapsulation layer 22 defines a first surface 22 a and a second surface 22 b opposite to the electronic component 21 The surface is flush with the first surface 22a of the packaging layer 22, and the lower surface of the lead 200 is flush with the second surface 22b of the packaging layer 22, so that the electronic component 21 and the lead 200 are exposed to the package Layer 22.

In one embodiment, the electronic component 21 has opposing active surfaces 21a and non-active surfaces 21b, and the active surface 21a is provided on the guide pin 200 by a plurality of conductive bumps 211, and the non-active surface 21b is flush The first surface 22a of the encapsulation layer 22.

In one embodiment, the encapsulation layer 22 defines a side surface 22c adjacent to the first and second surfaces 22a, 22b, so that the guide pin 200 is exposed to the side surface 22c of the encapsulation layer 22.

In one embodiment, the electronic component 21 is exposed on the first surface 22a of the encapsulation layer 22.

In one embodiment, the electronic package 2 includes an insulating layer 23 disposed on the second surface 22b of the packaging layer 22, and has a plurality of openings 230 exposing the lead 200.

In an embodiment, the electronic package 2 includes an action member 24 disposed on the first surface 22a of the electronic component 21 and the packaging layer 22. For example, the material of the action member 24 The quality is the same as the material of the insulating layer 23. Alternatively, the material of the action member 24 is a polymer, which is used as a protective layer.

In summary, the electronic package and its manufacturing method of the present invention use the upper and lower grinding processes to reduce the overall thickness of the electronic package, which can meet the needs of thinning and avoid the electronic The problem of broken components.

The above embodiments are used to exemplify the principles and effects of the present invention, rather than to limit the present invention. Anyone who is familiar with this skill can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be as listed in the scope of patent application mentioned later.

2‧‧‧Electronic package

20‧‧‧Carrier

20b‧‧‧Second side

200‧‧‧Guide feet

21‧‧‧Electronic components

21b‧‧‧non-acting surface

22‧‧‧Encapsulation layer

22a‧‧‧First surface

22b‧‧‧Second surface

22c‧‧‧Side

23‧‧‧Insulation

230‧‧‧opening

24‧‧‧Function piece

h‧‧‧thickness

Claims (17)

An electronic package includes: a carrier, which has a plurality of leads; an electronic component, which is coupled to the carrier and is electrically connected to the plurality of leads; an encapsulation layer is formed on the carrier and covers the An electronic component, wherein the packaging layer defines opposite first and second surfaces, one surface of the electronic component is flush with the first surface of the packaging layer, and one surface of the lead is flush with the package The second surface of the layer; and the active part are arranged on the first surface of the electronic component and the encapsulation layer, wherein the material of the active part is a polymer, which is used as a protective layer. The electronic package as described in item 1 of the patent application scope, wherein the carrier is a lead frame. The electronic package as described in item 1 of the patent application range, wherein the electronic component has opposite active surfaces and non-active surfaces, and the electronic component is provided on the guide pin with a plurality of conductive bumps on the active surface, And the non-active surface is flush with the first surface of the encapsulation layer. The electronic package as described in item 1 of the patent application scope, wherein the encapsulation layer defines a side surface adjacent to the first surface and the second surface, and a part of the surface of the lead pin is exposed to the side surface of the encapsulation layer. The electronic package described in item 1 of the patent application range includes an insulating layer disposed on the second surface of the packaging layer, which has a plurality of openings exposing the lead pins. The electronic package as described in item 5 of the patent application scope, wherein the material of the acting part is the same as the material of the insulating layer. A manufacturing method of electronic package includes: Combining the electronic component on a carrier with a plurality of lead pins, and making the electronic component electrically connected to the plurality of lead pins; forming an encapsulation layer on the carrier, so that the encapsulation layer covers the electronic component; and removing Part of the material of the encapsulation layer, part of the material of the electronic component and part of the material of the carrier make the encapsulation layer define the first surface and the second surface so that one surface of the electronic component is flush with the encapsulation layer The first surface, and one surface of the guide pin is flush with the second surface of the packaging layer. The method for manufacturing an electronic package as described in item 7 of the patent application scope, wherein the carrier is a lead frame. The method for manufacturing an electronic package as described in item 7 of the patent application scope, wherein the electronic component has opposite active surfaces and non-active surfaces, and the electronic component is provided on the guide pin with a plurality of conductive bumps on the active surface And the non-active surface is flush with the first surface of the encapsulation layer. The method for manufacturing an electronic package as described in item 7 of the patent application scope, wherein the packaging layer defines a side surface adjacent to the first surface and the second surface, and a part of the surface of the guide pin is exposed outside the packaging layer side. According to the method of manufacturing an electronic package described in item 7 of the patent application scope, the method further includes disposing an insulating layer on the second surface of the packaging layer, wherein the insulating layer has a plurality of openings exposing the lead pins. According to the manufacturing method of the electronic package described in item 7 of the patent application scope, the method further includes arranging the acting part on the first surface of the electronic component and the packaging layer. According to the method of manufacturing an electronic package described in item 12 of the patent application range, the method includes disposing an insulating layer on the second surface of the packaging layer, and the insulating layer has a plurality of openings exposing the lead pins. The manufacturing method of the electronic package as described in item 13 of the patent application scope, wherein the material of the acting part is the same as the material of the insulating layer. The manufacturing method of the electronic package as described in item 12 of the patent application scope, in which the material of the acting part is a polymer as a protective layer. The method for manufacturing an electronic package as described in item 7 of the patent application scope, in which part of the material of the packaging layer, part of the material of the electronic component and part of the material of the carrier are removed by grinding. For example, the manufacturing method of electronic packaging described in item 7 of the scope of patent application includes the operation of cutting orders.

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