TWI681507B - Via contact, memory device, and method of forming semiconductor structure - Google Patents

Abstract

Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.

Description

Through-hole contact structure, memory device and formation of semiconductor Body structure method

The invention relates to a semiconductor structure and a method of forming a semiconductor structure. Specifically, the present invention relates to a via contact structure for a semiconductor device, a memory device having a via contact structure, and a method of manufacturing the via contact structure and the memory device.

The semiconductor integrated circuit industry has experienced rapid growth. The manufacturing technology of integrated circuits has produced several generations of integrated circuits, and each generation of integrated circuits has smaller and more complex circuits than the previous generation of integrated circuits. The industry has developed a variety of advanced technologies to form smaller feature sizes, and these technologies are utilized in manufacturing data storage devices such as flash memory. However, some process technologies are not entirely satisfactory. For example, in traditional etching techniques, how to achieve high aspect ratio contact vias will face challenges. Therefore, one of the technical advantages of the present invention is to provide a solution to form a contact via with a high aspect ratio.

An aspect of the present invention is to provide a method of forming a semiconductor structure. The method includes the following steps: forming a first dielectric layer having a first through hole on the precursor substrate, the first through hole penetrating the first dielectric layer; filling the sacrificial material in the first through hole; forming a second dielectric having a second through hole The electrical layer is above the first dielectric layer, the second through hole exposes the sacrificial material in the first through hole, wherein the second through hole has a bottom width, the bottom width is smaller than the top width of the first through hole, and the first through hole and the second through hole are perpendicular The precursor substrate at least partially overlaps in one direction; after forming the second dielectric layer having the second through hole, the sacrificial material is removed; forming a barrier layer lining the side wall of the first through hole and the side wall of the second through hole; and forming conductive The material is inside the first and second perforations.

Another aspect of the present invention is to provide a via contact structure for a semiconductor device. The through-hole contact structure includes a first conductive structure, a second conductive structure, and a barrier layer. The first conductive structure has a top. The second conductive structure has a bottom, the bottom is in contact and is disposed on the top of the first conductive structure. The bottom of the second conductive structure has a width that is smaller than a width of the top of the first conductive structure, so that a portion of the top of the first conductive structure is not occupied by the bottom of the second conductive structure. The barrier layer covers the side wall of the first conductive structure and the side wall of the second conductive structure, and the barrier layer continuously extends from the side wall of the first conductive structure to the second conductive structure through the unoccupied portion of the top Sidewall.

Another aspect of the present invention is to provide a memory device. The memory device includes a semiconductor substrate, a dielectric layer, a barrier layer, and a conductive plug. The semiconductor substrate includes a memory array area and peripheral circuits adjacent to the memory array area. The dielectric layer is disposed above the peripheral circuit, the dielectric layer has There are a first hole and a second hole. The second hole is connected to the first hole and is located above the first hole. The bottom width of the second hole is smaller than the top width of the first hole, so that the dielectric layer forms an overhang at the connection between the first hole and the second hole. The barrier layer continuously extends from the side wall of the first hole to the side wall of the second hole via the overhang. The conductive plug is filled in the first hole and the second hole.

10‧‧‧Method

12, 14, 16‧‧‧ steps

18, 20, 22‧‧‧ steps

100‧‧‧Precursor substrate

100a‧‧‧Memory array area

100b‧‧‧peripheral circuit area

101‧‧‧Semiconductor substrate

102‧‧‧High voltage p-type metal oxide semiconductor transistor

102G‧‧‧Gate

102S/D‧‧‧Source/Drain

104‧‧‧Silicide metal structure

105‧‧‧Conductive characteristic structure

103‧‧‧Low voltage n-type metal oxide semiconductor transistor

103G‧‧‧Gate

102S/D‧‧‧Source/Drain

103S/D‧‧‧Source/Drain

106‧‧‧Silicide metal structure

107‧‧‧Conductive structure

108‧‧‧Isolated structure

109‧‧‧dielectric layer

110‧‧‧First dielectric layer

110a‧‧‧Dielectric material layer

111‧‧‧ First punch

111a‧‧‧Side wall

114‧‧‧Sacrifice material

120‧‧‧Second dielectric layer

120a‧‧‧Dielectric material layer

122‧‧‧Second Perforation

122a‧‧‧Side wall

130‧‧‧Stacking structure

132‧‧‧conductive layer

134‧‧‧Insulation

140‧‧‧ data storage structure

150‧‧‧Interlayer dielectric layer

151‧‧‧ First contact hole

152‧‧‧Second contact hole

160‧‧‧Barrier layer

170‧‧‧conductive material

200‧‧‧Through hole contact structure

210‧‧‧The first conductive structure

212‧‧‧Top

214‧‧‧Bottom

210a‧‧‧Side wall

220‧‧‧Second conductive structure

222‧‧‧Bottom

220a‧‧‧Side wall

230‧‧‧Barrier layer

240‧‧‧Semiconductor substrate

242‧‧‧Conductive structure

250, 252‧‧‧ dielectric layer

300‧‧‧Memory device

310‧‧‧Semiconductor substrate

310a‧‧‧Memory array area

310b‧‧‧ Peripheral circuit area

312‧‧‧Peripheral circuit

314‧‧‧Transistor

314G‧‧‧Gate

314S/D‧‧‧Source/Drain

316‧‧‧Metal silicide

317, 320 ‧‧‧ dielectric layer

321‧‧‧ First hole

322‧‧‧Second hole

324‧‧‧Overhang

330‧‧‧Barrier layer

340‧‧‧Conducting plug

350‧‧‧Stacking structure

352‧‧‧conductive layer

354‧‧‧Insulation

360‧‧‧Data storage structure

380‧‧‧Interlayer dielectric layer

381‧‧‧First contact hole

382‧‧‧Second contact hole

384‧‧‧Contact plug

400‧‧‧Precursor substrate

401‧‧‧Semiconductor substrate

400a‧‧‧Memory array area

400b‧‧‧ Peripheral circuit area

402‧‧‧High voltage p-type metal oxide semiconductor transistor

402G‧‧‧Gate

402S/D‧‧‧Source/Drain

403‧‧‧Low voltage n-type metal oxide semiconductor transistor

403G‧‧‧Gate

403S/D‧‧‧Source/Drain

410‧‧‧First dielectric layer

411‧‧‧ First punch

420”‧‧‧The first barrier material

430”‧‧‧The first conductive material

420‧‧‧The first barrier layer

430‧‧‧The first conductive plug

430a‧‧‧Top

440‧‧‧Second dielectric layer

450‧‧‧Stacking structure

452‧‧‧conductive layer

454‧‧‧Insulation

456‧‧‧Wire

460‧‧‧Data storage structure

462‧‧‧Data storage layer

464‧‧‧Insulation material

464‧‧‧Semiconductor layer

470‧‧‧Interlayer dielectric layer

471‧‧‧ First contact hole

472‧‧‧Second contact hole

480‧‧‧The second barrier layer

480a‧‧‧Bottom

491‧‧‧Contact plug

492‧‧‧Second conductive plug

D1‧‧‧ direction

D2‧‧‧ direction

D3‧‧‧ Height direction

S‧‧‧Main surface

W1‧‧‧Top width

W2‧‧‧Bottom width

FIG. 1 is a flowchart of a method of forming a semiconductor structure according to various embodiments of the present invention.

FIGS. 2-13 are cross-sectional views of the method for forming a semiconductor structure according to various embodiments of the present invention at different manufacturing stages.

14 is a schematic cross-sectional view of a through-hole contact structure according to various embodiments of the present invention.

FIG. 15 is a schematic cross-sectional view of a memory device according to various embodiments of the invention.

FIG. 16A shows an enlarged view of the area R in FIG. 15.

FIG. 16B is a schematic plan view of the first hole and the second hole along the cutting plane C in the region R. FIG.

17-24 are schematic cross-sectional views of a method for forming a semiconductor structure according to a comparative example of the present invention at different stages of the manufacturing process.

FIG. 25 shows an enlarged view of the area M in FIG. 24.

In order to make the description of this disclosure more detailed and complete, the following provides an illustrative description of the implementation form and specific embodiments of the present invention Description; but this is not the only form of implementing or using specific embodiments of the invention. The embodiments disclosed below can be combined or replaced with each other under beneficial circumstances, and other embodiments can be added to an embodiment without further description or description.

The following invention provides many different implementations or examples to achieve the different features of the subject matter. Specific implementations of components and arrangements are described below to simplify the present disclosure. Of course, these embodiments are only examples and are not intended to be limiting. For example, the following description describes the formation of the first feature on or above the second feature, which may include the first feature and the second feature are formed in direct contact with the embodiment, and may also include the formation between the first feature and the second feature An additional feature, such that the first feature and the second feature are not in direct contact. In addition, the present invention may use repeated element symbols and/or letters in each embodiment. Such repetition is for simplicity and clarity, and does not refer to the relationship between the embodiments and/or configurations discussed.

It should be understood that although the terms "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element may be referred to as the second element; similarly, the second element may be referred to as the first element without departing from the scope of the embodiments. The term "and/or" as used herein includes any and all combinations of one or more related listed items.

Furthermore, for ease of description, spatial relative terms (such as "below", "below", "lower", "above", "upper" and similar terms) are used in this article Describe the place in the schema The relationship between an element or feature shown and another element (or elements) or feature (or features). In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different directions of the device in use or steps. This device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative description words used in this article should be interpreted similarly.

In addition, when terms such as "about" and "approximately" are used to describe a numerical value or numerical range, the purpose of the term is to include a numerical range within a reasonable range, such as +/-20% of the numerical value or understood by those skilled in the art Other numerical ranges. For example, the term "about 5 nm" includes a size range of 4.0 nm to 6.0 nm.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

FIG. 1 is a flowchart of a method 10 for forming a semiconductor structure according to various embodiments of the present invention. Method 10 includes steps 12, 14, 16, 18, 20, and 22. Figures 2-13 illustrate the manufacturing methods of various embodiments of the present invention in more detail with a series of cross-sectional views. It should be understood that the methods described herein describe or depict many steps and/or features, but not all of these steps and/or features are necessary; and other steps and/or features that are not described or depicted may be added . In addition, the order of the steps in some embodiments may be different from that shown in the drawings. Furthermore, in some specific implementations, the illustrated steps can be further divided into sub-steps; while in other specific implementations, some illustrated steps can be performed simultaneously with another step.

Referring to FIG. 1, method 10 includes step 10, forming a first dielectric layer having at least one first through hole on the precursor substrate. As shown in FIG. 2, before forming the first dielectric layer, the precursor substrate 100 is provided. In some embodiments, the precursor substrate 100 includes a semiconductor substrate 101 having a memory array area 100a and a peripheral circuit area 100b. The peripheral circuit area 100b is adjacent to the memory array area 100a. For example, the semiconductor substrate 101 may include silicon. In some embodiments, the semiconductor substrate 101 may contain other element semiconductors, such as germanium. In some other embodiments, the semiconductor substrate 101 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, indium gallium phosphide, and the like. In still other embodiments, the semiconductor substrate 101 may include compound semiconductors, such as gallium arsenide, silicon carbide, indium phosphide, indium arsenide, and the like. In still other embodiments, the semiconductor substrate 101 may include a semiconductor-on-insulator (SOI) structure. In still other embodiments, the semiconductor substrate 101 may include an epitaxial layer covering the semiconductor material.

According to some embodiments, the precursor substrate 100 further includes peripheral circuits located in the peripheral circuit area 100b, such as high-voltage p-type metal oxide semiconductor transistors (hereinafter referred to as "HV pMOS") 102 and low-voltage n-type Metal oxide semiconductor transistor (hereinafter referred to as "LV nMOS") 103. The HV pMOS 102 includes a gate 102G and source/drain regions 102S/D. The gate 102G may optionally have a silicided metal feature 104. The source/drain regions 102S/D can also optionally have conductive features 105 (such as heavily doped regions or silicided metal). Similarly, LV nMOS 103 includes gate 103G and source/drain regions 103S/D. The gate 103G may optionally have a silicided metal feature 106. Source/drain The pole region 103S/D optionally has conductive features 105 (such as heavily doped regions or silicided metal). In the subsequent manufacturing process, a data storage structure will be formed on the memory array area 100a, which will be described in more detail below. In some embodiments, the precursor substrate 100 further includes one or more isolation structures 108, such as shallow trench isolation structures formed in the semiconductor substrate 101. The isolation structure 108 is formed between the memory array area 100a and the peripheral circuit area 100b, and separates the memory array area 100a and the peripheral circuit area 100b. In some embodiments, at least one isolation structure 108 is formed between the HV pMOS 102 and the LV nMOS 103, and separates the HV pMOS 102 and the LV nMOS 103. In some other embodiments, the precursor substrate 100 further includes a dielectric layer 109 covering the source/drain regions 102S/D and 103S/D on the memory array area 100a and the peripheral circuit area 100b, wherein the gate 102G and The gate 103G is exposed outside the dielectric layer 109, and the invention is not limited thereto.

FIGS. 3 and 4 illustrate a method for forming a first dielectric layer having a first through hole as described in step 12 in some embodiments of the present invention. Referring to FIG. 3, a dielectric material layer 110a is blanket-formed on the precursor substrate 100. According to some embodiments, the dielectric material layer 110a covers the memory array area 100a and the peripheral circuit area 100b. The dielectric material layer 110a can be formed by chemical vapor deposition (CVD) process, high density plasma chemical vapor deposition (high density plasma CVD) process, sub-atmospheric pressure vapor deposition (sub-atmospheric pressure CVD) process, spin It is formed by a spin-on dielectric (SOD) process or other suitable deposition techniques. In various examples, the dielectric material layer 110a may include, for example, silicon oxide or a suitable low dielectric constant material. Examples of low dielectric constant materials include Fluorinated silica glass (FSG), bisbenzo ring compound (BCB), carbon-doped silicon oxide, amorphous fluorinated carbon, polyimide, and/or other materials.

Referring to FIG. 4, according to some embodiments, the dielectric material layer 110a is selectively etched to form a first dielectric layer 110 having at least one first through-hole 111 (ie, one or more first through-holes 111); The first through-hole 111 penetrates the first dielectric layer 110. In some embodiments, the first through-hole 111 is formed in the peripheral circuit area 100b. In some embodiments, the first through-hole 111 is aligned with the gate 102G and the gate 103G, thereby exposing the gates 102G and 103G. For example, the metal silicide features 104, 106 of the gates 102G, 103G are exposed through the first through holes 111. In some embodiments, the first through-hole 111 further exposes the source/drain regions 102S/D and 103S/D. Although FIG. 4 shows a plurality of first through holes 111, the present invention is not limited to a plurality of first through holes. For example, forming a single first through hole 111 can still realize the present invention. In addition, the present invention is not limited to the method shown in FIGS. 3 and 4. Other suitable techniques may be used to form the first dielectric layer 110 having the first through holes 111.

The method 10 proceeds to step 14 of FIG. 1 and fills the first perforation with sacrificial material. As shown in FIG. 5, the first through hole 111 is filled with a sacrificial material 114. In some embodiments, a sacrificial material 114 is deposited to fill the first via 111 and cover the first dielectric layer 110, and then perform an etch-back process or a chemical mechanical polishing (CMP) process to remove the deposited on the first dielectric layer The excess material on 110 forms the sacrificial material 114 shown in FIG. 5. In some embodiments, the sacrificial material 114 filled in the first through-hole 111 is in contact with at least one of the gate electrodes 102G, 103G. For example, the metal silicide features 104 and/or metal silicide features 106 of the gates 102G and 103G are in contact The sacrifice material 114. In an embodiment where a plurality of first through holes 111 are formed, the sacrificial material 114 in the first through holes 111 may further contact the conductive features 105, 107 of the source/drain regions 102S/D, 103S/D. In some embodiments, the sacrificial material 114 is made of a dielectric material that can suppress or inhibit silicide diffusion. For example, the sacrificial material 114 may be made of silicon nitride or the like. The terms "made of" and "formed" used in this article mean "contains" or "consists of" in the sense. The sacrificial material 114 formed in this stage or step will provide specific technical effects for subsequent processes, which will be described in detail below.

The method 10 proceeds to step 16 of FIG. 1 to form a second dielectric layer having at least one second through hole above the first dielectric layer. There are various ways to implement step 16, and the following description in conjunction with FIGS. 6-11 is only an implementation or example, and the present invention is not limited thereto. In addition, other features and/or structures may be simultaneously formed during the formation of the second dielectric layer with the second through hole.

As shown in FIG. 6, according to some embodiments, a dielectric material layer 120 a is formed over the first dielectric layer 110 and the sacrificial material 114. In some embodiments, the dielectric material layer 120a further covers the first dielectric layer 110 in the memory array area 100a. In some embodiments, the dielectric material layer 120a seals the sacrificial material 114 in the first through-hole 111. In some other embodiments, the dielectric material layer 120a and the first dielectric layer 110 are made of the same material, but the material of the dielectric material layer 120a is different from the sacrificial material 114, for example, the first dielectric layer 110 and the dielectric material layer 120a include an oxide layer, and the sacrificial material 114 includes silicon nitride. In some other embodiments, the first dielectric layer 110 and the dielectric material layer 120a may be different materials, for example, one of them The silicon oxynitride is silicon oxide and the other is silicon oxide. The sacrificial material 114 includes silicon nitride, but the invention is not limited thereto. Referring to FIG. 7, in some embodiments, a portion of the first dielectric layer 110 and a portion of the dielectric material layer 120a are removed to expose the memory array area 100a. For example, an etching process may be used to remove part of the first dielectric layer 110 and part of the dielectric material layer 120a. Specifically, after removing the first dielectric layer 110 and the dielectric material layer 120a above the memory array region 100a, the main surface S of the memory array region 100a on the semiconductor substrate 101 is exposed.

Referring to FIG. 8, in some embodiments, a stacked structure 130 including a plurality of conductive layers 132 and a plurality of insulating layers 134 is formed on the memory array area 100a, where the conductive layers 132 and the insulating layers 134 are alternately stacked with each other. In some embodiments, the stacked structure 130 may include dozens to hundreds of conductive layers 132 and insulating layers 134. The conductive layer 132 may be formed of any suitable conductive material, such as a semiconductor material, a metal material, or a conductive material. For example, the semiconductor material is doped polysilicon or undoped polysilicon. The metal material includes titanium nitride, copper, tungsten, Platinum, the present invention is not limited to this, those skilled in the art can choose according to actual needs. The insulating layer 134 may be formed of any suitable dielectric material, such as silicon oxide or a low dielectric constant dielectric material. Examples of low dielectric constant materials include fluorinated silica glass (FSG), bisbenzocyclic compound (BCB), carbon-doped silicon oxide, amorphous fluorinated carbon, polyimide, and/or other materials.

Please refer to FIG. 9. In some embodiments, a plurality of data storage structures 140 are formed in the stacked structure 130. According to some embodiments, each data storage structure 140 extends along the direction D1. In other words, in these real In the embodiment, the length direction of the data storage structure 140 is substantially perpendicular to the main surface S of the memory array area 100a. In various embodiments, each data storage structure 140 includes a data storage layer 142, an insulating material 146, and a semiconductor layer 144 between the data storage layer 142 and the insulating material 146. For example, the data storage layer 142 may include an "ONO" structure (oxide-nitride-oxide), an "ONONO" structure (oxide-nitride-oxide-nitride-oxide), or "TANOS" Structure (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon). The semiconductor layer 144 may be made of polysilicon or other suitable semiconductor materials, for example. The insulating material 146 may be made of silicon oxide or a low dielectric constant material, for example. In some embodiments, the insulating material 146 and the insulating layer 134 (labeled in FIG. 8) are made of the same material. In addition, any conventional method can be used to form the data storage structure 140. In short, the stacked structure 130 is selectively etched first, and a plurality of trenches 138 are formed in the stacked structure 130, and then the data storage layer 142 is formed on the sidewalls of the trench 138. After that, the semiconductor layer 144 and the insulating material 146 are formed in the remaining space of the trench 138.

Referring to FIG. 10, in some embodiments, an interlayer dielectric layer 150 is formed above the data storage structure 140 on the memory array area 100a and above the dielectric material layer 120a on the peripheral circuit area 100b. The interlayer dielectric layer 150 may be formed using any conventional techniques and materials. In some embodiments, the thickness of the interlayer dielectric layer 150 is less than the total thickness of the first and second dielectric layers 110, 120.

Referring to FIG. 11, in some embodiments, the dielectric material layer 120a is selectively etched to form at least one second through hole 122 (ie, one or more second through holes 122) of the second dielectric layer 120, wherein the second through holes 122 expose the sacrificial material 114 within the first through holes 111. As described above, in the embodiment where the interlayer dielectric layer 150 is formed, the step of selectively etching the dielectric material layer 120a further includes selectively etching the interlayer dielectric layer 150 to form a plurality of first contact holes 151 and a plurality of Second contact hole 152. The first contact hole 151 exposes the data storage structure 140 on the memory array area 100a, and the second contact 152 communicates with the second through hole 122 on the peripheral circuit area 100b. In some embodiments, the etching process for forming the second through-hole 122 may substantially stop on the sacrificial material 114 or slightly etch the sacrificial material 114. Furthermore, the bottom width W2 of the second through hole 122 is smaller than the top width W1 of the first through hole 111. In some embodiments, the first and second perforations 111, 122 each have an aspect ratio of about 25 to about 50, such as 30, 35, 40, or 45. Although FIG. 11 shows a plurality of first through holes 111 and a plurality of second through holes 122, the present invention is not limited to a plurality of first through holes and a plurality of second through holes 122. For example, only forming a single first through hole 111 and a single second through hole 122 can still implement the present invention.

Although the foregoing and FIG. 11 illustrate that the second through-hole 122 is formed after forming the stacked structure 130, the data storage structure 140, and the interlayer dielectric layer 150, please note that the second through-hole 122 may be formed after forming the stacked structure 130, the data storage The structure 140 and/or the interlayer dielectric layer 150 were previously formed. In some embodiments, the second through hole 122 may be formed before the stacked structure 130 is formed. Specifically, in some embodiments, the second through hole 122 may be formed after the dielectric material layer 120 shown in FIG. 6 is formed. Alternatively, according to some other embodiments, the second through hole 122 may be the same as in the process shown in FIG. 7 Is formed, that is, etching a portion of the first dielectric layer 110 and a portion of the dielectric material layer 120a.

According to some other embodiments, although the stacked structure 130 and the data storage structure 140 described in FIGS. 8 and 9 are formed after steps 12 and 14, the stacked structure 130 and the data storage structure 140 may be formed before step 12 . For example, before forming the first dielectric layer 110 and/or peripheral circuits (for example, HV pMOS 102 and LV nMOS 103) on the precursor substrate 100, a stack structure 130 and data storage may be formed on the semiconductor substrate 101 Structure 140. In addition, according to other embodiments, even though FIGS. 9-11 show that the HV pMOS 102 and LV nMOS 103 are at a lower level than the top of the stacked structure 130 and the data storage structure 140, the HV pMOS 102 and LV nMOS 103 may be It is formed at a position higher than the top of the stacked structure 130 and the data storage structure 140.

Returning to FIG. 1, the method 10 proceeds to step 18, after forming the second dielectric layer having the second through hole, the sacrificial material is removed. As shown in FIG. 12, the sacrificial material 114 in the first through-hole 111 is removed. For example, the sacrificial material 114 can be removed by a wet etching process, where a hot phosphoric acid solution is used as an etchant. After removing the sacrificial material 114, the side walls 111a, 122a of the first and second through holes 111, 122 are exposed, and the second through hole 122 communicates with the first through hole 111. In some embodiments, after the sacrificial material 114 is removed, the silicided metal features 104, 106 of the gates 102G, 103G and the conductive features 105, 107 of the source/drain regions 102S/D, 103S/D via The first and second perforations 111, 122 are exposed.

Method 10 proceeds to step 20 of Figure 1, forming a barrier layer Lining the side wall of the first through hole and the side wall of the second through hole. As shown in FIG. 13, a barrier layer 160 lined on the side walls 111 a, 122 a of the first and second through holes 111, 122 is formed. In various embodiments, the barrier layer 160 continues from the side wall 111 a of the first through-hole 111 to the side wall 122 a of the second through-hole 122. Specifically, the barrier layer 160 has a sawtooth profile in the cross section along the height direction of the first and second through holes 111, 122. In some other embodiments, the barrier layer 160 is further formed at the bottom of the first through-hole 111, so that the barrier layer 160 contacts the metal silicide features 104, 106 and/or source/drain regions of the gate electrodes 102G, 103G Conductive features 105, 107 of 102S/D, 103S/D. In the embodiment where the first and second contact holes 151, 152 are formed in the interlayer dielectric layer 150, the barrier layer 160 is also lined in the first and second contact holes 151, 152. In various embodiments, the barrier layer 160 may be formed using an appropriate chemical vapor deposition process, such as a high-density plasma chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process, a flow chemical vapor deposition process, Or other suitable deposition techniques. In addition, the barrier layer 160 may also be referred to as an “adhesive layer”. In some embodiments, the barrier layer 160 may include titanium, titanium nitride, tantalum nitride, or a combination thereof or the like. In some other embodiments, the barrier layer 160 may include silicon nitride, silicon oxynitride (SiON), or a combination thereof or the like.

Method 10 proceeds to step 22 of FIG. 1 to form conductive material in the first and second through holes. Please continue to refer to FIG. 13 to form the conductive material 170 filled in the first and second through holes 111 and 122. Specifically, after the barrier layer 160 is lined with the first and second through holes 111 and 122, there is still space left in the first and second through holes 111 and 122. 170 conductive material Fill the remaining space of the first and second perforations 111, 122. In the embodiment where the interlayer dielectric layer 150 having the first and second contact holes 151, 152 is formed, the conductive material 170 is also filled in the first and second contact holes 151, 152. In various embodiments, the conductive material 170 may be formed of tungsten, aluminum, aluminum silicide, tungsten silicide, copper, or an alloy including tungsten, or the like.

According to some embodiments, the barrier layer 160 and the conductive material 170 may be formed using the following method. First, a layer of barrier material is deposited on the conformal carpet, so that the barrier material is deposited on the inner surfaces of the first and second through holes 111, 122 and the inner surfaces of the first and second contact holes 151, 152. The barrier material also covers the interlayer dielectric layer 150. Then, a layer of conductive material is deposited to fill the first and second through holes 111, 122 and the first and second contact holes 151, 152, and the conductive material is also deposited over the interlayer dielectric layer 150. Thereafter, a chemical mechanical polishing or etch-back process is performed to remove excess barrier material and conductive material deposited on the interlayer dielectric layer 150, thereby forming the barrier layer 160 and conductive material 170 shown in FIG.

The method disclosed herein provides various advantages in manufacturing processes and semiconductor devices. Specifically, this method is suitable for forming a contact hole with a high aspect ratio, for example, an aspect ratio greater than 30 or greater. In particular, the barrier layer 160 continuously extends from the side wall 111a of the first through-hole 111 to the second through-hole 122. The side wall 122a. Furthermore, no barrier layer is interposed in the conductive material 170. In addition, the method disclosed herein can prevent the conductive material 170 in the first and second through holes 111 and 122 from forming oxide because the conductive material 170 is formed using a single deposition process. Therefore, the electrical performance of the manufactured via contact structure is reliable, and the manufacturing process is robust (robust). Furthermore, please refer to FIG. 5, the sacrificial material 114 is formed in the first through-hole 111 on the silicided metal feature structure. During the subsequent process of forming the data storage structure 140 (see FIGS. 8-9 ), the sacrificial material 114 can Suppresses or eases the diffusion of silicide metal to the dielectric layer. The various advantages mentioned above and others can be more fully understood after referring to the comparative examples shown in FIGS. 17-24, which will be described in more detail below.

Another aspect of the present invention is to provide a through-hole contact structure. FIG. 14 is a schematic cross-sectional view of a through-hole contact structure 200 according to various embodiments of the present invention. The via contact structure 200 may be formed in a semiconductor device such as a memory device or other functional devices. For example, the via contact structure 200 is formed in the peripheral circuit area of the three-dimensional NAND flash memory. As shown in FIG. 14, the via contact structure 200 includes at least a first conductive structure 210, a second conductive structure 220 and a barrier layer 230.

According to some embodiments, the first conductive structure 210 is disposed above the conductive features 242 of the semiconductor substrate 240 and is aligned with the conductive features 242. The first conductive structure 210 includes a top 212 and a bottom 214, and the width and/or cross-sectional area of the top 212 is greater than the width and/or cross-sectional area of the bottom 214. The first conductive structure 210 has a long-axis direction D2 that is substantially perpendicular to the surface of the semiconductor substrate 240.

The second conductive structure 220 is disposed on the top 212 of the first conductive structure 210. In some embodiments, the second conductive structure 220 extends upward from the top 212 of the first conductive structure 210 along the long axis direction D2. The second conductive structure 220 has a bottom 222 that contacts the top 212 of the first conductive structure 210. The width and/or profile of the bottom 222 of the second conductive structure 220 The area is smaller than the width and/or cross-sectional area of the top 212 of the first conductive structure 210. Here, the term "cross-sectional area" of the top portion 212 and the bottom portion 222 is defined on a cross section perpendicular to the direction D2. Therefore, the partial portion 212a of the top portion 212 is not occupied by the bottom portion 222 of the second conductive structure 220. In some embodiments, the first and second conductive structures 210, 220 each have an aspect ratio of about 25 to about 50, such as 30, 35, 40, or 45.

The barrier layer 230 covers the sidewalls 210a and 220a of the first and second conductive structures 210 and 220. The barrier layer 230 further covers the unoccupied partial portion 212a in the top portion 212 of the first conductive structure 210. Please note that the barrier layer 230 extends continuously from the sidewall 210a of the first conductive structure 210, through the unoccupied partial portion 212a in the top portion 212, to the sidewall 220a of the second conductive structure 220. In various embodiments, the barrier layer 230 has a sawtooth profile in a cross-section along the direction D2 (also referred to as the “height direction”). In some embodiments, the barrier layer 230 also covers the bottom 214 of the first conductive structure 210.

According to some embodiments, the via contact structure 200 may be buried in the dielectric layers 250, 252 above the semiconductor substrate 240. In various embodiments, the dielectric layers 250, 252 surround the outer sidewalls of the barrier layer 230, wherein the barrier layer 230 surrounds the sidewalls of the first and second conductive structures 210, 220.

Another aspect of the present invention is to provide a memory device. FIG. 15 is a schematic cross-sectional view of a memory device 300 according to various embodiments of the present invention. The memory device 300 includes at least a semiconductor substrate 310, dielectric layers 317, 320, a barrier layer 330, and a conductive plug 340.

The semiconductor substrate 310 includes a memory array area 310a and a It is connected to the peripheral circuit area 310b of the memory array area 310a. According to some embodiments, although FIG. 15 only shows a portion of the memory device 300, the peripheral circuit area 310b may actually surround the memory array area 310a. The semiconductor substrate 310 further includes a peripheral circuit 312 located on the peripheral circuit area 310b. In some embodiments, the peripheral circuit 312 includes a transistor 314 (eg, HV pMOS or LV nMOS), and the transistor 314 has a gate 314G and source/drain regions 314S/D. In various embodiments, the metal silicide 316 may be formed in the gate 314G and/or the source/drain regions 314S/D of the transistor 314. A plurality of data storage structures are provided on the memory array area 310a, which will be described in detail below.

The dielectric layers 317 and 320 are arranged above the peripheral circuit 312. The dielectric layers 317 and 320 respectively have a first hole 321 and a second hole 322. The second hole 322 is located above the first hole 321 and connected to the first hole 321. FIG. 16A shows an enlarged view of the area R in FIG. 15. FIG. 16B is a schematic plan view of the first hole 321 and the second hole 322 along the cutting plane C in the region R. FIG. As shown in FIGS. 16A and 16B, the second hole 322 has a bottom width W2 and a bottom area 322B. The bottom width W2 and the bottom area 322B are smaller than the top width W1 and the top area 321T of the first hole 321, respectively, because the dielectric layer 320 An overhang 324 is formed at the connection between the first hole 321 and the second hole 322. In various embodiments, the overhanging portion 324 has a bottom surface 324 b that extends from the side wall 321 a of the first hole 321 to the side wall 322 a of the second hole 322. According to some embodiments, the dielectric layers 317, 320 each have a plurality of first holes 321 and a plurality of second holes 322, as shown in FIG. Each second hole 322 is located above a corresponding first hole 321 and is connected to the corresponding first hole; each first hole 321 and each second hole 322 have a structure similar to or the same as that shown in FIGS. 16A and 16B .

The barrier layer 330 is continuously lined with the side walls 321a, 322a and the overhanging portion 324 of the first and second holes 321, 322. Specifically, the barrier layer 330 continuously extends from the side wall 321 a of the first hole 321 to the side wall 322 a of the second hole 322 via the bottom surface 324 b of the overhang 324. The barrier layer 330 only partially fills the first and second holes 321 and 322, so there is still space left in the first and second holes 321 and 322. For example, the thickness of the barrier layer 330 is tens of angstroms to tens of nanometers. In some embodiments, as shown in FIG. 15, the barrier layer 330 has a sawtooth profile in a cross section along the height direction D3 of the first and second holes 321 and 322. In some other embodiments, the barrier layer 330 is also formed at the bottom of the first hole 321, so the barrier layer 330 contacts the metal silicide 316 on the transistor 314. According to some embodiments, although the barrier layer 330 is illustrated as a single layer in FIGS. 15 and 16A, please note that the barrier layer 330 may include multiple sub-layers or sub-layers (composite layers) so that the barrier layer 330 has The dual function of the adhesive layer and the barrier layer. Therefore, the barrier layer 330 may also be referred to as an “adhesive layer”.

The conductive plug 340 is filled in the first hole 321 and the second hole 322. In some embodiments, the conductive plug 340 fills the remaining space of the first hole 321 and the second hole 322. Although FIGS. 15, 16A, and 16B show that only the barrier layer 330 and the conductive plug 340 are formed in the first hole 321 and the second hole 322, other layer structures may be formed between the barrier layer 330 and the conductive plug 340. In some embodiments, the barrier layer 330 covers the conductive plug 340 except for the top of the conductive plug 340. According to some other embodiments, the conductive plug 340 is aligned with the metal silicide 316 on the peripheral circuit 312. In the embodiment where the dielectric layers 317 and 320 each have a plurality of first holes 321 and a plurality of second holes 322, The memory device 300 includes a plurality of conductive plugs 340. Each conductive plug 340 is filled in the corresponding first hole 321 and second hole 322. Therefore, some conductive plugs 340 are connected to the gate 314G of the transistor 314, and some conductive plugs 340 are connected to the source/drain regions 314S/D of the transistor 314. Exemplary materials of the conductive plug 340 include tungsten, aluminum, aluminum silicide (AlSi), tungsten silicide (WSi), copper, or the like.

In some embodiments, the memory device 300 further includes a stacked structure 350 located on the memory array area 310a. The stacked structure 350 includes a plurality of conductive layers 352 and a plurality of insulating layers 354 that are alternately stacked on each other. The implementation of the stacking structure 350 may be the same as or similar to the stacking structure 130 described above with reference to FIG. 8, and thus will not be repeated.

In some embodiments, the memory device 300 further includes a plurality of data storage structures 360 located on the memory array area 310a. According to some embodiments, each data storage structure 360 penetrates the stacked structure 350. The implementation of the data storage structure 360 may be the same as or similar to the data storage structure 140 described above with respect to FIG. 9, and thus will not be repeated.

In other embodiments, the memory device 300 further includes an interlayer dielectric layer 380 on the dielectric layer 320. According to some embodiments, the interlayer dielectric layer 380 has a plurality of first contact holes 381 and a plurality of second contact holes 382. In some embodiments, the barrier layer 330 lines the inner surfaces of the first contact hole 381 and the second contact hole 382. In some other embodiments, each first contact hole 381 is aligned with a corresponding data storage structure 360. According to some other embodiments, the memory device 300 further includes a contact plug 384 filling the remaining space of the first contact hole 381. In an embodiment, each second contact The hole 382 is connected to a corresponding second hole 322 in the dielectric layer 320, so the conductive plug 340 is also filled in the second contact hole 382.

17-24 are schematic cross-sectional views of a method for forming a semiconductor structure according to a comparative example of the present invention. Those of ordinary skill in the art to which the present invention pertains can more clearly understand the various advantages of the present disclosure after comparing the method illustrated in FIGS. 17-24 with the embodiments of the present invention.

In FIG. 17, the first dielectric layer 410 is formed on the precursor substrate 400. The precursor substrate 400 includes a semiconductor substrate 401 having a memory array area 400a and a peripheral circuit area 400b adjacent to the memory array area 400a. The precursor substrate 400 further includes HV pMOS 402 and LV nMOS 403 on the peripheral circuit area 400b. The HV pMOS 402 includes a gate 402G and source/drain regions 402S/D. Similarly, LV nMOS 403 includes gate 403G and source/drain regions 403S/D. The formed first dielectric layer 410 has a plurality of first through holes 411. Some first through holes 411 expose the gate electrodes 402G, 403G, while other first through holes 411 expose the source/drain regions 402S/D, 403S/D. After that, a first barrier material 420" is deposited to surround the first through hole 411 and cover the first dielectric layer 410, and then a first conductive material 430" is deposited on the first barrier material 420" and fills the first through hole 411 .

In FIG. 18, an etch back process or a chemical mechanical polishing process is performed to remove excess material deposited on the first dielectric layer 410. Therefore, the first barrier layer 420 formed in the first through hole 411 and the plurality of first conductive plugs 430 are filled in the first through hole 411.

In FIG. 19, a second dielectric layer 440 is formed to cover the first dielectric layer 410, the first barrier layer 420, and the first conductive plug 430.

In FIG. 20, portions of the first and second dielectric layers 410, 440 are removed to expose the memory array area 400a. The remaining first and second dielectric layers 410 and 440 still partially cover the peripheral circuit area 400b.

In FIG. 21, a stacked structure 450 including a plurality of conductive layers 452 and a plurality of insulating layers 454 is formed on the memory array region 400a, where the conductive layers 452 and the insulating layers 454 are alternately stacked with each other. In the process of forming the stacked structure 450, a plurality of wires 456 are simultaneously formed. Each wire 456 is connected to a corresponding conductive layer 452.

In FIG. 22, a plurality of data storage structures 460 are formed in the stacked structure 450. Each data storage structure 460 includes a data storage layer 462, an insulating material 464, and a semiconductor layer 464 between the data storage layer 462 and the insulating material 464.

In FIG. 23, an interlayer dielectric layer 470 is blanket formed to cover the second dielectric layer 440, the stack structure 450, and the data storage structure 460. After that, the interlayer dielectric layer 470 and the second dielectric layer 440 are etched, and the first contact hole 471 and the second contact hole 472 are formed in the interlayer dielectric layer 470 and the second contact layer 440 is formed in the second dielectric layer 440 Perforated 442. The first contact hole 471 exposes the data storage structure 460. The second contact hole 472 is located in the peripheral circuit area 400b. The second through hole 442 penetrates through the second dielectric layer 440. The second contact hole 472 is aligned with and communicates with the second through hole 442 to expose the first conductive plug 430.

In FIG. 24, the second barrier layer 480 is formed to line the inner surfaces of the first and second contact holes 471, 472 and the second through hole 442. Then, a second conductive material is deposited to fill the first and second contact holes 471, 472 to And the remaining space of the second through hole 442, so that the contact plug 491 is formed in the first contact hole 471, and the second conductive plug 492 is formed in the second through hole 442 and the second contact hole 472.

FIG. 25 shows an enlarged view of the area M in FIG. 24. As shown in the figure, please note that the first barrier layer 420 does not physically contact the second barrier layer 480. Specifically, a portion of the top portion 430a of the first conductive plug 430 is not covered by any first barrier layer 420 or second barrier layer 480, which will cause the reliability of the contact structure to decrease. In addition, the bottom 480 a of the second barrier layer 480 is interposed between the first conductive plug 430 and the second conductive plug 492. The bottom 480a constructs an additional interface between the first and second conductive plugs 430, 492, which also reduces the performance and reliability of the overall contact structure. Furthermore, please return to FIG. 18, when an etch-back process or a chemical mechanical polishing process is performed to remove excess material deposited on the first dielectric layer 410, the top 430a of the first conductive plug 430 is exposed to air ( It contains oxygen), so the top 430a will form undesirable oxides. In order to ensure the conductivity of the first conductive plug 430 and avoid various problems in the subsequent process, before forming the second dielectric layer 440 shown in FIG. 19, an additional etching process must be performed to remove the oxide on the top 430a .

According to various embodiments of the present invention, various disadvantages of the above-mentioned comparative examples can be solved. Returning to FIG. 14, the barrier layer 230 covers the sidewalls 210 a and 220 a of the first and second conductive structures 210 and 220, and further covers the unoccupied partial portion 212 a of the top 212 of the first conductive structure 210. Please note that the barrier layer 230 extends from the side wall 210a of the first conductive structure 210, through the unoccupied partial portion 212a of the top 212, to the side wall of the second conductive structure 220 220a is continuous. In addition, no barrier layer is interposed between the first and second conductive structures 210, 220. Furthermore, the first and second conductive structures 210 and 220 are formed using a single deposition step. Therefore, the embodiments of the present invention solve all the disadvantages of the comparative example.

Although the present invention has been disclosed as above in an embodiment, it is not intended to limit the present invention. Anyone who is familiar with this art can make various modifications and retouching without departing from the spirit and scope of the present invention, so the protection of the present invention The scope shall be as defined in the appended patent application scope.

10‧‧‧Method

12, 14, 16, 18, 20, 22 ‧‧‧ steps

Claims (10)

A method of forming a semiconductor structure includes: forming a first dielectric layer having a first through hole on a precursor substrate, the first through hole penetrating the first dielectric layer; filling a sacrificial material in the first through hole Forming a second dielectric layer with a second through hole above the first dielectric layer, the second through hole exposing the sacrificial material in the first through hole, wherein the second through hole has a bottom width, the bottom The width is smaller than a top width of the first through hole, and the first through hole and the second through hole at least partially overlap in a direction perpendicular to the precursor substrate; after forming the second dielectric layer with the second through hole, move Removing the sacrificial material; forming a barrier layer lining a side wall of the first through hole and a side wall of the second through hole; and forming a conductive material in the first and second through holes. The method of claim 1, wherein the barrier layer continuously extends from the side wall of the first through hole to the side wall of the second through hole. The method of claim 1, wherein the barrier layer has a sawtooth profile in a cross-section along a height direction of the first and second through holes. The method of claim 1, wherein the precursor substrate includes a memory array area and a peripheral circuit adjacent to the memory array area Road area, and the first and second through holes and the sacrificial material are formed in the peripheral circuit area. The method of claim 1, wherein forming the second dielectric layer having the second through hole above the first dielectric layer comprises blanket depositing a layer of dielectric material on the first dielectric layer and Above the sacrificial material; and selectively etching the dielectric material layer to form the second through hole. The method according to claim 5, after depositing the dielectric material layer, but before selectively etching the dielectric material layer to form the second through hole, further comprising removing a portion of the first dielectric layer and a portion The dielectric material layer to expose the memory array area. A through-hole contact structure for a semiconductor device, comprising: a first conductive structure with a top; a second conductive structure with a bottom, the bottom is in contact and arranged on the top of the first conductive structure, wherein The bottom of the second conductive structure has a width that is less than a width of the top of the first conductive structure, so that a portion of the top of the first conductive structure is not occupied by the bottom of the second conductive structure; and a The barrier layer covers a side wall of the first conductive structure and a side wall of the second conductive structure, and the barrier layer is continuous from the side wall of the first conductive structure through the unoccupied portion of the top Extend to the second The side wall of the conductive structure. The through hole contact structure according to claim 7, wherein the barrier layer has a sawtooth profile in a cross section along a height direction of the first and second conductive structures. A memory device includes: a semiconductor substrate including a memory array area and a peripheral circuit adjacent to the memory array area; a dielectric layer disposed above the peripheral circuit, the dielectric layer having a first A hole and a second hole connected to and located above the first hole, wherein a bottom width of the second hole is smaller than a top width of the first hole, so that the dielectric layer is in the first hole An overhang is formed at the connection with the second hole; a barrier layer continuously extends from a side wall of the first hole to a side wall of the second hole through the overhang; and a conductive plug, Filled in the first hole and the second hole. The memory device according to claim 9, further comprising: a stacked structure located in the memory array area, the stacked structure including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other: and a plurality of data storage structures located in In the memory array area, each of the data storage structures penetrates the stacked structure.

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