TWI817325B - Semiconductor device structure with silicide portion between conductive plugs and a method for preparing the same - Google Patents

Abstract

The present disclosure provides a semiconductor device structure with a silicide portion between conductive plugs and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first conductive plug disposed in the first dielectric layer, and a second conductive plug disposed in the second dielectric layer and directly over the first conductive plug. The semiconductor device structure further includes a silicide portion disposed between the first conductive plug and the second conductive plug.

Description

Semiconductor element structure with silicide portion between multiple conductive plugs and preparation method thereof

This application claims the priority and benefits of U.S. Patent Application Nos. 17/520,991 and 17/522,324 (priority dates are "November 8, 2021" and "November 9, 2021"), which The contents of the US application are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device structure and a manufacturing method thereof. In particular, it relates to a semiconductor element structure having a silicide portion between a plurality of conductive plugs and a manufacturing method thereof.

For many modern applications, semiconductor components are indispensable. With the advancement of electronic technology, the size of semiconductor components is becoming smaller and smaller, while providing better functions and containing a larger number of integrated circuits. Due to the miniaturization of the specifications of semiconductor components, different types and sizes of semiconductor components that implement different functions are integrated and packaged in a single module. Furthermore, many manufacturing steps are performed on the integration of various types of semiconductor devices.

However, the fabrication and integration of these semiconductor devices involves many complex steps and operations. Integration into these semiconductor devices is becoming increasingly complex. Increased complexity in the fabrication and integration of these semiconductor devices can create a number of defects. Accordingly, there is a need to continuously improve the manufacturing process of these semiconductor devices in order to cope with these defects and enhance their performance.

The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. should not be used as any part of this case.

An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first dielectric layer disposed on a semiconductor substrate; and a second dielectric layer disposed on the first dielectric layer. The semiconductor device also includes a first conductive plug disposed in the first dielectric layer; and a second conductive plug disposed in the second dielectric layer directly above the first conductive plug. The semiconductor element further includes a silicone portion disposed between the first conductive plug and the second conductive plug.

In one embodiment, the silicone portion directly contacts the first conductive plug and the second conductive plug. In one embodiment, a width of the silicone portion is substantially the same as a width of the second conductive plug. In one embodiment, the semiconductor device structure further includes a liner to separate the first conductive plug from the first dielectric layer and the semiconductor substrate. In one embodiment, the liner directly contacts the silicone portion. In one embodiment, the semiconductor device structure further includes a polysilicon layer disposed between the first dielectric layer and the second dielectric layer.

In one embodiment, the silicone portion is surrounded by the polycrystalline silicon layer. In one embodiment, the silicone portion directly contacts the polycrystalline silicon layer. In one embodiment, the semiconductor device structure further includes a third conductive plug surrounded by the first dielectric layer, the polysilicon layer and the second dielectric layer, wherein the first conductive plug, the second conductive plug The plug and the silicone portion are disposed in a dense pattern area, and the third conductive plug is disposed in a sparse pattern area. In one embodiment, a width of the third conductive plug is greater than a width of the second conductive plug.

Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first dielectric layer disposed in a semiconductor substrate; and a polycrystalline silicon layer disposed on the first dielectric layer. The semiconductor device structure also includes a second dielectric layer disposed on the polysilicon layer; and a first conductive plug disposed in the first dielectric layer. The semiconductor device structure also includes a silicide portion disposed in the polycrystalline silicon layer and covering the first conductive plug; and a second conductive plug disposed in the second dielectric layer and covering the silicide portion.

In one embodiment, the second conductive plug directly contacts the silicone portion, and an upper surface area of the silicone portion is substantially the same as a lower surface area of the second conductive plug. In one embodiment, the silicone portion is surrounded by the polycrystalline silicon layer and directly contacts the polycrystalline silicon layer. In one embodiment, the polysilicon layer directly contacts the first dielectric layer and the second dielectric layer. In one embodiment, the semiconductor device structure further includes a liner to separate the first conductive plug from the first dielectric layer.

In one embodiment, the liner and the first conductive plug together form a conductive structure, and a width of the conductive structure is substantially the same as a width of the silicone portion. In one embodiment, an upper surface of the liner directly contacts the lower surface of the silicone portion. In one embodiment, the semiconductor device structure further includes a third conductive plug surrounded by the first dielectric layer, the polysilicon layer and the second dielectric layer, wherein the third conductive plug has a width greater than the A width of the second conductive plug. In one embodiment, the first conductive plug, the second conductive plug, and the silicone portion are disposed in an array area, and the third conductive plug is disposed in a surrounding circuit area.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device structure. The semiconductor device structure and preparation method include forming a first dielectric layer on a semiconductor substrate; and forming a first conductive plug in the first dielectric layer. The preparation method includes forming a polycrystalline silicon layer to cover the first dielectric layer and the first conductive plug; and converting a portion of the polycrystalline silicon layer into a silicon compound portion. The preparation method also includes forming a second conductive plug directly on the silicone portion; and forming a second dielectric layer to surround the second conductive plug.

In one embodiment, the transforming includes performing a heat treatment process on the polysilicon layer. In one embodiment, the portion of the polysilicon layer directly contacts the first conductive plug. In one embodiment, the silicone portion is covered by the second conductive plug before the second dielectric layer is formed. In one embodiment, after the second conductive plug is formed, the second dielectric layer is formed on and contacts a remaining portion of the polysilicon layer. In one embodiment, the preparation method further includes forming a first opening through the first dielectric layer to expose the semiconductor substrate; and forming a lining material on the first dielectric layer and lining the first dielectric layer. First to speak. In addition, the preparation method includes forming a conductive material on the lining material and filling the first opening; and planarizing the lining material and the conductive material to form a pad to connect the first conductive plug and the first opening. The first dielectric layer is separated from the semiconductor substrate.

In one embodiment, the liner is covered by the polycrystalline silicon layer before the portion of the polycrystalline silicon layer is transformed. In one embodiment, the liner is covered by the silicone portion after the portion of the polycrystalline silicon layer is transformed. In one embodiment, the preparation method further includes forming a second opening through the first dielectric layer, the polysilicon layer and the second dielectric layer to expose the semiconductor substrate; and forming a third conductive plug. in this second opening. In one embodiment, the first opening is disposed in a dense pattern area, and the second opening is disposed in a sparse pattern area. In one embodiment, a width of the second opening is greater than a width of the first opening.

The present disclosure provides some embodiments of a semiconductor device structure and a manufacturing method thereof. In some embodiments, the semiconductor device structure has a first conductive plug, a second conductive plug, and a silicone portion. The second conductive plug is disposed directly above the first conductive plug, and the silicone portion is disposed on the first conductive plug. between the first conductive plug and the second conductive plug. The process of forming the two conductive plugs can help eliminate the problem of overhangs caused by the difficulty of filling a high aspect ratio opening structure.

Furthermore, the second conductive plug is formed on the silicone portion through a self-aligned process, and the second conductive plug is formed before the surrounding dielectric layer is formed. Therefore, there is no need to etch the dielectric layer surrounding the second conductive plug. Accordingly, the likelihood of gap formation between the conductive plugs and the surrounding dielectric layers may be reduced, and the risk of misalignment between the first conductive plugs and the second conductive plugs may be avoided. Therefore, the performance, reliability and yield of the semiconductor device structure can be improved.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. An embodiment such that the first and second components are not in direct contact. In addition, embodiments of the present disclosure may repeat reference numbers and/or letters in many examples. These repetitions are for simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed unless otherwise specified herein.

In addition, for ease of explanation, spaces such as "beneath", "below", "lower", "above", "upper", etc. may be used in this article. Relative terms are used to describe the relationship of one element or feature shown in the figures to another (other) element or feature. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

1 and 2 are schematic cross-sectional views illustrating intermediate stages of a process of forming a semiconductor device structure 100 according to a comparative example. In this comparative example, a semiconductor substrate 101 is provided, a first dielectric layer 103 and conductive plugs 105a, 105b surrounded by the first dielectric layer 103 are disposed on the semiconductor substrate 101, and a second dielectric layer 107 is disposed on the first dielectric layer 103 .

Furthermore, the structure of FIG. 1 has a sparse pattern area A (eg, surrounding circuit area) and a dense pattern area B (eg, column area). An opening 111a passing through the first dielectric layer 103 and the second dielectric layer 107 is provided in the sparse pattern area A, while the openings 110b and 110c passing through the second dielectric layer 107 are provided in the pattern dense area B. The conductive plug 105a is exposed through the opening 110b, and the conductive plug 105b is exposed through the opening 110c. In order to make this disclosure clear, the dotted line in the middle of FIG. 1 is used to represent the boundary between the sparse pattern area A and the pattern dense area B.

During the process of forming openings 110a, 110b, 110c, some degree of bit alignment may occur due to variations in overlay bit alignment offset defects during the lithography process. The variation of the migration defect results in the formation of gaps G1, G2, G3 surrounding the conductive plugs 105a, 105 as shown in Figure 1. Then, as shown in FIG. 2 , pads 113a, 113b, 113c and conductive plugs 115a, 115b, 115c are formed in the openings 110a, 110b, 110c. Since the gaps G1, G2, and G3 are too small to be filled, the gaps G1, G2, and G3 are sealed in the semiconductor device structure 100, which may degrade device performance.

FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device structure 200 according to different embodiments of the present disclosure. As shown in FIG. 3 , according to some embodiments, a semiconductor device structure 200 includes a semiconductor substrate 201 and a first dielectric layer 203 disposed on the semiconductor substrate 201 . In addition, according to some embodiments, the semiconductor device structure 200 includes a polysilicon layer 221 and a second dielectric layer 225. The polysilicon layer 221 is disposed on the first dielectric layer 203, and the second dielectric layer 225 is disposed on the polysilicon layer 221. .

In some embodiments, the semiconductor device structure 200 has a sparse pattern region A and a dense pattern region B. The sparse pattern area A can also be expressed as a surrounding circuit area, and the pattern dense area B can also be expressed as an array area. In the sparse pattern area A, the semiconductor device structure 200 includes a conductive structure 239a surrounded by the first dielectric layer 203, the polysilicon layer 221 and the second dielectric layer 225.

In some embodiments, the conductive structure 239a includes a conductive plug 237a and a liner 235a surrounding the conductive plug 237a. In some embodiments, the conductive plug 237a is disposed in the first dielectric layer 203 and passes through the polysilicon layer 221 and the second dielectric layer 225. In some embodiments, the lower surface and sidewalls of the conductive plug 237a are covered by pads 235a, so that the conductive plug 237a connects the semiconductor substrate 201, the first dielectric layer 203, the polycrystalline silicon layer 221 and the third layer through the pads 235a. Two dielectric layers 225 separate them.

In the pattern-dense area B, the semiconductor element structure 200 includes conductive structures 219a, 219b, silicide portions 221a, 221b, and conductive plugs 223a, 223b. The conductive structures 219a, 219b are disposed in the first dielectric layer 203, and the silicide portion 221a , 221b are disposed in the polycrystalline silicon layer 221 and directly on the conductive structures 219a, 219b, and the conductive plugs 223a, 223b are disposed in the second dielectric layer 225 and directly on the silicone portions 221a, 221b. In some embodiments, the conductive structure 219a includes a conductive plug 217a and a liner 215a surrounding the conductive plug 217a, and the conductive structure 219b includes a conductive plug 217b and a liner 215b surrounding the conductive plug 217b. In some embodiments, the lower surface and sidewalls of the conductive plug 217a are covered by pads 215a, so that the conductive plug 217a is separated from the semiconductor substrate 201 and the first dielectric layer 203 by the pads 215a.

Furthermore, in some embodiments, the lower surface and sidewalls of the conductive plug 217b are covered by pads 215b, so that the conductive plug 217b is separated from the semiconductor substrate 201 and the first dielectric layer 203 by the pads 215b. . In some embodiments, the conductive plug 223a is electrically connected to the conductive structure 219a via the silicone portion 221a, and the conductive plug 223b is electrically connected to the conductive structure 219b via the silicone portion 221b.

In some embodiments, the conductive plug 239a in the sparse pattern area A has a width W1, the conductive plug 223a in the pattern dense area B has a width W2, and the conductive plug 223b in the pattern dense area B has a width W3. In some embodiments, width W2 is approximately the same as width W3, and width W1 is greater than each of widths W2 and W3. In the context of this disclosure, the word "substantially" means that the better is 90%, the better is 95%, the still better is 98%, and the best is 99%.

In some embodiments, semiconductor device structure 200 is a dynamic random access memory (DRAM). In this case, the conductive structures 219a, 219b and the conductive plugs 223a, 223b may serve as bit line (BL) contact plugs, capacitor contact plugs, and/or interconnect structures that provide vertical electrical conduction paths in the DRAM structure.

4 is a schematic flowchart illustrating a method 10 for manufacturing a semiconductor device structure (eg, a semiconductor device structure 200 ) according to different embodiments of the present disclosure. According to some embodiments, the manufacturing method 10 includes steps S11, S13, S15, S17, S19, and S21. , S23. Steps S11 to S23 of Figure 4 are described in conjunction with the following figures, which are, for example, Figures 5 to 19.

5 to 19 are schematic cross-sectional views illustrating different intermediate stages during the formation of the semiconductor device structure 200 according to different embodiments of the present disclosure. As shown in FIG. 5 , a semiconductor substrate 201 is provided. The semiconductor substrate 201 may be a semiconductor wafer, such as a silicon wafer.

Additionally or additionally, the semiconductor substrate 201 may include elemental semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium and/or diamond. Examples of compound semiconductor materials may include silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or antimonide Indium (indium antimonide), but not limited to this. Examples of alloy semiconductor materials may include silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide ( GaInP) and/or gallium indium arsenide phosphide (GaInAsP), but is not limited to this.

In some embodiments, the semiconductor substrate 201 includes an epitaxial layer. For example, the semiconductor substrate 201 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 201 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer and a semiconductor layer, and the buried oxide layer The physical layer is on the substrate, the semiconductor layer is on the buried oxide layer, and the insulator-on-semiconductor substrate is such as a silicon-on-insulator (SOI) substrate or a silicon-on-insulator (silicon germanium). -on-insulator, SGOI) substrate or an insulator-on-insulator (germanium-on-insulator, GOI) substrate. The semiconductor-on-insulator substrate can be manufactured using separation by implanted oxygen (SIMOX), wafer bonding, and/or other applicable methods.

According to some embodiments, as shown in FIG. 5 , a first dielectric layer 203 is formed on the semiconductor substrate 201 . The corresponding steps are shown in step S11 in the method 10 shown in FIG. 4 . In some embodiments, the first dielectric layer 203 includes silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant dielectric material, or other suitable materials. The manufacturing technology of the first dielectric layer 203 may include a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and a spin coating process. or other suitable method.

Next, in some embodiments, as shown in FIG. 6 , a patterned mask 205 having openings 210a, 210b is formed on the first dielectric layer 203. In some embodiments, the openings 210a and 210b are disposed in the pattern-dense region B, so that the portion of the first dielectric layer 203 in the pattern-dense region B is partially exposed through the openings 210a and 210b. In some embodiments, the portion of the first dielectric layer 203 in the sparse pattern region A is completely covered by the patterned mask 205 . In addition, the opening 210a has a width W2, and the opening 210b has a width W3. In some embodiments, width W2 is approximately the same as width W3.

Then, according to some embodiments, as shown in FIG. 7 , an etching process is performed on the first dielectric layer 203 using the patterned mask 205 as a mask, so that the openings 212 a and 212 b are formed on the first dielectric layer 203 . in the electrical layer 203. In some embodiments, the openings 212a, 212b pass through the first dielectric layer 203 to expose the semiconductor substrate 201. The etching process may be a wet etching process, a dry etching process, or combinations thereof.

Since the fabrication technique of openings 212a, 212b may include transferring the pattern into the patterned mask 205, the width of opening 212a is approximately the same as the width W2 of opening 210a, and the width of opening 212b is approximately the same as the width of opening 210b. In some embodiments, openings 212a, 212b have the same width. After openings 212a, 212b are formed, patterned mask 205 can be removed.

Next, according to some embodiments, as shown in FIG. 8 , a lining material 215 is formed on the first dielectric layer 203 and lines the openings 212a and 212b. In some embodiments, lining material 215 includes Ti, TiN, Ta, TaN, CoW, other suitable materials, or combinations thereof. Furthermore, the manufacturing technology of the lining material 215 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a metal organic chemical vapor deposition (MOCVD) process, a sputtering process, and a plating process. or other suitable processes.

Next, according to some embodiments, as shown in Figure 9, a conductive material 217 is formed on the lining material 215 and fills the openings 212a, 212b. In some embodiments, conductive material 217 includes Cu, Al, W, Ti, Ta, Au, Ag, other suitable materials, or combinations thereof. Some of the processes used to form the conductive material 217 are similar or identical to the processes used to form the lining material 215, and detailed descriptions thereof will not be repeated herein.

Then, according to some embodiments, as shown in FIG. 10 , a planarization process is performed on the lining material 215 and the conductive material 217 until the first dielectric layer 203 is exposed. In some embodiments, conductive structures 219a (including a liner 215a and a conductive plug 217a) and 219b (including a liner 215b and a conductive plug 217b) are formed in the pattern dense area B after performing a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process. The corresponding steps are shown in step S13 in the method 10 shown in FIG. 4 .

Next, according to some embodiments, as shown in FIG. 11 , a polysilicon layer 221 is formed on the first dielectric layer 203 and covers the conductive structures 219a and 219b. The corresponding steps are shown in step S15 in the method 10 shown in FIG. 4 . In some embodiments, the polycrystalline silicon layer 221 covers the pattern-dense region A and the pattern-sparse region B. In some embodiments, the manufacturing technology of the polycrystalline silicon layer 221 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process, or other suitable methods.

Next, according to some embodiments, as shown in FIG. 12 , a heat treatment process is performed on the polycrystalline silicon layer 221 to transform portions of the polycrystalline silicon layer 221 into silicide portions 221 a and 221 b. In some embodiments, silicone portions 221a, 221b are formed in the pattern-dense region B. The corresponding steps are shown in step S17 in the method 10 shown in FIG. 4 .

In some embodiments, due to the reaction between the conductive structures 219a, 219b and the material of the polycrystalline silicon layer 221, the polycrystalline silicon layer 221 is covered by the conductive structures 219a, 219b and directly contacts some portions of the conductive structures 219a, 219b through the heat treatment process 220 And converted into silicone parts 221a and 221b. In some embodiments, after the heat treatment process, the silicone portion 221a has an upper surface area TS1, and the silicone portion 221b has an upper surface area TS2.

Then, according to some embodiments, as shown in Figure 113, conductive plugs 223a, 223b are formed directly on the silicone portions 221a, 221b. The corresponding steps are shown in step S19 in the method 10 shown in FIG. 4 . In some embodiments, the silicone portion 221a is disposed between the conductive structure 219a and the conductive plug 223a and directly contacts the conductive structure 219a and the conductive plug 223a, while the silicone portion 221b is disposed between the conductive structure 219b and the conductive plug 223b and directly contacts the conductive structure 219a and the conductive plug 223a. Contact conductive structure 219b and conductive plug 223b.

In some embodiments, the material of the conductive plugs 223a, 223b includes Cu, Al, W, Ti, Ta, Au, Ag, other suitable materials, or combinations thereof. In some embodiments, the manufacturing technology of the conductive plugs 223a and 223b may include a deposition process, such as a CVD process, a PVD process, an ALD process, a MOCVD process, a sputtering process, a plating process, or other suitable processes. process.

In some embodiments, the deposition process that forms conductive plugs 223a, 223b is selective such that they are deposited on silicone portions 221a, 221b, but not on silicone portion 221 (eg, after thermal treatment process 220). the remaining portion of the polycrystalline silicon layer 221). This selective deposition process can be achieved because the silicide portions 221a and 221b have a higher tendency to absorb or react with the metal material of the conductive plugs 223a and 223b than the polycrystalline silicon layer 221. Therefore, the conductive plugs 223a and 223b are formed with a plurality of openings therebetween, and the polycrystalline silicon layer 221 is exposed through the openings.

In some embodiments, the width of the silicone portion 221a is approximately the same as the width of the conductive plug 223a, and the width of the silicone portion 221b is approximately the same as the width of the conductive plug 223b. In some embodiments, conductive plug 223a has a lower surface area BS1 and conductive plug 223b has a lower surface area BS2. Please refer to Figures 12 and 13. According to some embodiments, the upper surface area TS1 of the silicone portion 221a is substantially the same as the lower surface area BS1 of the conductive plug 223a, and the upper surface area TS2 of the silicone portion 221b is substantially the same as the lower surface area of the conductive plug 223b. BS2.

Next, as shown in FIG. 14 , a second dielectric layer 225 is formed to cover the polysilicon layer 221 and the conductive plugs 223a and 223b. In some embodiments, the plurality of openings between conductive plugs 223a and 223b are completely filled with the second dielectric layer 225. Some materials and processes used to form the second dielectric layer 225 are similar or identical to those used to form the first dielectric layer 203 , and their detailed description will not be repeated herein.

Basically, according to some embodiments, as shown in FIG. 15 , a planarization process is performed on the second dielectric layer 225 to expose the conductive plugs 223a, 223b. The planarization process may include a CMP process. In some embodiments, each sidewall of the conductive plugs 223a, 223b is surrounded by the second dielectric layer 225. The corresponding steps are shown in step S21 in the method 10 shown in FIG. 4 .

Then, according to some embodiments, as shown in FIG. 16 , a patterned mask 227 having an opening 230 is formed on the second dielectric layer 225 . In some embodiments, the opening 230 is disposed in the sparse pattern region A, such that the portion of the second dielectric layer 225 in the sparse pattern region A is exposed through the opening 230 . In some embodiments, the portion of the second dielectric layer 225 in the pattern-dense region B is completely covered by the patterned mask 227 . Furthermore, the opening 230 has a width W4. Referring to Figures 6 and 16, the width W4 is larger than each of the widths W2 and W3.

Next, according to some embodiments, as shown in FIG. 17 , an etching process is performed on the second dielectric layer 225 using the patterned mask 227 as a mask, so that an opening 232 is formed in the second dielectric layer 225 . 225, polysilicon layer 221 and first dielectric layer 203. In some embodiments, the opening 232 passes through the second dielectric layer 225 , the polysilicon layer 221 and the first dielectric layer 203 to expose the semiconductor substrate 201 . The etching process may be a wet etching process, a dry etching process or a combination thereof. Since the fabrication technique of opening 232 involves transferring the pattern in patterned mask 227 , the width of opening 232 is approximately the same as the width W4 of opening 230 . After openings 232 are formed, patterned mask 227 can be removed.

Basically, according to some embodiments, as shown in FIG. 18 , a lining material 235 is formed on the second dielectric layer 225 and lines the opening 232 . In some embodiments, the sidewalls of the second dielectric layer 225 , the sidewalls of the polysilicon layer 221 , the sidewalls of the first dielectric layer 203 and the upper surface of the semiconductor substrate 201 exposed through the opening 232 are lined with material. 235 covered. Some of the materials and processes used to form the lining material 235 are similar or identical to those used to form the lining material 215 ( FIG. 8 ), and detailed descriptions thereof will not be repeated herein.

Then, according to some embodiments, as shown in FIG. 19 , a conductive material 237 is formed on the lining material 235 and fills the opening 232 . Some materials and processes used to form the conductive material 237 are similar or identical to those used to form the conductive material 217 ( FIG. 9 ), and their detailed description will not be repeated herein.

Referring back to FIG. 3 , according to some embodiments, after the conductive material 237 is formed, a planarization process is performed on the lining material 235 and the conductive material 237 until the second dielectric layer 225 is exposed. In some embodiments, after the planarization process is performed, a conductive material 239a (including a liner 235a and a conductive plug 237a) is formed in the sparse pattern area A. The planarization process may include a CMP process. The corresponding steps are shown in step S23 in the method 10 shown in FIG. 4 . After the planarization process is performed, the semiconductor device structure 200 is obtained.

20 is a partial structural schematic diagram illustrating an exemplary integrated circuit, such as a memory device 1000, having an array of memory cells 50 according to some embodiments of the present disclosure. In some embodiments, memory device 1000 has a dynamic random access memory (DRAM) device. In some embodiments, the memory device 1000 has a plurality of memory cells 50 arranged in a grid pattern and having a plurality of rows and columns. The plurality of memory cells 50 may vary according to system requirements and fabrication technology.

In some embodiments, each memory cell 50 has an access element and a storage element. The access element is configured to provide controlled access to the storage element. In some embodiments, the access element is a field effect transistor (FET) 51 and the storage element is a capacitor 53, according to some embodiments. In each memory cell 50 , the field effect transistor 51 has a drain 55 , a source 57 and a gate 59 . One terminal of the capacitor 53 is electrically connected to the source 57 of the field effect transistor 51 , and the other terminal of the capacitor 53 is electrically connected to ground. In addition, in each memory cell 50 , the gate 59 of the field effect transistor 51 is electrically connected to a word line WL, and the drain 55 of the field effect transistor 51 is electrically connected to a bit line BL.

The above description mentioned that the terminal of the field effect transistor 51 electrically connected to the capacitor 53 is the source 57 , and the terminal of the field effect transistor 51 electrically connected to the bit line BL is the drain 55 . However, during read and write operations, the terminal of the field effect transistor 51 electrically connected to the capacitor 53 may be the drain, and the field effect transistor 51 is electrically connected to the terminal of the bit line BL. Can be the source. That is, any terminal of the field effect transistor 51 can be a source or a drain, depending on the way the field effect transistor 51 is controlled by the voltages applied to the source, drain and gate.

By controlling the voltage at gate 59 through word line WL, a voltage potential can be generated across field effect transistor 51 so that electrical charge can flow from source 55 to capacitor 53 . Therefore, the charge stored in the capacitor 53 can be represented as a two-bit data in the memory cell 50 . For example, a positive charge stored in the capacitor 53 at a threshold voltage is represented by a two-bit "1". If the charge in capacitor 53 is below a critical value, one or two bits "0" may be said to be stored in memory cell 50.

The bit lines BL are configured to read or write data from and to the memory cells 50 . The word lines WL are configured to activate field effect transistors 51 to access a specific column of the memory cells 50 . Accordingly, the memory device 1000 also has a surrounding circuit area, which may include an address buffer, a row decoder, and a column decoder. Row decoders and column decoders selectively access the memory cells 50 in response to multiple address signals that are provided to address buffers during read, write, and refresh operations. device. The address signals are typically provided by an external controller, such as a microprocessor or other type of memory controller.

Referring back to FIG. 3 , the conductive structure 239a is formed in the sparse pattern area A, while the conductive plugs 223a and 223b, the silicide portions 221a and 221b and the conductive structures 219a and 219b are formed in the pattern dense area B. The pattern-sparse area A may be any one of a plurality of areas of the address buffer, column decoder, or row decoder in the memory device 1000 , and the pattern-dense area B may be any of the areas of the address buffer, column decoder, or row decoder in the memory device 1000 . Any one of multiple regions of the memory cell 50 .

Various embodiments of a semiconductor device structure 200 and methods of fabricating the same are provided in the present disclosure. In some embodiments, the semiconductor device structure 200 includes a first conductive plug (eg, conductive plug 217a) and a second conductive plug (eg, conductive plug 223a) directly above the first conductive plug, and is disposed on the first conductive plug. A silicone portion (eg, silicone portion 221a) between the conductive plug and the second conductive plug. The process used to form the two conductive plugs can help eliminate the overhang problem caused by the difficulty of filling a high aspect ratio opening structure, such as through the second dielectric layer. 225. The opening structure of the polycrystalline silicon layer 221 and the first dielectric layer 203.

Furthermore, the second conductive plug is formed on the silicone portion through a self-aligned process, and the second conductive plug is formed before the surrounding dielectric layer (eg, second dielectric layer 225) is formed. Forming. Therefore, there is no need to etch the dielectric layer surrounding the second conductive plug. Accordingly, the likelihood of gap formation between the conductive plugs and the surrounding dielectric layers may be reduced, and the risk of misalignment between the first conductive plugs and the second conductive plugs may be avoided. Therefore, the performance, reliability and yield of the semiconductor device structure can be improved.

An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first dielectric layer disposed on a semiconductor substrate; and a second dielectric layer disposed on the first dielectric layer. The semiconductor device also includes a first conductive plug disposed in the first dielectric layer; and a second conductive plug disposed in the second dielectric layer directly above the first conductive plug. The semiconductor element further includes a silicone portion disposed between the first conductive plug and the second conductive plug.

Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first dielectric layer disposed in a semiconductor substrate; and a polycrystalline silicon layer disposed on the first dielectric layer. The semiconductor device structure also includes a second dielectric layer disposed on the polysilicon layer; and a first conductive plug disposed in the first dielectric layer. The semiconductor device structure also includes a silicide portion disposed in the polycrystalline silicon layer and covering the first conductive plug; and a second conductive plug disposed in the second dielectric layer and covering the silicide portion.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device structure. The semiconductor device structure and preparation method include forming a first dielectric layer on a semiconductor substrate; and forming a first conductive plug in the first dielectric layer. The preparation method includes forming a polycrystalline silicon layer to cover the first dielectric layer and the first conductive plug; and converting a portion of the polycrystalline silicon layer into a silicon compound portion. The preparation method also includes forming a second conductive plug directly on the silicone portion; and forming a second dielectric layer to surround the second conductive plug.

Some embodiments of the present disclosure have several advantageous features. In some embodiments, the semiconductor device structure has a first conductive plug and a second conductive plug directly above the first conductive plug, and a conductive plug disposed between the first conductive plug and the second conductive plug. Silicones Division. The second conductive plug is formed on the silicone portion through a self-aligned process, and the second conductive plug is formed before the surrounding dielectric layer is formed. Therefore, there is no need to etch the dielectric layer surrounding the second conductive plug. Therefore, the possibility of gap formation may be reduced, and the risk of misalignment between the first conductive plug and the second conductive plug may be avoided. Therefore, the performance, reliability and yield of the semiconductor device structure can be improved.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

10:Preparation method 50: memory cell 51: Field effect transistor 53:Capacitor 55:Jiji 57:Source 59: Gate 100:Semiconductor component structure 101:Semiconductor substrate 103: First dielectric layer 105a: Conductive plug 105b: Conductive plug 107: Second dielectric layer 110a:Open your mouth 110b: Open your mouth 110c:Open your mouth 113a:Packing 113b:Packing 113c:Padding 115a: Conductive plug 115b: Conductive plug 115c: Conductive plug 200:Semiconductor component structure 201:Semiconductor substrate 203: First dielectric layer 205:Patterned Mask 210a: Open your mouth 210b: Open your mouth 212a: Open your mouth 212b:Open your mouth 215: Lining material 215a:Packing 215b:Packing 217: Conductive materials 217a: Conductive plug 217b: Conductive plug 219a: Conductive structures 219b:Conductive structure 220:Heat treatment process 221:Polycrystalline silicon layer 221a:Silicon Division 221b:Silicon Division 223a: Conductive plug 223b: Conductive plug 225: Second dielectric layer 227:Patterned mask 230:Open your mouth 232:Open your mouth 235: Lining material 235a:Packing 237: Conductive materials 237a: Conductive plug 239a: Conductive structure 1000:Memory component A: Pattern sparse area B: Pattern dense area BL: bit line BS1: Lower surface area BS2: Lower surface area G1: Gap G2: Gap G3: Gap S11: Steps S13: Steps S15: Steps S17: Steps S19: Steps S21: Steps S23: Steps TS1: Upper surface area TS2: Upper surface area W1: Width W2: Width W3: Width W4: Width WL: word line

By referring to the embodiments and the patent scope together with the drawings, the disclosure content of the present application can be more fully understood. The same element symbols in the drawings refer to the same elements. FIG. 1 is a schematic cross-sectional view illustrating an intermediate stage of a process of forming a semiconductor device structure according to a comparative example. FIG. 2 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a comparative example. FIG. 3 is a schematic cross-sectional view illustrating semiconductor device structures according to different embodiments of the present disclosure. FIG. 4 is a schematic flowchart illustrating methods of manufacturing semiconductor device structures according to different embodiments of the present disclosure. 5 is a schematic cross-sectional view illustrating an intermediate stage of forming a first dielectric layer on a semiconductor substrate during the formation of a semiconductor device structure according to various embodiments of the present disclosure. 6 is a schematic cross-sectional view illustrating an intermediate stage of forming a patterned mask on the first dielectric layer during formation of a semiconductor device structure according to different embodiments of the present disclosure. 7 is a schematic cross-sectional view illustrating an intermediate stage of etching the first dielectric layer to form a plurality of openings exposing the semiconductor substrate during the formation of the semiconductor device structure according to various embodiments of the present disclosure. 8 is a schematic cross-sectional view illustrating an intermediate stage of forming a lining material on a dielectric layer and lining the openings during formation of a semiconductor device structure according to various embodiments of the present disclosure. 9 is a schematic cross-sectional view illustrating an intermediate stage of forming a conductive material on the lining material and filling the openings during the formation of the semiconductor device structure according to various embodiments of the present disclosure. 10 is a schematic cross-sectional view illustrating an intermediate stage of planarizing a lining material and a conductive material to form a plurality of pads and a plurality of conductive plugs in the first dielectric layer during formation of a semiconductor device structure according to various embodiments of the present disclosure. 11 is a schematic cross-sectional view illustrating an intermediate stage of forming a polysilicon layer on the first dielectric layer and covering the pads and the conductive plugs during the formation of the semiconductor device structure according to different embodiments of the present disclosure. 12 is a schematic cross-sectional view illustrating various embodiments of the present disclosure at an intermediate stage of converting portions of a polycrystalline silicon layer into multiple silicide portions during formation of a semiconductor device structure. 13 is a schematic cross-sectional view illustrating an intermediate stage of forming a plurality of conductive plugs directly over the silicide portions during the formation of the semiconductor device structure according to different embodiments of the present disclosure. 14 is a schematic cross-sectional view illustrating an intermediate stage of forming a second dielectric layer to cover the polysilicon layer and a plurality of conductive plugs on the silicide portions during the formation of semiconductor device structures according to various embodiments of the present disclosure. 15 is a schematic cross-sectional view illustrating an intermediate stage of planarizing the second dielectric layer to expose the conductive plugs in the second dielectric layer during formation of the semiconductor device structure according to various embodiments of the present disclosure. 16 is a schematic cross-sectional view illustrating an intermediate stage of forming a patterned mask on the second dielectric layer during the formation of a semiconductor device structure according to various embodiments of the present disclosure. 17 is a schematic cross-sectional view illustrating an intermediate stage of etching the first dielectric layer, the polysilicon layer, and the second dielectric layer during the formation of the semiconductor device structure according to different embodiments of the present disclosure. 18 is a schematic cross-sectional view illustrating an intermediate stage of forming a lining material on the second dielectric layer and lining the opening during formation of a semiconductor device structure according to various embodiments of the present disclosure. 19 is a schematic cross-sectional view illustrating an intermediate stage of forming a conductive material on the lining material and filling the opening during the formation of the semiconductor device structure according to various embodiments of the present disclosure. 20 is a partial structural schematic diagram illustrating an exemplary integrated circuit having an array of multiple memory cells according to some embodiments of the present disclosure.

200:Semiconductor component structure

201:Semiconductor substrate

203: First dielectric layer

215a:Packing

215b:Packing

217a: Conductive plug

217b: Conductive plug

219a: Conductive structures

219b:Conductive structure

221:Polycrystalline silicon layer

221a:Silicon Division

221b:Silicon Division

223a: Conductive plug

223b: Conductive plug

225: Second dielectric layer

235a:Packing

237a: Conductive plug

239a: Conductive structure

A: Pattern sparse area

B: Pattern intensive area

W1: Width

W2: Width

W3: Width

Claims (30)

A semiconductor element structure includes: a first dielectric layer disposed on a semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; a first conductive plug disposed on the first dielectric layer. In the electrical layer; a second conductive plug is disposed in the second dielectric layer and directly above the first conductive plug; a polysilicon layer separates the first dielectric layer from the second dielectric layer; and a silicone portion disposed between the first conductive plug and the second conductive plug, wherein the silicone portion is laterally surrounded by the polycrystalline silicon layer. The semiconductor device structure of claim 1, wherein the silicone portion directly contacts the first conductive plug and the second conductive plug. The semiconductor device structure of claim 1, wherein a width of the silicide portion is substantially the same as a width of the second conductive plug. The semiconductor device structure according to claim 1, further comprising a liner to separate the first conductive plug from the first dielectric layer and the semiconductor substrate. The semiconductor device structure of claim 4, wherein the pad directly contacts the silicone part. The semiconductor device structure of claim 4, wherein the polysilicon layer is located above the pad. The semiconductor device structure of claim 4, wherein the silicone portion covers the pad. The semiconductor device structure of claim 1, wherein the silicide part directly contacts the polycrystalline silicon layer. The semiconductor device structure according to claim 1, further comprising a third conductive plug surrounded by the first dielectric layer, the polysilicon layer and the second dielectric layer, wherein the first conductive plug, the second The conductive plug and the silicide part are disposed in a dense pattern area, and the third conductive plug is disposed in a sparse pattern area. The semiconductor device structure of claim 9, wherein a width of the third conductive plug is greater than a width of the second conductive plug. A semiconductor element structure includes: a first dielectric layer provided in a semiconductor substrate; a polycrystalline silicon layer provided on the first dielectric layer; a second dielectric layer provided on the polycrystalline silicon layer; A first conductive plug is disposed in the first dielectric layer; a silicone portion is disposed in the polycrystalline silicon layer and covers the first conductive plug, wherein The silicide portion is laterally surrounded by the polycrystalline silicon layer; and a second conductive plug is disposed in the second dielectric layer and covers the silicide portion. The semiconductor device structure of claim 11, wherein the second conductive plug directly contacts the silicide part, and an upper surface area of the silicide part is substantially the same as a lower surface area of the second conductive plug. The semiconductor device structure of claim 11, wherein the silicide part is surrounded by the polycrystalline silicon layer and directly contacts the polycrystalline silicon layer. The semiconductor device structure of claim 11, wherein the polysilicon layer directly contacts the first dielectric layer and the second dielectric layer. The semiconductor device structure according to claim 11, further comprising a liner to separate the first conductive plug from the first dielectric layer. The semiconductor device structure of claim 15, wherein the liner and the first conductive plug together form a conductive structure, and a width of the conductive structure is substantially the same as a width of the silicide part. The semiconductor device structure of claim 15, wherein an upper surface of the liner directly contacts the lower surface of the silicide part. The semiconductor device structure of claim 11, further comprising a third conductive plug surrounded by the first dielectric layer, the polysilicon layer and the second dielectric layer, wherein a width of the third conductive plug is greater than A width of the second conductive plug. The semiconductor device structure of claim 18, wherein the first conductive plug, the second conductive plug and the silicone portion are disposed in an array area, and the third conductive plug is disposed in a surrounding circuit area. A method for preparing a semiconductor device structure, including: forming a first dielectric layer on a semiconductor substrate; forming a first conductive plug in the first dielectric layer; forming a polycrystalline silicon layer to cover the first dielectric layer with the first conductive plug; converting a portion of the polysilicon layer into a silicide portion; forming a second conductive plug directly on the silicide portion; and forming a second dielectric layer surrounding the second conductive plug , wherein the second conductive plug covers the silicide portion before the second dielectric layer is formed. The method of manufacturing a semiconductor device structure as claimed in claim 20, wherein the transformation includes performing a heat treatment process on the polycrystalline silicon layer. The method of manufacturing a semiconductor device structure as claimed in claim 20, wherein the portion of the polycrystalline silicon layer directly contacts the first conductive plug. The method of manufacturing a semiconductor device structure as claimed in claim 20, wherein the polycrystalline silicon layer separates the first dielectric layer and the second dielectric layer. The method for manufacturing a semiconductor device structure as claimed in claim 20, wherein after the second conductive plug is formed, the second dielectric layer is formed on a remaining portion of the polycrystalline silicon layer and contacts the remaining portion of the polycrystalline silicon layer. part. The method for manufacturing a semiconductor device structure as claimed in claim 20, further comprising: forming a first opening through the first dielectric layer to expose the semiconductor substrate; forming a lining material on the first dielectric layer and lining the first opening; forming a conductive material on the lining material and filling the first opening; and planarizing the lining material and the conductive material to form a liner to connect the first conductive material The plug is separated from the first dielectric layer and the semiconductor substrate. The method for preparing a semiconductor device structure as claimed in claim 25, wherein before the part of the polycrystalline silicon layer is transformed, the liner is covered by the polycrystalline silicon layer. The method of manufacturing a semiconductor device structure as claimed in claim 25, wherein after the portion of the polycrystalline silicon layer is transformed, the liner is covered by the silicide portion. The method of manufacturing a semiconductor device structure as claimed in claim 25, further comprising: forming a second opening through the first dielectric layer, the polycrystalline silicon layer and the second dielectric layer. layer to expose the semiconductor substrate; and forming a third conductive plug in the second opening. The method of manufacturing a semiconductor device structure as claimed in claim 28, wherein the first opening is disposed in a pattern dense area, and the second opening is disposed in a pattern sparse area. The method of manufacturing a semiconductor device structure as claimed in claim 28, wherein a width of the second opening is greater than a width of the first opening.