TWI680512B - Polishing method for silicon wafer, manufacturing method for silicon wafer, and silicon wafer - Google Patents

Abstract

Provided are a flat-side polishing method of a silicon wafer, a method of manufacturing a silicon wafer, and a silicon wafer, which can suppress slippage from a notch portion formed on an outer peripheral portion of a silicon wafer during a heat treatment of an element formation process.

In the method of flattening and polishing a silicon wafer having a notch, the notch is over-polished on the main surface side of at least one of the silicon wafers by mirror polishing.

Description

   Polishing method of silicon wafer, manufacturing method of silicon wafer, and silicon wafer   

The present invention relates to a method for polishing a silicon wafer, a method for manufacturing a silicon wafer, and a silicon wafer, and more particularly to a method capable of suppressing slippage from a notch portion formed on an outer peripheral portion of a silicon wafer during a heat treatment of an element formation process. Silicon wafer polishing method, silicon wafer manufacturing method and silicon wafer.

In the wafer manufacturing process, a silicon wafer used as a substrate for a semiconductor element is subjected to a grinding process on the outer periphery of a single-crystal silicon ingot that has been developed by using the CZochralski method or the CZ method. After the diameter of the ingot was adjusted to a predetermined value, it was sliced into a plurality of silicon wafers. Next, the obtained silicon wafer is subjected to flattening processing, flattening (rough grinding) processing, double-side polishing processing, final processing polishing processing, etc., and finally cleaned, and various quality inspections are performed. If no abnormality is confirmed, , Then complete the shipment as a product.

Various semiconductor elements are formed on the silicon wafers that have been shipped. In this device formation process, a plurality of heat treatments are applied to a silicon wafer, but in recent years, a rapid temperature rise and fall treatment has been used as the heat treatment. As a result, the stress on the wafer is increased due to the temperature difference between the front and back surfaces of the silicon wafer. Therefore, the situation described later has increased: the oxygen precipitates that have been precipitated in the silicon wafer or the transport injuries formed during the transport of the element formation process, and the contact with the wafer holder that supports the silicon wafer during heat treatment, When a differential row is formed by a contact flaw or the like formed on the back surface of the wafer outer peripheral portion, slippage of the formed differential row due to stress propagation becomes a problem.

When slippage occurs, it is a cause of local deformation. In the element formation process, an overlap (overlap) error is caused in a photo-etching process in which an element pattern is transcribed on a silicon wafer, and the yield of the element is reduced. Therefore, it is important that slipping does not occur even if a rapid temperature rise and heat treatment is performed.

Against this background, Patent Document 1 describes a method for controlling the density and size of precipitates inside a silicon wafer by a specific heat treatment in crystals having no Grown-in defects, thereby, in the element formation process, Even in the case of rapid temperature rising and lowering heat treatment, slip extension from oxygen precipitates, transport injuries, and contact injuries is prevented.

However, a notch indicating a specific crystal direction is often formed on the outer periphery of a silicon wafer. For example, a silicon wafer having a (100) plane crystal face is formed with a notch indicating the <110> direction and the like. This notch is formed by a method described later: after adjusting the diameter of the single crystal silicon ingot that has been bred in the wafer manufacturing process, for example, vermiculite is moved in the axial direction of the ingot (for example, refer to Patent Document 2) .

    Advance technical literature         Patent literature    

Patent Document 1: Japanese Patent Application Laid-Open No. 2010-228931

Patent Document 2: Japanese Patent Application Laid-Open No. 2005-219506

In the notch formed as described above and a region next to it (hereinafter referred to as a "notch part"), due to the special shape, thermal stress is easily concentrated during heat treatment. In addition, the damage formed on the end face of the notch during the notch processing is difficult to be removed by the subsequent smoothing treatment, and it is easy to remain. Therefore, during the heat treatment of the element formation process, slipping easily occurs from the notch portion.

In addition, in Patent Document 1, by controlling the density and size of the precipitates in the silicon wafer, it is possible to prevent the transport injury or contact injury from slipping from the outer peripheral portion of the wafer back surface, but the inventor of the present case learned that During the heat treatment of the element formation process, slipping occurs in the transport injury or contact injury from the notch portion.

As described above, in the heat treatment of the element formation process, even if the machining damage from the notch end surface or the notch portion is liable to slip, there is no method to suppress the occurrence of such slip.

Therefore, an object of the present invention is to provide a method for flat-side polishing of a silicon wafer, a method for manufacturing a silicon wafer, and a silicon wafer, which can suppress grooves formed on the outer periphery of the silicon wafer during the heat treatment of the element formation process. Mouth slipping.

The gist of the present invention that solves the above-mentioned problems is structured as follows.

(1) A method for flat-side polishing of a silicon wafer, characterized in that, in a method of flat-side polishing of a silicon wafer having a notch, at least one main surface side of the silicon wafer is subjected to The mirror surface is ground and polished, and the notch is over polished.

(2) The method of polishing a flat edge of a silicon wafer as described in (1), with the depth of the notch being D [mm], the over-polishing is performed from the outer peripheral end of the silicon wafer to the notch The distance between the inner ends of the wafer diameters in the polished area is 1.7 × D [mm] or more.

(3) The method of polishing a flat edge of a silicon wafer as described in (2), the over-polishing is performed so that the distance is 1.95 × D [mm] or more

(4) The method of polishing a flat edge of a silicon wafer according to any one of (1) to (3), wherein the over-polishing is performed so that the polishing process from the outer peripheral end of the silicon wafer to the polishing area of the notch is performed. The distance between the inner ends of the wafer diameters is 3.0 mm or less.

(5) The flat-side grinding method for polishing a silicon wafer according to any one of (1) to (3), wherein the oxygen concentration in the outer peripheral portion of the silicon wafer is 10.1 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) and above.

(6) The flat-side polishing method for silicon wafer grinding according to any one of (1) to (3), so that the processing damage on the end face of the notch is made apparent and all of it is removed.

(7) The method of polishing a flat edge of a silicon wafer as described in (6), and the manifestation of the processing damage is performed by a method described later: the silicon crystal is used at a first temperature of 900 ° C to 1150 ° C. The circle is subjected to a first heat treatment, followed by a second heat treatment at a second temperature of 1100 ° C. to 1200 ° C., followed by a selective etching treatment with an etching rate of 1.3 μm / min or less.

As described in (7), in the method of polishing a flat edge of a silicon wafer, the selective etching process is performed by a photo-etching method.

(9) A method for manufacturing a silicon wafer, characterized in that a silicon ingot is bred by a specific method, and the silicon ingot that has been sliced to obtain a silicon wafer, and the silicon crystal according to (1) to (8) The round grinding and flat-side grinding method applies a mirror-ground flat-side grinding process to the obtained silicon wafer.

(10) The method for manufacturing a silicon wafer according to (9), wherein the specific method is a Chuklaski method.

(11) A silicon wafer characterized in that, in a silicon wafer having a notch, a depth of the notch is D [mm] on at least one main surface side of the silicon wafer, and The distance from the outer peripheral end of the wafer to the inner end of the wafer diameter direction in the polishing region of the notch is 1.7 × D [mm] or more.

(12) The silicon wafer according to (11), wherein the distance is 1.95 × D [mm] or more.

(13) The silicon wafer according to (11) or (12), wherein the distance is 3.0 mm or less.

(14) The silicon wafer according to (11) or (12), wherein the oxygen concentration in the outer peripheral portion is 10.1 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more.

(15) The silicon wafer according to (11) or (12), wherein the processing damage in the notch is zero.

According to the present invention, it is possible to suppress slippage from the notch portion during the heat treatment of the element formation process.

[Fig. 1] Schematic diagram explaining the mirror-ground flat-side grinding process of the notch.

FIG. 2 is a schematic diagram illustrating a polishing region of a notch.

(Surface polishing method for silicon wafer)

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The method of flat-side polishing of a silicon wafer according to the present invention is a method of flat-side polishing of a silicon wafer having a notch. Here, it is characterized in that on at least one main surface side of the silicon wafer, The notch is over-polished by mirror-ground flat-side grinding.

As described above, due to the special shape of the notch portion, thermal stress is concentrated during the heat treatment of the element formation process and slippage easily occurs. In addition, among the causes of slippage, it is impossible to determine whether or not it has been removed. Therefore, it is difficult to completely remove the machining damage formed on the end face of the notch.

On the other hand, generally, in the element formation process, the outer peripheral portion of the back surface of the wafer is held for transportation or support. For this reason, it is difficult to prevent the formation of the transport damage or contact damage formed on the outer peripheral portion of the wafer back surface at all. However, the inventor of the present case learned that the transport or contact injury on the outer peripheral portion of the back surface of the wafer will become the starting point of slippage. Only the injury existing in the notch portion will prevent the slippage from existing in the groove. Transport or contact injuries occur in areas other than the mouth.

Therefore, the inventors of the present invention have examined a method of suppressing the occurrence of slippage that starts from such a transport injury or contact injury at the notch portion.

As described above, due to the special shape, thermal stress is easily concentrated in the notch portion during heat treatment. Therefore, the thermal stress generated by this heat treatment is a major cause of slippage. However, since the shape of the notch is determined by the specifications, it is difficult to solve this factor.

Therefore, the inventors of the present invention focused on the contact pressure generated at the outer peripheral portion of the back surface of the silicon wafer and the contact portion of the wafer holder. That is, during the heat treatment of the element formation process, the silicon wafer is supported by the wafer holder at its outer peripheral portion, and the contact portion between the outer peripheral portion of the silicon wafer backside and the wafer holder occurs due to the silicon wafer. Contact pressure of its own weight.

As far as the current situation is concerned, the area of the outer periphery of the wafer supported by the wafer holder is an area from the outer periphery of the wafer to the center of about 2 mm, but in the future, it can be imagined that the support area will be larger than it is now. narrow. In addition, with the increase in the diameter of silicon wafers, the weight of the wafer itself has also increased. As a result, it can be expected that the above-mentioned contact pressure will increase in the future, and slippage will also occur more easily.

Therefore, the inventor of the present invention believes that if the above-mentioned contact pressure is reduced in the notch portion, even if thermal stress is concentrated, it should be possible to suppress the occurrence of slipping from a transport injury or a contact injury as a starting point. Moreover, it was learned that, on at least one main surface side of the silicon wafer, that is, at least on the back surface side of the silicon wafer that is in contact with the wafer holder, the notch is over-polished by mirror-ground flat-side polishing. This method is very effective for reducing the above-mentioned contact pressure.

Generally speaking, the so-called "over-polishing" means that the wafer is ground to the inner side of the wafer surface more than usual in the processing of the flattened edges of the wafer outer periphery. In general, when performing a flat edge grinding process, in order to increase the effective area of the wafer, it is possible to manufacture more components, and reduce the flat edge width, that is, to suppress or prevent over-polishing. However, in the present invention, in order to prevent slipping of the transport injury or contact injury from the notch portion, the notch is deliberately over-polished by a mirror surface flat-side polishing process.

With the over-polishing of the notch, the flat surface of the area that is the main surface of at least one side is processed with a tapered surface. Therefore, the contact area between the outer peripheral portion of the back surface of the wafer and the wafer holder is reduced, and the notch is reduced. Contact pressure. Therefore, as shown in the examples described later, the stress of the transport injury or the contact injury applied to the notch portion is reduced. In addition, the transport injury or the contact injury itself is also reduced, so that occurrence of slippage can be suppressed.

FIG. 1 is a schematic diagram illustrating a mirror-ground flat-side polishing process of a notch. The mirror-ground flat-side polishing process for the notch N can be performed in the following manner. The silicon wafer W is placed on the table T, and the polishing pad P is abutted against the notch N at a specific inclination angle with respect to the vertical direction. The polishing pad P is rotated.

When the notch N is subjected to mirror-ground flat-side polishing, the polishing conditions such as the inclination angle of the polishing pad P from the vertical direction, the hardness of the polishing pad P, the polishing time, and the type of polishing slurry can be appropriately set to perform the notch N Over polished.

It is better to carry out the above polishing: the depth of the notch is D [mm], so that the distance from the outer peripheral end of the silicon wafer W to the inner end of the wafer diameter direction of the polishing area of the notch N is 1.7 × D [ mm] or more. Thereby, as shown in the embodiment described later, the contact pressure between the outer peripheral portion of the wafer back surface and the wafer holder is reduced, so that the stress applied to the notch portion during the transport injury or the contact injury is reduced, and the stress from The notch part slips during transport or contact injuries.

In particular, as shown in the examples described later, when the oxygen concentration in the peripheral portion of the silicon wafer is high (for example, 10.1 × 10 ¹⁷ atoms / cm ³ or more), it is possible to completely prevent the transport injury or contact injury from the notch portion. Slip occurred.

The depth D of the notch is defined by the SEMI specification. For example, for a wafer having a diameter of 300 mm, it is 1.00 mm + 0.25 mm-0.00 mm. That is, in the case of a wafer having a diameter of 300 mm, the depth D of the predetermined notch is 1.00 mm or more and 1.25 mm or less. Therefore, when the depth D of the notch is 1.00 mm, the above effect can be achieved by setting the distance from the outer peripheral end of the silicon wafer W to the inner end of the wafer diameter direction in the polishing region of the notch N to be 1.7 mm or more. Similarly, when the depth D of the notch is 1.25 mm, the above-mentioned effect can be achieved by setting the above-mentioned distance to 1.95 mm or more.

Furthermore, in the present invention, the "distance from the outer peripheral end of the silicon wafer to the inner end of the wafer diameter direction in the polishing region of the notch" is, as shown in Fig. 2 (a), the wafer diameter of the notch N In the direction inner end T, the distance L between the outer peripheral end E of the silicon wafer and the wafer diameter direction inner end I of the over-polished area of the notch N. Here, the "outer peripheral end E of the silicon wafer W" is a position where the outer peripheral end E 'of the area other than the slot N is extrapolated to the position of the slot N.

Moreover, the distance L described above is, as shown in FIG. 2 (b), the inside diameter I of the notch N in the wafer diameter direction, the depth D of the notch, and the inside end T of the wafer diameter direction in the notch N. The sum of the flattened edge M and the over-polished width W.

In addition, the above-mentioned over-polishing is performed so that the above-mentioned distance L is preferably 1.95 × D [mm] or more. As a result, as shown in the embodiment described later, the contact pressure between the outer peripheral portion of the wafer back surface and the wafer holder is further reduced, and the stress on the transport damage or contact damage of the notch portion is further reduced, and Since the transport injury or contact injury itself can be reduced, slipping of the transport injury or contact injury from the notch portion can be suppressed. In addition, even when the oxygen concentration in the outer peripheral portion of the silicon wafer is low (for example, less than 9.8 × 10 ¹⁷ atoms / cm ³ ), the contact formation from the outer peripheral portion of the back surface of the wafer can be completely prevented during the element formation process. Slip occurred.

On the other hand, the upper limit of the above-mentioned distance L is not particularly limited in terms of suppressing slippage, but is preferably 3.0 mm or less in terms of processing difficulty.

Furthermore, according to the investigation by the inventor of the present invention, slippage does not occur from a wound existing at a position away from the notch toward the inside of the wafer diameter direction. Specifically, the inventors of the present case confirmed that, among the injuries in the notch portion, slippage did not occur from the injury existing at a position 8 mm from the outer peripheral end.

The oxygen concentration in the outer peripheral portion of the silicon wafer is preferably 9.8 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more. The oxygen in the silicon wafer has the effect of pinning the differential row to suppress the occurrence of slip. In order to fully obtain such an oxygen pinning effect, it is preferable that the oxygen concentration in the outer peripheral portion of the silicon wafer is 9.8 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more. The oxygen concentration in the outer peripheral portion is particularly preferably 10.1 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more. In addition, in the present invention, the "outer peripheral portion of the silicon wafer" is an annular region 10 mm in the direction from the outer peripheral end of the wafer to the center of the wafer.

In addition, it is preferable that the machining damage formed on the end face of the notch is significantly increased and reduced. As described above, in the heat treatment of the element formation process, slipping may occur from the processing damage of the notch end surface formed when the notch is formed. Moreover, the machining damage of this notch end surface is different from the wound, and it cannot be observed without making it visible, so it is difficult to remove it. The inventor of the present case explored a method which can make it visible.

As a result, as described in Japanese Patent Application No. 2015-223807 previously applied by the inventor of the present case, the inventor of the present case found that, for the silicon wafer, the first temperature was performed at a relatively low temperature of 900 ° C. to 1150 ° C. After the heat treatment, a second heat treatment at a second temperature of 900 ° C. to 1150 ° C., which is higher than the first temperature, is applied, and then a selective etching treatment with an etching rate of 1.3 μm or less is applied to thereby make the end face of the slot The processing damage was manifested as Oxidation induced Stacking Fault (OSF). Hereinafter, a method for making processing damage visible to OSF will be described.

The first heat treatment described above can be performed using an appropriate heat treatment furnace, and the temperature when the silicon wafer described above is put into the heat treatment furnace is preferably 650 ° C to 800 ° C. The temperature increase rate before reaching the first temperature is preferably 3 ° C / second or more and 6 ° C / second or less.

The time for applying the first heat treatment is preferably 30 minutes or more and 300 minutes or less. Here, it is set to be 30 minutes or more, whereby the oxygen in the silicon wafer is aggregated near the processing damage to form an OSF core. On the other hand, if it exceeds 300 points, the OSF nucleation effect is saturated and does not change.

In addition, the environment in which the first heat treatment is performed is not particularly limited, but from the viewpoint of condensing oxygen in the silicon wafer near the processing damage, the first heat treatment is preferably performed in a dry oxygen gas environment.

Then, the silicon wafer to be evaluated subjected to the first heat treatment is subjected to a second heat treatment at a second temperature of 1100 ° C to 1200 ° C. This is because the formation of OSF may not be sufficient when the second temperature is less than 1100 ° C. On the other hand, if it exceeds 1200 ° C, the diffusion of silicon between the lattices becomes faster, and as a result, formation of OSF becomes difficult.

The time for applying the second heat treatment is preferably 30 minutes or more and 200 minutes or less. Here, by setting it to 30 minutes or more, the OSF can be formed from the OSF core formed by the first heat treatment as a starting point. On the other hand, even if it exceeds 200 points, the OSF formation effect is saturated and does not change.

The environment in which the second heat treatment is performed is not particularly limited, but from the viewpoint of efficiently forming the OSF, it is preferably performed in a humid oxygen gas environment containing water vapor.

Next, the silicon wafer to be evaluated subjected to the second heat treatment described above is subjected to a selective etching treatment having an etching rate of 1.3 μm / min or less. Thereby, it is possible to make the machining damage on the end face of the notch significantly become OSF. In addition, if the etching rate is too low, it will take too much time to make the OSF significantly visible. Therefore, the etching rate is preferably 0.05 μm / min or more.

The above-mentioned etching rate of 1.3 μm / min or less can be performed by, for example, preparing an etching solution. Specifically, the selective etching of Si is performed by oxidation of Si and removal of Si oxide. Since the above-mentioned etching by Si oxide removal continues, by adjusting the ratio of the drug used for oxidation and the drug used for oxide film removal, and the amount of buffer added to suppress both oxidation and oxide removal , The etching rate can be made 1.3 μm / min or less. The medicine used for oxidation is, for example, nitric acid or chromic acid, the medicine used for removing the oxide film is, for example, hydrofluoric acid, and the buffering agent is, for example, water or acetic acid.

Existing methods for performing selective etching treatment with the above-mentioned etching rate of 1.3 μm / min or less include a photo-etching method, a dash etching method using a mixed solution of hydrofluoric acid and nitric acid, and the like. Observation of OSF such as rough surface From the viewpoint of easiness, it is preferable to use a photoetching method. The etching rate of the photoetching method was 1.0 μm / min.

The time for which the etching process is performed is preferably 1 second to 180 seconds. Here, by setting it to 1 second or longer, the OSF can be formed using the OSF core formed by the first heat treatment as a starting point. On the other hand, if the time exceeds 180 seconds, surface roughness occurs, and the observation of OSF becomes difficult due to the influence of the surface roughness. It is more preferably 5 seconds to 30 seconds.

With the above processing, the processing damage existing on the notch end surface of the silicon wafer can be significantly changed to OSF. Therefore, by observing the notch end surface by an optical microscope, for example, the processing damage can be detected by the OSF.

As shown in the examples described below, it can be known that if the processing damage of the notch end surface can be significantly increased by the above method, it is possible to reduce the polishing pad or slurry when the mirror surface flat edge polishing treatment is appropriately selected. The above process damage. In addition, it was also found that by using a combination of a polishing pad and a polishing slurry, processing damage can be completely removed.

In this way, the machining damage at the end face of the notch is significantly increased and reduced, and slippage from the machining damage as a starting point can be suppressed. Furthermore, by completely eliminating the processing damage, it is possible to prevent the processing damage from slipping from the notch end surface.

The reduction of the machining damage on the notch end surface can be performed in the same procedure of mirror-polishing and flat-side grinding of the notch over-polishing, or in another procedure different from over-polishing.

In addition, the effect of over-polishing is related to the contact pressure between the outer periphery of the wafer backside and the wafer holder, and the transport or contact damage generated on the back side of the wafer. Therefore, the above-mentioned over-polishing can only be applied to the wafer. Executed on the back side.

As described above, by the method of flat-side polishing of a silicon wafer according to the present invention, it is possible to suppress slippage from a notch portion during a heat treatment of an element formation process.

(Silicon wafer manufacturing method)

Next, a method for manufacturing a silicon wafer according to the present invention will be described. The method for manufacturing a silicon wafer of the present invention is characterized in that a silicon ingot is bred by a specific method, and the silicon ingot that has been sliced is sliced to obtain a silicon wafer. The method of flat-side polishing of silicon wafers is performed by mirror-ground flat-side polishing of the notches. Therefore, there are no restrictions on the procedures other than the mirror-ground flat-side polishing process of the above-mentioned notch portion. An example of a method for manufacturing a silicon wafer of the present invention is shown below.

First, according to the CZ method, polycrystalline silicon that has been put into a quartz crucible is melted to about 1400 ° C, and then the seed crystal is dipped into the liquid surface and pulled while being rotated, thereby producing a single crystal having a (100) plane crystal surface, for example. Silicon ingot. Here, in order to obtain a desired resistivity, for example, boron or phosphorus is doped. In addition, a magnetic field application magnetic field CZochralski (MCZ) method using a magnetic field during ingot manufacturing can control the oxygen concentration in the silicon ingot.

Next, after grinding the outer periphery of the obtained single crystal silicon ingot to make the diameter uniform, a vermiculite having an appropriate shape is pressed against the outer peripheral surface of the ingot, and the movement of the ingot in the axial direction is repeated. This formation, for example, indicates a notch in the <110> direction.

Next, using a wire saw or an inner peripheral cutter, the single crystal silicon block having the notch formed is sliced into a thickness of, for example, about 1 mm to obtain a silicon wafer.

After that, the outer peripheral portion of the obtained silicon wafer was subjected to a smoothing process once. This primary edging process can be performed in the following manner, using a grinding process, in advance, forming a vermiculite vermiculite having a groove having a shape corresponding to the shape of the edged side, or contour processing. Specifically, first, for example, a metal bonded cylindrical vermiculite having a degree of # 600 is pressed against the outer peripheral portion of the silicon wafer, and the roughened edge is subjected to a single smoothed edge treatment with a specific shape. Thereby, the outer peripheral portion of the silicon wafer is processed into a specific round shape.

In the same manner, the notch is subjected to a flat-edging treatment once. At this time, a metal bonding material, such as # 600, which has a smaller diameter than the vermiculite used on the entire periphery of the silicon wafer (for example, the diameter at which the wafer is in contact with the wafer is 1 mm), makes the vermiculite against the notch while rotating. , So that the vermiculite moves along the contour of the slot, thereby performing a smooth edge processing.

After that, the primary surface of the silicon wafer is subjected to a planarization process (rough grinding process) once. In this one-time planarization process, the silicon wafer is arranged between a pair of coarse grinding platens which are parallel to each other, and a coarse grinding liquid formed of a mixture of alumina abrasive particles and a dispersant and water is supplied to the coarse grinding platens. It is rotated and slid under a specific pressure to mechanically roughen the front and back surfaces of the silicon wafer, thereby improving the flatness of the wafer. At this time, the total rough grinding amount of the silicon wafer on both sides of the wafer surface is about 40 to 100 μm.

Next, the outer peripheral portion of the silicon wafer that has been subjected to the first flattening treatment is subjected to two flattening edges by grinding, contouring, etc., of a disc-shaped vermiculite with a fine grinding vermiculite. These two smoothing edges are finer than the first smoothing edges. For example, a metal bonded material of # 2000 is used to smooth the edges with vermiculite.

Similarly, the notch was also subjected to two rounded edges. At this time, a metal bonding material, such as # 2000, which has a smaller diameter than the vermiculite used for the entire periphery of the silicon wafer (for example, the diameter at which the wafer is in contact with the wafer is 1 mm) can be used. The notch is performed by moving vermiculite along the outline of the notch.

After that, the silicon wafer that has been subjected to the flattening process twice is etched. Specifically, acid etching using an aqueous solution formed of at least one of hydrofluoric acid, nitric acid, acetic acid, and phosphoric acid, or alkali etching using an aqueous potassium hydroxide solution or an aqueous sodium hydroxide solution, or the acid etching and alkali etching described above, This removes the distortion of the wafer caused by the processing before the previous procedure.

Next, the silicon wafer that has been etched is subjected to a planar grinding process to improve the flatness of the wafer. This plane grinding process can be performed by a plane grinding device. For example, # 8000 vitrified grinding vermiculite having a distribution center diameter of diamond abrasive grains of 0.7 μm can be used as the vermiculite for this plane grinding treatment.

Thereafter, a double-side polishing process is performed on the silicon wafer that has been subjected to the surface grinding process using a double-side polishing processing apparatus. This double-side polishing process is performed. After the silicon wafer is embedded in the hole portion of the carrier board, the carrier board The upper plate and the lower plate of the abrasive cloth are clamped, so that abrasive slurry such as colloidal silicon dioxide flows between the upper plate and the lower plate, and the wafer, so that the upper plate and the carrier rotate in opposite directions. Thereby, the unevenness on the wafer surface can be reduced to obtain a wafer having a high flatness.

Next, the outer peripheral portion of the silicon wafer is subjected to mirror-ground flat-side polishing. This mirror-surface flat-side polishing process is performed using a mirror-surface flat-side polishing device that rotates, for example, a cylindrical polyurethane wheel with a motor. Mirror surface grinding and flat-side polishing processing, the polyurethane grinding wheel is rotated by the motor, and the outer peripheral portion of the silicon wafer is brought into contact with the outer peripheral surface of the rotating grinding wheel. Thereby, the wafer peripheral surface is mirror-finished.

Similarly, the notch is also subjected to mirror-ground flat-side polishing. This mirror surface grinding and flat-side grinding process is performed, so that the disc-shaped polyurethane grinding wheel is rotated against the notch while rotating. In the present invention, the notch is over-polished by the mirror-side flat-side polishing process according to the method for processing a silicon wafer of the present invention. Thereby, even if a transfer injury or a contact injury is formed on the outer peripheral portion of the back surface of the wafer during the element formation process, the contact pressure on the back surface of the notch portion can be reduced, and slippage from the notch portion can be suppressed.

Thereafter, a single-side polishing device is used to apply a single-side polishing process to the silicon wafer that has undergone the mirror-ground flat-side polishing process. This one-side polishing process can be performed by using a polishing cloth made of flannel, and using, for example, an alkaline polishing liquid containing colloidal silica as the polishing liquid.

Next, the silicon wafers that have undergone the final processing and polishing process are transferred to a cleaning program, using, for example, SC-1 cleaning solution as a mixture of ammonia, hydrogen peroxide, and water, or hydrochloric acid, hydrogen peroxide, and water. SC-2 cleaning solution of the mixture to remove particles, organics, metals, etc. on the wafer surface.

Finally, the cleaned silicon wafer is transferred to an inspection program to check the flatness of the wafer, the number of LPD on the wafer surface, damage, and contamination on the wafer surface. Only wafers that pass these inspections and meet specific product quality are shipped as products.

Furthermore, the wafer obtained in the above steps may be subjected to an annealing process or an epitaxial film growth process as needed, thereby obtaining an annealed wafer or an epitaxial wafer, a SOI (Silicon On Insulator) wafer, or the like.

In this way, a silicon wafer capable of suppressing slippage from the notch portion during the element formation process can be manufactured.

(Silicon wafer)

Next, the silicon wafer of the present invention will be described. The silicon wafer of the present invention is a silicon wafer having a notch, characterized in that the depth of the notch is D [mm], and at least one of the main surface sides of the silicon wafer is from the outer peripheral end of the silicon wafer The distance from the wafer radial direction inner end to the polishing area of the notch is 1.7 × D [mm] or more.

According to the silicon wafer of the present invention described above, it is possible to prevent slippage from occurring during the heat treatment of the element formation process from a transport flaw or a contact flaw formed on the back surface of the wafer. When the wafer has a high oxygen concentration (for example, 10.1 × 10 ¹⁷ atoms / cm ³ or more), it is possible to completely prevent the occurrence of slippage.

In addition, it is particularly preferable that the distance from the outer peripheral end of the silicon wafer to the inner end of the wafer radial direction in the polishing region of the notch is 1.95 × D [mm] or more. With this, even when the silicon wafer has a low oxygen concentration (for example, less than 10.1 × 10 ¹⁷ atoms / cm ³ ), it is possible to completely prevent the transport or contact damage caused by the notch portion formed on the back of the wafer from The starting point slipped.

The distance from the outer peripheral end of the silicon wafer to the inner end of the wafer diameter direction in the polishing area of the notch is not particularly limited in terms of preventing slippage from the rear surface of the transport injury or contact injury as a starting point, but From the viewpoint of processing difficulty, it is preferably 3.0 mm or less.

The oxygen concentration in the outer peripheral portion of the silicon wafer is preferably 9.8 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more. Oxygen is known to have the effect of pinning differential rows. Therefore, by setting the oxygen concentration in the outer peripheral portion to 9.8 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979), it is possible to suppress the occurrence of slippage by pinning the differential displacement generated at the notch portion. The oxygen concentration in the outer peripheral portion is particularly preferably 10.1 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more.

Moreover, it is preferable that there is no machining damage in the notch (that is, the machining damage in the notch end surface is zero). As described above, the machining damage of the notch end surface is likely to be the starting point of slippage. Therefore, machining damage on the end surface of the notch can be eliminated, and slippage can be prevented starting from the machining damage on the notch.

[Example 1]

Hereinafter, examples of the present invention will be described, but the present invention is not limited by the following examples.

<Reviewing the processing conditions for mirror-ground and flat-side grinding of the notch end surface by making processing damage apparent>

In the mirror-ground flat-side polishing process of flattening the end surface of the edge portion, it is necessary to review the combination of a polishing pad and a polishing pad having the ability to remove the processing damage formed on the notch end surface of the silicon wafer. First, four silicon wafers were prepared, and the notches were formed under the same conditions, and they had been subjected to the first edge polishing process and the second edge polishing process. In addition, a hard and soft polishing pad is prepared, and a polishing slurry having a low specific gravity and a high specific gravity is prepared. Using the four combinations of these polishing pads and polishing slurry, the notch of the silicon wafer is subjected to mirror-ground flat-side polishing.

When evaluating the machining damage of the notch end surface, the method described in Japanese Patent Application No. 2015-223807, which has been previously applied by the inventor of the present application, is used to make the above-mentioned machining damage into OSF.

Specifically, first, dry oxygen gas was introduced into the vertical heat treatment furnace, and the inside of the furnace was made into a dry oxygen gas environment, and then the temperature in the furnace was raised to 700 ° C. Next, the silicon wafer which has been subjected to mirror polishing and flat-side polishing to the notch is put into a heat treatment furnace, and the temperature is raised to 1000 ° C., which is the first heat treatment temperature, at a temperature increase rate of 6 ° C./second, and then maintained for 180 minutes. The circle is subjected to a first heat treatment.

Next, the environment in the furnace was switched to a humid oxygen gas environment, and the temperature was raised to 650 ° C./sec to 1150 ° C., which was the second heat treatment temperature, and then the temperature was maintained for 110 minutes, and the silicon wafer was subjected to the second heat treatment. Finally, after the temperature was lowered to 700 ° C at a rate of 2 ° C / sec, the sample was taken out of the heat treatment furnace and cooled at room temperature.

Then, the silicon wafer subjected to the heat treatment as described above is subjected to a photo-etching process. Specific, using HF to 30cm _^3, CH ³ COOH to _{^{30cm 3, Cu (NO 3)}} 2 to 1g, CrO ₃ (5M) to 15cm _^3, HNO ³ to 15cm ^3, 30cm ³ of water are mixed ratio The solution was used as an etching solution, and an etching process was applied to the silicon wafer for 10 seconds.

The number of OSFs generated by the heat treatment and the etching process was observed with an optical microscope. The quantity of the obtained OSF is shown in Table 1.

【Table 1】     

By making the processing damage obvious, it is known that the combination of a hard polishing pad A and a polishing slurry A with a low specific gravity has the lowest removal ability of processing damage, and a combination of a soft polishing pad B and a polishing slurry B with a high specific gravity. Its processing damage removal ability is the highest. In addition, it was also found that, from the viewpoint of improving the ability to remove processing damage, it is more effective to appropriately select a polishing pad than a polishing slurry. This is because the degree of adhesion to the end face of the notch can be improved by a soft polishing pad.

[Example 2]

<Review of Slip Occurrence Suppression Effect>

First, prepare 8 silicon wafers (diameter: 300mm, notch depth: 0.1mm, oxygen concentration: 9.8 × 10 ¹⁷ atoms / cm ³ ). The notches are formed under the same conditions, and have been polished once. , And 2 times flattened edges. Next, for these silicon wafers, the inclination angle and polishing time of the pad against the vertical direction of the notch under the combined conditions of polishing pad B and polishing slurry B without processing damage are changed as shown in Table 2. Thus, a mirror-ground flat-side grinding process is applied to thereby produce over-polishing, that is, samples with different wafer-diameter inner ends from the outer peripheral end to the polishing area of the notch.

【Table 2】     

Next, each silicon wafer is subjected to a simulated heat treatment that simulates a heat treatment history of a standard element formation process.

Next, the number of transport and contact injuries in the notch portion of the back surface of the wafer introduced during the simulated heat treatment described above was calculated. In addition, using an optical microscope, the occurrence of slippage from the notch portion was checked. Then, the distance from the outer peripheral end of the wafer to the inner end in the wafer radial direction of the polishing area of the notch was measured. The results obtained are shown in Table 2.

Table 2 also shows the results obtained by performing the above-mentioned processing and evaluation on 8 silicon wafers having an oxygen concentration of 10.1 × 10 ¹⁷ atoms / cm ³ .

As shown in Table 2, it can be seen that if the distance between the outer peripheral end of the wafer and the inner end in the wafer radial direction of the polishing region is 1.7 mm or more, no slippage occurs from the notch portion. In addition, it was also found that when the distance between the outer peripheral end of the wafer and the inner end in the wafer radial direction of the polishing region is greater than 1.7 mm, the transport damage and contact damage on the back surface of the notch portion are reduced.

In addition, it is known from Table 2 that when the oxygen concentration in the outer peripheral portion of the silicon wafer is as high as 10.1 × 10 ¹⁷ atoms / cm ³ , if the distance between the outer peripheral end of the wafer and the inner end in the wafer radial direction of the polishing region is 1.7 mm or more, it can completely prevent slipping. When the distance between the wafer outer peripheral end and the wafer radial direction inner end of the polishing region is 1.95 mm or more, even when the oxygen concentration in the outer peripheral portion of the silicon wafer is as low as 9.8 × 10 ¹⁷ atoms / cm ³ , Can also completely prevent the occurrence of slippage.

In addition, by over-polishing, even if a transport injury or a contact injury is introduced on the back surface of the notch portion, it is possible to suppress slippage from the formed injury. This is because the contact pressure between the outer periphery of the silicon wafer and the wafer holder is reduced, and the stress of the transport injury or contact injury applied to the notch portion is reduced.

[Industrial possibilities]

According to the present invention, it is possible to suppress slippage from the notch portion during the heat treatment of the element formation process, and thus it is useful in the semiconductor industry.

Claims (9)

A method for flat-side grinding of silicon wafers, characterized in that, in a method of flat-side grinding of a silicon wafer having a notch, a mirror-side flat-side grinding process is performed on the back side of the silicon wafer. , Over-polishing the notch, wherein the depth of the notch is D [mm], and the over-polishing is performed so that the diameter from the outer peripheral end of the silicon wafer to the inner end of the wafer diameter direction of the polishing region of the notch The distance is 1.7 × D [mm] or more. As in the method for flattening and polishing the silicon wafer described in item 1 of the scope of patent application, the over-polishing is performed so that the distance is 1.95 × D [mm] or more. As in the method for flattening and polishing a silicon wafer as described in item 1 or 2 of the patent application scope, the over-polishing is performed so that the wafer diameter direction from the outer peripheral end of the silicon wafer to the wafer radial direction inner side of the notch The distance between the ends is 3.0 mm or less. The scope of the patent side polishing method polished silicon wafer described in the item 1 or 2, the oxygen concentration in the outer peripheral portion of the silicon wafer was ^{10.1 × 10 17 atoms / cm 3} (ASTM F121-1979) above. The method for flattening and polishing the silicon wafer as described in item 1 or 2 of the scope of the patent application makes the processing damage on the end face of the notch obvious and removes it completely. As in the method for flat-side polishing of a silicon wafer described in item 5 of the scope of the patent application, the manifestation of the processing damage is performed by a method described below: the silicon crystal is used at a first temperature of 900 ° C. to 1150 ° C. The circle is subjected to a first heat treatment, followed by a second heat treatment at a second temperature of 1100 ° C. to 1200 ° C., followed by a selective etching treatment with an etching rate of 1.3 μm / min or less. The selective etching process is performed by a photo-etching method, as in the flat-side polishing method of silicon wafers described in item 6 of the scope of patent application. A method for manufacturing a silicon wafer, comprising: cultivating a silicon ingot by a specific method, slicing the silicon ingot that has been sliced to obtain a silicon wafer, and grinding the silicon wafer in accordance with claims 1 to 7 according to the polishing method. In the polishing method, a mirror-ground flat-side polishing process is performed on the obtained silicon wafer. As the method for manufacturing a silicon wafer as described in the patent application No. 8, the specific method is the Chuklaski method.