TWI673700B - Pixel circuit and transparent display - Google Patents

Abstract

A pixel circuit includes a first transistor, a second transistor, and a third transistor. A first terminal of the first transistor receives a first power voltage. The control terminal of the first transistor receives a first gate signal. A first terminal of the second transistor and a second terminal of the first transistor are coupled to the first node. A second terminal of the second transistor receives a second power supply voltage. The control terminal of the third transistor is used to receive the second gate signal. The first terminal of the third transistor receives a data signal. The second terminal of the third transistor and the control terminal of the second transistor are coupled to the second node.

Description

Pixel circuit and transparent display

This case relates to a pixel circuit and a transparent display, and more particularly to a pixel circuit and a transparent display of a cholesteric liquid crystal.

Transparent displays can be used in a variety of usage scenarios, and in response to the needs of transparent displays, a variety of display technologies have been derived, such as liquid crystal displays (LCD) and organic light emitting diode (OLED) transparent displays; The transparent place shows the problem of transparency; while the organic light emitting diode transparent display has a much higher transmittance than the liquid crystal display because there is no polarizer, but the organic light emitting diode transparent display will The problem of light leakage caused by black display pixels makes the organic light-emitting diode transparent display have a low contrast under a high-brightness environment background, resulting in poor display effects.

One aspect of this case is to provide a pixel circuit for driving a display unit. The pixel circuit includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first terminal, a control terminal, and a second terminal. The first terminal is used to receive a first power voltage. The control end is used for receiving the first gate signal. The second transistor includes a first terminal, a control terminal, and a second terminal. The first terminal and the second terminal of the first transistor are coupled to the first node. The second terminal is used to receive a second power voltage. The third transistor includes a control terminal, a first terminal, and a second terminal. The control end is used for receiving the second gate signal. The first end is used to receive data signals. The second terminal and the control terminal of the second transistor are coupled to the second node, so as to control the conduction state of the second transistor.

Another aspect of the present case is to provide a transparent display including a transparent display panel and a switch module. The switch module is disposed on one side of the light-emitting surface of the disparate and transparent display panel. The switch module includes a plurality of pixel circuits. When the voltage level of the first node is the third voltage level, the corresponding switch module is displayed as a transparent screen, and when the voltage level of the first node is the second voltage level, the corresponding switch module is displayed as a black screen , Where the second voltage level is lower than the third voltage level.

Therefore, according to the technical aspect of the present case, the embodiments of the present case provide an organic light emitting diode transparent display and cholesterol by providing a pixel circuit and a transparent display, and in particular, a pixel circuit and a transparent display related to a cholesterol-type liquid crystal. In combination with the liquid crystal display of the liquid crystal type, the problem of light leakage of the black display pixels of the organic light emitting diode transparent display is solved by the light shielding of the cholesteric liquid crystal added with a dichroic dye, thereby increasing the contrast of the display. In addition, the size of the driving voltage provided to the cholesteric liquid crystal display is controlled by the pixel circuit so that the pixel electrode reaches an ideal potential. In this way, the pixel circuit in the transparent display can display transparent or black.

100‧‧‧ transparent display

110‧‧‧ transparent display panel

130‧‧‧Switch Module

115‧‧‧ transparent display unit

135‧‧‧Switch Module Unit

200, 200A, 300A‧‧‧ pixel circuit

200B, 300B‧‧‧Control waveform

210‧‧‧display unit

G1 to G3‧‧‧Gate signals

T1 to T4‧‧‧Transistors

C1, C2‧‧‧capacitor

Vdd, Vss‧‧‧ Power supply voltage

Data‧‧‧ Data Signal

Vq, Vp‧‧‧node

Vreset‧‧‧ reset voltage

CF_com‧‧‧Power supply voltage

P1 to P14 ‧‧‧ time interval

V1, V2, V3‧‧‧Voltage levels

In order to make the above and other objects, features, advantages, and embodiments of the present invention more comprehensible, the description of the drawings is as follows: FIG. 1A is a schematic diagram of a transparent display according to some embodiments of the present invention; FIG. 1B is a top view of a transparent display according to some embodiments of the present case; FIG. 2A is a schematic diagram of a pixel circuit according to some embodiments of the present case; FIG. 2B is a view of some pixel circuits according to the present case; A control waveform diagram according to the embodiment; FIG. 3A is a schematic diagram of a pixel circuit according to some embodiments of the present invention; FIG. 3B is a control waveform diagram according to some embodiments of the present invention Figure 4A is a schematic diagram of a conventional transparent display; Figure 4B is a schematic diagram of a transparent display according to some embodiments of the present case; and Figure 4C is a schematic diagram of a transparent display according to some embodiments of the present case A detailed schematic diagram of the transparent display shown in FIG. 4B.

The following disclosure provides many different embodiments or illustrations to implement different features of the invention. The components and configurations in the particular example are discussed below Was used to simplify this disclosure. Any illustrations discussed are for illustrative purposes only and do not in any way limit the scope and meaning of the invention or its illustrations. In addition, the present disclosure may repeatedly refer to numerical symbols and / or letters in different examples, and these repetitions are for simplification and explanation, and do not themselves specify the relationship between different embodiments and / or configurations in the following discussion.

The terms used throughout the specification and the scope of patent applications, unless otherwise specified, usually have the ordinary meaning of each term used in this field, in the content disclosed here, and in special content. Certain terms used to describe this disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art on the description of this disclosure.

As used herein, "coupled" or "connected" can mean that two or more components make direct physical or electrical contact with each other, or indirectly make physical or electrical contact with each other, and "coupled" or " "Connected" may also mean that two or more elements operate or act on each other.

In this article, the terms first, second, third, etc. are used to describe various elements, components, regions, layers, and / or blocks that are understandable. However, these elements, components, regions, layers and / or blocks should not be limited by these terms. These terms are limited to identifying single elements, components, regions, layers, and / or blocks. Therefore, a first element, component, region, layer, and / or block in the following may also be referred to as a second element, component, region, layer, and / or block without departing from the intention of the present invention. As used herein, the term "and / or" includes any combination of one or more of the associated listed items. The "and / or" mentioned in this document refers to any, all or any combination of at least one of the listed elements.

See Figure 1A. FIG. 1A is a schematic diagram of a transparent display 100 according to some embodiments of the present invention. As shown in FIG. 1A, the transparent display 100 includes a transparent display panel 110 and a switch module 130. One side of the transparent display panel 110 is a light emitting surface. The switch module 130 is disposed on one side of the light-emitting surface of the disparate transparent display panel 110. The transparent display panel 110 of the transparent display 100 includes a plurality of transparent display units 115, and the switch module 130 of the transparent display 100 includes a plurality of switch module units 135. Each switch module unit 135 includes a plurality of pixel circuits 200 and a plurality of display units 210.

See Figure 1B. FIG. 1B is a top view of a transparent display 100 according to some embodiments of the present invention. It can be seen from FIG. 1B that the plurality of transparent display units 115 are arranged in an array, and the plurality of switch module units 135 are also arranged in an array. It should be noted that the number and arrangement of the transparent display unit 115 and the switch module unit 135 as shown in FIG. 1A or FIG. 1B are only for illustrative purposes, and the implementation in this case is not limited to the above.

The pixel circuit 200 may be the pixel circuit 200A as shown in FIG. 2A or the pixel circuit 300A as shown in FIG. 3A. For detailed structures and driving methods of the pixel circuits 200A and 300A, reference will be made later. 2A to 3B are described together.

See Figure 2A. FIG. 2A is a schematic diagram of a pixel circuit 200A according to some embodiments of the present invention. As shown in FIG. 2A, the pixel circuit 200A includes transistors T1, T2, T3, and T4.

The first terminal of the transistor T1 is used to receive the power supply voltage Vdd, and the control terminal of the transistor T1 is used to receive the gate signal G1. Transistor T1 second The terminal and the first terminal of the transistor T2, the first terminal of the capacitor C1, and the first terminal of the capacitor C2 are coupled to the node Vp. The second terminal of the transistor T2 is used to receive the power supply voltage Vss. The control terminal of the transistor T2 is coupled to the second terminal of the transistor T3 and the first terminal of the transistor T4 to the node Vq. The voltage of the node Vq is used to control the conducting state of the transistor T2. The control terminal of transistor T3 is used to receive the gate signal G2, and the first terminal of transistor T3 is used to receive the data signal Data. The second terminal of the transistor T4 is used to receive the reset voltage Vreset, and the control terminal of the transistor T4 is used to receive the gate signal G3. The second terminal of the capacitor C1 is used to receive the power supply voltage CF_com, and the second terminal of the capacitor C2 is used to receive the power supply voltage Vss.

The pixel circuit 200A determines the voltage level of the node Vp according to the conducting state of the transistor T1 and the transistor T2, so as to drive the display unit 210 of the switching module 130. In some embodiments, the pixel circuit 200A determines the voltage level of the node Vp according to the resistance value of the transistor T1 and the resistance value of the transistor T2, and drives the display unit 210 at the voltage level output by the node Vp.

Please also refer to Figure 2B. FIG. 2B is a control waveform diagram 200B for driving the pixel circuit 200A in FIG. 2A according to some embodiments of the present invention. As shown in FIG. 2B, the control waveform diagram 200B includes the gate signals G1, G2, G3, the data signal Data, and the voltage level of the node Vp.

Assume that the voltage of the power supply voltage Vdd is 40V (volt), the power supply voltage Vss is -2V, and the reset voltage Vreset is -2V, and the data signal Data is 15V in the time interval P1 to P5. In the time interval P1, the gate signal G1 is at a high voltage level, and the gate signal G2 is at a low voltage level. At this time, the transistor T1 is turned on, and the transistors T2 and T3 are not turned on. Power supply voltage Vdd via transistor T1 is transmitted to node Vp. The voltage level of the node Vp is gradually pulled up to a voltage level V1 close to the power supply voltage Vdd, that is, the voltage level of the node Vp is gradually pulled up to close to 40V.

During the time interval P2, the gate signals G1 and G2 are both at high voltage levels. At this time, the transistors T1 and T3 are turned on. The data signal Data is transmitted to the node Vq through the transistor T3, so the transistor T2 is turned on. When transistor T2 is turned on, transistors T1 and T2 divide the voltage level of node Vp. Thereafter, the voltage level of node Vp is gradually pulled down.

In the time interval P3, the gate signal G1 is at a low voltage level, and the gate signal G2 is at a high voltage level. Transistor T1 is not conducting at this time, and transistors T2 and T3 are conducting. The voltage level of the node Vp is gradually pulled down to the voltage level V2 close to the power supply voltage Vss via the transistor T2.

During the time interval P4, the gate signals G1 and G2 are both at low voltage levels. At this time, the transistors T1, T2, and T3 are not turned on. The voltage level of the node Vp is maintained at a voltage level V2 close to the power supply voltage Vss.

In the time interval P5, the gate signals G1 and G2 are both at a low voltage level, and the gate signal G3 is at a high voltage level in the initial state of the time interval P5. At this time, the transistors T1, T2, and T3 are not turned on, and the transistor T4 is turned on. Since the transistor T4 is turned on, the node Vq is reset by the reset voltage Vreset.

At the time interval P6, the data signal Data changes from 15V to 0V. The gate signal G1 is a high voltage level, and the gate signal G2 is a low voltage level. At this time, the transistor T1 is turned on again, and the transistors T2 and T3 are not turned on. The power supply voltage Vdd is transmitted to the node Vp via the transistor T1. The voltage level of the node Vp is gradually pulled up to a voltage level V1 close to the power supply voltage Vdd.

During the time interval P7, the gate signals G1 and G2 are both at high voltage levels. At this time, the transistors T1 and T3 are turned on. The data signal Data is transmitted to the node Vq via the transistor T3. Since the data signal Data is 0V, the transistor T2 is not turned on. The voltage level of the node Vp is maintained at a voltage level close to the power supply voltage Vdd, that is, the voltage level of the node Vp is maintained at approximately 40V. In some embodiments, during the time interval P7, the voltage level of the node Vp may drop slightly.

In the time interval P8, the gate signal G1 is at a low voltage level, and the gate signal G2 is at a high voltage level. At this time, transistors T1 and T2 are not conducting, and transistor T3 is conducting. The voltage level of the node Vp is maintained at a voltage level close to the power supply voltage Vdd.

In the time interval P9, the gate signals G1 and G2 are both at a low voltage level. At this time, the transistors T1, T2, and T3 are not turned on. The voltage level of the node Vp is maintained at a voltage level close to the power supply voltage Vdd.

In the time interval P10, the gate signals G1 and G2 are at a low voltage level, and the gate signal G3 is at an initial state in the time interval P10 at a high voltage level. At this time, the transistors T1, T2, and T3 are not turned on, and the transistor T4 is turned on. Because the transistor T4 is turned on, the node Vq is reset by the reset voltage Vreset again.

At the time interval P11, the data signal Data changes from 0V to 5.6V. At this time, the gate signal G1 is at a high voltage level, and the gate signal G2 is at a low voltage level. At this time, the transistor T1 is turned on, and the transistors T2 and T3 are not turned on. The voltage level of the node Vp is pulled up again to a voltage level V1 close to the power supply voltage Vdd, that is, the voltage level of the node Vp is gradually pulled up to close to 40V.

At the time interval P12, the gate signals G1 and G2 are both high power Pressure level. At this time, the transistors T1 and T3 are turned on. The data signal Data is transmitted to the node Vq through the transistor T3, so the transistor T2 is turned on. When transistor T2 is turned on, transistors T1 and T2 divide the voltage level of node Vp. Thereafter, the voltage level of node Vp is gradually pulled down.

In the time interval P13, the gate signal G1 is at a low voltage level, and the gate signal G2 is at a high voltage level. Transistor T1 is not conducting at this time, and transistors T2 and T3 are conducting. The voltage level of the node Vp is gradually pulled down to the voltage level V3 via the transistor T2.

In the time interval P14, the gate signals G1 and G2 are both at a low voltage level. At this time, the transistors T1, T2, and T3 are not turned on. The voltage level of the node Vp is maintained at the voltage level V3, and is maintained at the voltage level V3 during a period when neither of the transistors T1 and T3 is conducting.

In some embodiments, the voltage level of the node Vp is inversely related to the voltage level of the data signal Data. For example, see Figures 2A and 2B. In the time interval P2, the gate signals G1 and G2 are both high voltage levels, and the voltage level of the data signal Data is 15V, that is, the data signal Data is a higher voltage level. At this time, the transistors T1, T2, and T3 are all turned on, and the voltage level of the node Vp decreases from the voltage level V1 to the voltage level V2. It can be seen from FIG. 2B that the voltage level V2 is a relatively low voltage level.

Conversely, in the time interval P7, the gate signals G1 and G2 are both high voltage levels, and the voltage level of the data signal Data is the voltage level 0V, that is, the data signal Data is a lower voltage level. At this time, the transistors T1, T2, and T3 are all turned on, and the voltage level of the node Vp is maintained close to the voltage level V1. That is, the power saving Vp is maintained at a relatively high voltage level.

It can be known from the above that when the voltage level of the data signal Data is higher, the voltage level of the node Vp is lower. Conversely, when the voltage level of the data signal Data is lower, the voltage level of the node Vp is higher. That is, the voltage level of the node Vp is negatively related to the voltage level of the data signal Data.

In detail, in some embodiments, the voltage level of the node Vp can be controlled by adjusting the signal received by the control terminal of the transistor T2. In some embodiments, the voltage level of the node Vp may be controlled between 15V and 20V as the voltage level for driving the display unit 210.

In some embodiments, see FIG. 3A. FIG. 3A is a schematic diagram of a pixel circuit 300A according to some embodiments of the present invention. The difference between the pixel circuit 300A and the pixel circuit 200A is that the pixel circuit 300A does not include the transistor T4.

Please also refer to Figure 3B. FIG. 3B is a control waveform diagram 300B for driving the pixel circuit 300A in FIG. 3A according to some embodiments of the present invention. The control waveforms 200B and 300B perform the same operations in the time interval P1 to P10, and the difference between the control waveforms 200B and 300B is the operation after the time interval P11. In the control waveform diagram 300B, before the transistor T3 is not turned on, the control terminal of the transistor T2 receives the data signal Data of a low voltage level, so that the Vq voltage is reduced, and the transistor T2 is not turned on.

For example, see Figures 3A and 3B. In the time interval P12, the gate signals G1 and G2 are both at a high voltage level. At this time, the transistors T1 and T3 are turned on, and the data signal Data is transmitted to the node Vq through the transistor T3 to enable the transistor T2 to turn on. After transistor T2 is turned on, the voltage level of node Vp is pulled down.

In the time interval P13, the gate signal G1 is a low voltage level, the gate signal G2 is a high voltage level, and the data signal Data is a low voltage level. At this time, the transistor T1 is not turned on, and the transistor T3 is turned on. The data signal Data is transmitted to the node Vq through the transistor T3. Because the data signal Data is at a low voltage level, the Vq voltage is reduced, and the transistor T2 is not turned on. In this way, in this case, the overall operation can still be completed without using the transistor T4 shown in FIG. 2A by the above-mentioned operation mode.

During the time interval P14, the gate signals G1 and G2 are at low voltage levels, and the transistors T1 and T3 are not turned on. Moreover, as described above, before the transistor T3 is not turned on, the voltage level received by the control terminal of the transistor T2 has been turned to a low voltage level, so that the transistor T2 is not turned on.

In some embodiments, the data signal Data is a positive polarity driving voltage at a high voltage level, and the data signal Data is a negative polarity driving voltage at a low voltage level. In other words, during the time interval P12, when the transistors T1 and T3 are turned on and the data signal Data is a positive polarity driving voltage, the transistor T2 is turned on. The voltage level of the node Vp is pulled down from the voltage level V1 to the voltage level V3. In the time interval P13, when the gate signal G1 is at a low voltage level, the gate signal G2 is at a high voltage level, and when the data signal Data is a negative driving voltage, the transistor T2 is not turned on.

Please also refer to Figure 1A. In some embodiments, when the voltage level of the node Vp is the voltage level V2, the switch module 200 in FIG. 1A is a black screen. When the voltage level of Vp is the voltage level V3, the switch module 200 in FIG. 1A is a transparent screen.

In some embodiments, the transparent display panel 110 may be organic A diode light emitting display (OLED), and the switch module 130 may be a cholesterol-type liquid crystal display, but the present invention is not limited to the above embodiment.

Please refer to FIG. 4A and FIG. 4B together. FIG. 4A is a schematic diagram of a conventional transparent display 400A. FIG. 4B is a schematic diagram of a transparent display 400B according to some embodiments of the present invention. As shown in FIG. 4A and FIG. 4B, in the display screen of the conventional transparent display 400A, since the places that should not be transparent are also displayed as transparent, the physical objects located behind the traditional transparent display 400A will penetrate the display of the traditional transparent display 400A. Areas that should not be transparent (such as portrait images) appear in the picture. On the contrary, in the display screen of the transparent display 400B of the embodiment of the present invention, since the transparent place is displayed as transparent, and the non-transparent place is displayed as opaque, the physical object behind the transparent display 400B does not penetrate the transparent display 400B. Display areas that should not be transparent (such as portrait images) appear.

See Figure 4C. FIG. 4C is a detailed schematic diagram of a transparent display 400B shown in FIG. 4B according to some embodiments of the present invention. As shown in FIG. 4C, the transparent display 400B includes a transparent display panel 400B1 and a switch module 400B2. The transparent display panel 400B1 displays a colored portrait pattern, and the switch module 400B2 displays black at the relative position where the transparent display panel 400B1 displays the colored portrait pattern, so that the place where the colored portrait pattern is displayed does not appear translucent, thereby solving the transparent display. The black display pixel of the panel 400B1 has a problem of light leakage and increases the contrast of the display screen of the transparent display 400B. In this way, the physical object located behind the transparent display 400B does not penetrate through the display screen of the transparent display 400B and should not appear.

It can be known from the implementation of the above-mentioned case that the embodiments of the present case provide an organic light emitting diode transparent display and a cholesterol-type display by providing a pixel circuit and a transparent display, and in particular, a pixel circuit and a transparent display related to a cholesterol-type liquid crystal The liquid crystal display is combined to solve the problem of light leakage of the black display pixels of the organic light-emitting diode transparent display by blocking the cholesteric liquid crystal added with a dichroic dye, thereby increasing the contrast of the display. In addition, the size of the driving voltage provided to the cholesteric liquid crystal display is controlled by the pixel circuit so that the pixel electrode reaches an ideal potential. For example, when driving a cholesteric liquid crystal, the ideal potential may be about 15V to 20V. In this way, the pixel circuit in the transparent display can display transparent or black according to actual needs.

Although this case has been disclosed as above in the form of implementation, it is not intended to limit the case. Any person skilled in this art can make various changes and retouches without departing from the spirit and scope of this case. The attached application patent shall prevail.

Claims (11)

A pixel circuit for driving a display unit includes: a first transistor including: a first terminal for receiving a first power supply voltage; a control terminal for receiving a first gate signal; And a second terminal; a second transistor comprising: a first terminal coupled to a first node with the second terminal of the first transistor; a control terminal; and a second terminal for: Receiving a second power supply voltage; and a third transistor including: a control terminal for receiving a second gate signal; a first terminal for receiving a data signal; and a second terminal for connection with the The control terminal of the second transistor is coupled to a second node, thereby controlling the conduction state of the second transistor. The pixel circuit according to claim 1, wherein the pixel circuit determines a voltage level of the first node according to a conduction state of the first transistor and the second transistor to drive the display unit. The pixel circuit according to claim 1, wherein when the first transistor is turned on and the third transistor is not turned on, the first power voltage is transmitted to the first node through the first transistor, which is pulled up by Voltage of one of the first nodes Level to a first voltage level. The pixel circuit according to claim 3, wherein when the first transistor and the third transistor are turned on, when one level of the data signal is a first positive polarity driving voltage, the second transistor It is turned on, and the first power voltage is transmitted to the first node through the first transistor, and the voltage level of the first node is pulled down to a second voltage level. The pixel circuit according to claim 4, wherein when the first transistor is turned on and the third transistor is not turned on, the voltage level of the first node is pulled up from the second voltage level to the first voltage level. A voltage level, and the voltage level of the first node is negatively related to the level of the data signal. The pixel circuit according to claim 5, wherein when the first transistor and the third transistor are turned on, when the level of the data signal is a second positive driving voltage, the second transistor Turn on, the voltage level of the first node is pulled down from the first voltage level to a third voltage level, and is maintained at the third voltage level during the non-conduction period of the first transistor and the third transistor When the first transistor is turned on again, the voltage level of the first node is pulled up from the third voltage level by the first voltage level. The pixel circuit according to claim 6, wherein when the first transistor and the third transistor are turned on, when the level of the data signal is a second negative driving voltage, the second transistor Continuity, the first node The voltage level is pulled down from the first voltage level to the third voltage level, and is maintained at the third voltage level during a period when the first transistor and the third transistor are not conducting. The pixel circuit according to claim 7, wherein before the third transistor is turned off, the control terminal of the second transistor receives the data signal at a low voltage level so that the second transistor is not turned on. . The pixel circuit according to claim 6, wherein when the first transistor and the third transistor are turned on, when the level of the data signal is a third positive polarity driving voltage, the second transistor Turn on, the voltage level of the first node is pulled down from the first voltage level to the third voltage level, and when the level of the data signal is a third negative driving voltage, the second voltage The crystal is not conducting. The pixel circuit according to claim 1, further comprising: a fourth transistor, including: a first terminal, the control terminal of the second transistor is coupled to the second node; a second terminal, For receiving a reset voltage and a control terminal for receiving a third gate signal; wherein when the first transistor and the third transistor are not conductive, the fourth transistor is based on the third gate The signal is turned on to transmit the reset voltage to the second node, so that the second transistor is not turned on. A transparent display includes: a transparent display panel; and a switch module disposed on one side of the light-emitting surface of the transparent display panel, wherein the switch module includes a plurality of items such as any one of claims 6 to 9. In the pixel circuit, when the voltage level of the first node is the third voltage level, the corresponding switch module is displayed as a transparent screen, and when the voltage level of the first node is the At the second voltage level, the corresponding switch module is displayed as a black screen, wherein the second voltage level is lower than the third voltage level.