TWI848399B - Display panel - Google Patents

Abstract

A display panel includes a substrate, a pixel array, a plurality of display pads, an electrode array and a plurality of touch pads. The pixel array includes a plurality of pixels, and the pixel array is disposed in an active area of the substrate. The display pads are disposed in a bonding area of ​​the substrate. The display pads are electrically coupled to the pixels through a plurality of data lines, and the display pads are configured to transmit a plurality of data voltages to corresponding pixels. The electrode array is disposed in the active area of the substrate, and the electrode array includes a plurality of electrode blocks. The touch pads are disposed in the bonding area of ​​the substrate. The touch pads are respectively electrically coupled to the electrode blocks through a plurality of transmission lines, wherein the touch pads are floating pads in conjunction with a single display chip device.

Description

Display Panel

This case relates to a display panel, and more particularly to a technology for using a display chip in a touch panel.

In some display panel technologies, the structural difference between some embedded touch panels and pure display panels is that the embedded touch panels have an electrode array while the pure display panels have a common electrode layer. In such a case, how to use the embedded touch panel with a similar structure as the pure display panel as a pure display panel to reduce the total number of masks in the manufacturing process, thereby reducing costs, is an important issue in this field.

The present disclosure document provides a display panel. The display panel includes a substrate, a pixel array, a plurality of display pads, an electrode array, and a plurality of touch pads. The pixel array includes a plurality of pixels, and the pixel array is disposed in a display area on the substrate. The display pads are disposed in an installation area of the substrate. The display pads are electrically coupled to the pixels via a plurality of data lines, and the display pads are used to transmit a plurality of data voltages to corresponding ones of the pixels. The electrode array is disposed in the display area on the substrate, and the electrode array includes a plurality of electrode blocks. The touch pads are disposed in the installation area of the substrate. The pads are electrically coupled to the electrode blocks through a plurality of transmission lines, respectively, and are matched with a display type single chip. The touch pads are floating pads.

The present disclosure document provides a display panel. The display panel includes a substrate, a pixel array, an electrode array, and a display chip. The pixel array includes a plurality of pixels disposed in a display area on the substrate. The electrode array includes a plurality of electrode blocks disposed in a display area on the substrate. The display chip is disposed in a mounting area on the substrate. The single chip has no touch function and does not provide a touch signal.

In summary, the present disclosure sets some pads in a display panel as floating pads, so that the display panel with an electrode array is used as a pure display circuit.

The following is a detailed description of the embodiments with the attached diagrams, but the embodiments provided are not intended to limit the scope of the disclosure, and the description of the structure operation is not intended to limit its execution order. Any device with equal functions produced by the re-combination of components is within the scope of the disclosure. In addition, the diagrams are for illustration purposes only and are not drawn according to the original size. For ease of understanding, the same or similar components in the following description will be marked with the same symbols.

The terms used throughout the specification and claims generally have the ordinary meanings of each term used in the art, in the context of this disclosure and in the specific context, unless otherwise specified.

In addition, the terms "include", "including", "have", "contain", etc. used in this article are open terms, which means "including but not limited to". In addition, "and/or" used in this article includes any one or more items in the relevant enumerated items and all combinations thereof.

In this article, when an element is referred to as "coupled" or "coupled", it may refer to "electrically coupled" or "electrically coupled". "Coupled" or "coupled" may also be used to indicate the coordinated operation or interaction between two or more elements. In addition, although the terms "first", "second", etc. are used in this article to describe different elements, the terms are only used to distinguish between elements or operations described with the same technical terms.

Please refer to FIG. 1, which is a schematic diagram of a display panel 100 according to some embodiments of the present disclosure. As shown in FIG. 1, the display panel 100 includes a substrate SUBa, a pixel array PIX, a gate drive circuit GOA, a single chip device 140, an electrode array 110, a first switch group 120, a second switch group 130, a flexible printed circuit board FPC, a printed circuit board assembly PCBA, and a power management integrated circuit PMIC.

In some embodiments, if the display panel 100 is implemented as a pure display panel, the single-chip device 140 will use a pure display driver chip (e.g., a timing controller embedded driver (TED or source driver)) to drive the pixel array PIX of the display panel 100. If the display panel 100 is implemented as a pure display panel, how to operate the electrode array 110 in the display panel 100 as a common electrode layer in the pure display panel to reduce the unevenness of the display screen will be described in detail in subsequent embodiments.

In some embodiments, the substrate SUBa is implemented by a glass substrate. In some embodiments, the pixel array PIX and the electrode array 110 are disposed in a display area of the substrate SUBa. Furthermore, the pixel array PIX and the electrode array 110 are disposed in adjacent layers.

In some embodiments, the gate drive circuit GOA is disposed in the non-display area of the substrate SUBa. The gate drive circuit GOA is electrically coupled to the pixel array PIX via gate lines (e.g., gate lines G1-G3), and the single chip device 140 is electrically coupled to the pixel array PIX via data lines (e.g., data lines D1-D3).

In some embodiments, the single chip device 140 is disposed in the mounting area of the substrate SUBa. The single chip device 140 is electrically coupled to the electrode array 110 via transmission lines (e.g., transmission lines L1-L4), and the electrode array 110 is electrically coupled to the test pads 32-35 via the transmission lines (e.g., transmission lines L1-L4) and the second switch group 130. The number of the test pads 32-35 is used for example. In other embodiments, the number of the test pads is greater or less, and the present invention is not limited thereto.

Please refer to FIG. 1 and FIG. 2 together. FIG. 2 is a schematic diagram illustrating pixels SB11-SB12 and SB21-SB22 in the pixel array PIX of FIG. 1 according to some embodiments of the present disclosure.

As shown in FIG. 2 , pixels in the same pixel row in the pixel array PIX (e.g., pixels SUB11 and SU12 or SUB21 and SUB22) are connected to the gate drive circuit GOA via gate lines G1 and G2 extending along a first direction (e.g., horizontal direction) to transmit a scanning signal to the corresponding pixel row through the gate lines G1-G2. Pixels in the same row in the pixel array PIX (e.g., pixels SUB11 and SU21 or SUB12 and SUB22) are connected to the single chip device 140 via data lines D1-D2 extending along a second direction (e.g., vertical direction) to transmit a data voltage to the corresponding pixel through the data lines D1-D2.

The pixel SB11 includes a transistor TRA1, a pixel electrode PE, a common electrode CE, a liquid crystal layer LCL, and a pixel capacitor Cst. The gate terminal of the transistor TRA1 is electrically coupled to the gate line G1, the first end of the transistor TRA1 is electrically coupled to the data line D1, and the second end of the transistor is electrically coupled to the pixel electrode PE and the pixel capacitor Cst. The liquid crystal layer LCL is between the pixel electrode PE and the common electrode CE. In some embodiments, the common electrode CE corresponds to the electrode block of the electrode array 110.

Please refer to FIG. 1 and FIG. 3 together. FIG. 3 is a schematic diagram of a substrate SUBa according to some embodiments of the present disclosure. In the embodiment of FIG. 3, for better understanding, only 3*4 electrode blocks are shown. In practice, the electrode array 110 includes n*m electrode blocks arranged in an array, where "n" and "m" are positive integers. Therefore, the present invention is not limited thereto. The electrode array 110 is electrically coupled between the first switch group 120 and the second switch group 130.

The first switch group 120 and the second switch group 130 are disposed on opposite sides of the display area AA of the substrate SUBa along the horizontal direction, and the electrode blocks 112, 114, 116, and 118 are electrically coupled between the first switch group 120 and the single-chip device 140 and the second switch group 130 through transmission lines L1-L4 extending along the second direction (e.g., the vertical direction). Functionally, the first switch group 120 and the second switch group 130 are used to be turned on according to control signals CS1 and CS2 provided by the single-chip device 140, respectively, so that the potential of the common electrode voltage VCOM is transmitted to the electrode blocks 112, 114, 116, and 118 through the transmission lines L1-L4, so as to be implemented as a common electrode.

In some embodiments, the transmission lines L1-L4 are used to transmit the common electrode voltage VCOM to the electrode blocks in the electrode array 110 to stabilize the potential of the electrode blocks in the electrode array 110, thereby improving the problem of uneven display and color difference of the display panel 100a caused by the unstable potential of the electrode blocks.

Specifically, please refer to Figure 1, Figure 3 and Figure 4, Figure 4 is a schematic diagram of a substrate SUBa according to some embodiments of the present disclosure. The display panel 100 includes a first switch group 120, a second switch group 130 and an electrode array 110 disposed on the substrate SUBa.

The first switch group 120 includes first switches STP1-STP4. Specifically, the first ends of the first switches STP1-STP4 are used to receive the common electrode voltage VCOM, and the second ends of the first switches STP1-STP4 are electrically coupled to the first ends of the transmission lines L1-L4. The gate ends of the first switches STP1-STP4 are used to receive the control signal CS1, and the first switches STP1-STP4 are turned on according to the control signal CS1 to transmit the common electrode voltage VCOM to the electrode blocks 112, 114, 116 and 118 in the electrode array 110 through the transmission lines L1-L4.

The second switch group 130 includes second switches SCT1-SCT4. Specifically, the first ends of the second switches SCT1-SCT4 are electrically coupled to the second ends of the transmission lines L1-L4, respectively, and the second ends of the second switches SCT1-SCT4 are used to receive the common electrode voltage VCOM. The gate ends of the second switches SCT1-SCT4 are used to receive the control signal CS2, and the second switches SCT1-SCT4 are used to be turned on according to the control signal CS2 to transmit the common electrode voltage VCOM to the electrode blocks 112, 114, 116 and 118 in the electrode array 110 through the transmission lines L1-L4.

In some embodiments, the power management integrated circuit PMIC is electrically coupled to the second ends of the second switches SCT1-SCT4 and the first ends of the first switches STP1-ST4, and the common electrode voltage VCOM is provided by the power management integrated circuit PMIC. In other embodiments, the single-chip device 140 is electrically coupled to the second ends of the second switches SCT1-SCT4 and the first ends of the first switches STP1-ST4, and the voltage of the common electrode voltage VCOM is provided by the single-chip device 140.

In some embodiments, the electrode array 110 is connected to the test pads 32-35 in a checkerboard pattern via the second switch group 130. For example, the electrode block 112 and the electrode block 116 are connected to the test pad 32 via the second switch group 130, and the electrode block 114 and the electrode block 118 are connected to the test pad 33 via the second switch group 130. In this way, the electrode blocks in each test area can be tested through the test pads 32-35 during the test phase.

In some embodiments, the mounting area BA of the substrate SUBa is used to mount the single chip device 140. The mounting area BA of the substrate SUBa includes touch pads (e.g., touch pads 11-14) and display pads 40. The touch pads 11-14 are electrically coupled to the electrode blocks 112, 114, 116, and 118 respectively through transmission lines L1-L4. The display pad 40 is electrically coupled to the data line (such as the data lines D1-D3 shown in FIG. 1), and the display pad 40 is used to transmit a plurality of data voltages to the corresponding ones of the pixels through the data line.

Please refer to FIG. 1 and FIG. 3 to FIG. 5A. FIG. 5A is a schematic diagram of pins of a touch and display driver integrated chip TDDI according to some embodiments of the present disclosure. In some embodiments, if the single chip device 140 is implemented by a touch and display driver integrated chip TDDI, after the touch and display driver integrated chip TDDI is installed in the installation area BA on the substrate SUBa, a plurality of output pins (e.g., touch pins TPIN and display pins DPIN) of the touch and display driver integrated chip TDDI are electrically coupled to touch pads (e.g., touch pads 11-14) and display pads 40, respectively. A plurality of input pins INPIN of the touch and display driver integrated chip TDDI are electrically coupled to a plurality of pads 50 respectively.

Please refer to FIG. 1, FIG. 3 to FIG. 4 and FIG. 5B. FIG. 5B is a schematic diagram of the pins of the timing controller embedded driver TED according to some embodiments of the present disclosure. If the single-chip device 140 is implemented by a pure display chip (e.g., a timing controller embedded driver TED), after installing the timing controller embedded driver TED to the installation area BA on the substrate SUBa, the multiple output pins (e.g., display pins DPIN) of the timing controller embedded driver TED are respectively electrically coupled to the display pads 40. The multiple input pins INPIN of the timing controller embedded driver TED are respectively electrically coupled to the multiple pads 50.

It should be noted that since the timing controller embedded driver TED does not have touch pins, after the timing controller embedded driver TED is installed in the installation area BA on SUBa, the timing controller embedded driver TED is electrically insulated from the touch pads 11~14 on the substrate SUBa, and the touch pads 11~14 will be in a floating state, making the touch pads 11~14 floating pads.

In some embodiments, another portion of the output pins of the timing controller embedded driver TED is used to electrically couple the pads 21, 22, and 31. In some embodiments, the timing controller embedded driver TED transmits the control signal CS1 to the gate terminals of the first transistors STP1-STP4 via the pad 21, and the timing controller embedded driver TED transmits the control signal CS2 to the gate terminals of the second transistors SCT1-SCT4 via the pad 31.

In some embodiments, please refer to FIG. 1, FIG. 3 to FIG. 4, and FIG. 6 to FIG. 8. FIG. 6 to FIG. 8 are schematic diagrams showing the timing of the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the control signals CS1a~CS1c and CS2a~CS2c when the single-chip device 140 is implemented by a pure display chip according to some embodiments of the present disclosure. The control signals CS1a~CS1c correspond to the control signals CS1 of FIG. 3 and FIG. 4, and the control signals CS2a~CS2c correspond to the control signals CS2 of FIG. 3 and FIG. 4.

In some embodiments, the duration of the horizontal synchronization signal Hsync in the first phase (display phase) T1 of a cycle is greater than the scanning time of at least one gate line (for example, in the first phase T1 in FIG. 6 , the horizontal synchronization signal Hsync has a plurality of pulses, each pulse representing the scanning action of the gate drive circuit GOA on a gate line), and the duration of the horizontal synchronization signal Hsync in the second phase T2 of the cycle is in the range of 100 to 600 microseconds. In some embodiments, the duration of the long vertical blanking mode LVM of the single-chip device 140 in a frame is greater than 700 microseconds.

In the embodiment of FIG. 6 , the control signal CS1a provided by the single-chip device 140 is maintained at a high logic level HH in one frame to control the switch in the first switch group 120 to be turned on, so that the common electrode voltage VCOM is transmitted to the electrode array 110 via the first switch group 120, thereby stabilizing the potential of the electrode blocks (e.g., electrode blocks 112-118) of the electrode array 110 at the common electrode potential DC-VCOM in one frame, thereby improving the picture uniformity.

The single chip device 140 generates a control signal CS2a according to the horizontal synchronization signal Hsync. In the long horizontal blanking mode LHM, CS2a has a plurality of pulses. In the first stage T1 of the long horizontal blanking mode LHM, the control signal CS2a has a high logic level HH to control the switch in the second switch group 130 to be turned on, so that the common electrode voltage VCOM is transmitted to the electrode array 110 through the first switch group 120 and the second switch group 130, so that during the operation period of the pixel array PIX, the potential of the electrode blocks (e.g., electrode blocks 112-118) of the electrode array 110 is reset and stabilized at the common electrode potential DC-VCOM, thereby improving the picture uniformity.

In the embodiment of FIG. 7 , the control signal CS2b provided by the single-chip device 140 is maintained at a high logic level HH in one frame to control the switch in the second switch group 130 to be turned on, so that the common electrode voltage VCOM is transmitted to the electrode array 110 via the second switch group 130, thereby stabilizing the potential of the electrode blocks (e.g., electrode blocks 112-118) of the electrode array 110 at the common electrode potential DC-VCOM in one frame, thereby improving the picture uniformity.

The single chip device 140 generates a control signal CS1b according to the horizontal synchronization signal Hsync. In the long horizontal blanking mode LHM, CS1b has a plurality of pulses. In the first stage T1 of the long horizontal blanking mode LHM, the control signal CS1b has a high logic level HH to control the switch in the first switch group 120 to be turned on, so that the common electrode voltage VCOM is transmitted to the electrode array 110 through the first switch group 120, thereby resetting and stabilizing the potential of the electrode blocks (e.g., electrode blocks 112-118) of the electrode array 110 at the common electrode potential DC-VCOM during the operation period of the pixel array PIX, thereby improving the picture uniformity.

In the embodiment of FIG. 8 , during the operation of the pixel array PIX, the single chip device 140 provides a potential having an enable level (e.g., a high logic level HH) as control signals CS1c and CS2c, so as to control the first switch group 120 and the second switch group 130 to be turned on and transmit the common electrode voltage VCOM to the electrode array 110 according to the control signals CS1c and CS2c, so as to stabilize the potential of the electrode blocks (e.g., 112 to 118) of the electrode array 110 at the common electrode potential DC-VCOM during the operation of the pixel array PIX, thereby improving the picture uniformity.

Please refer to FIG. 1 and FIG. 9. FIG. 9 is a schematic diagram of a substrate SUBb according to some embodiments of the present disclosure. In some embodiments, the substrate SUBa of the display panel 100 in FIG. 1 can be implemented by the substrate SUBb in FIG. 9.

Compared with the substrate SUBa in the embodiment of FIG. 4, the substrate SUBb in the embodiment of FIG. 9 is different in that the second switch group 130 is not provided. Specifically, the electrode blocks 112-118 in the electrode array 110 are connected to the wiring of the test pads 32 and 33 through the transmission lines L1-L4, and the wiring of the test pads 32 and 33 is used to receive the common electrode voltage VCOM, so as to transmit the potential of the common electrode voltage VCOM to the electrode blocks 112-118 through the transmission lines L1-L4.

In some embodiments, if the display panel 100 is used as a touch display panel, the path of the electrode array 110 directly electrically connected to the common electrode VCOM must be cut off.

In order to cut off the path of the electrode array 110 directly electrically connected to the common electrode VCOM, the circuit path between the transmission lines L1-L4 and the test pads 32 and 33 can be cut along the horizontal axis according to the laser cutting marks 61-62, and the electrode array 110 can be used as a touch electrode array in combination with a touch display driver chip.

In some embodiments, if the display panel 100 is used as a pure display panel, the circuit paths between the transmission lines L1-L4 and the wiring of the test pads 32 and 33 can be retained, so as to transmit the common electrode voltage VCOM from the wiring of the test pads 32 and 33 to the electrode array 110, and used in conjunction with a pure display chip. The other detailed connection relationships and operation methods of the substrate SUBb are roughly the same as those of the substrate SUBa in the embodiment of FIG. 4 above, and are not further described here.

Please refer to FIG. 10A and FIG. 10B. FIG. 10A is a schematic diagram showing a stacked structure of the display panel 100 in FIG. 1 according to some embodiments of the present disclosure. FIG. 10B is a schematic diagram showing a stacked structure of a display panel according to other embodiments.

As shown in FIG. 10A , the display panel 100 includes a polarizing layer PL, a glass substrate GL, a filter layer LC, an electrode array 110, and a pixel array AR. The pixel array AR in FIG. 10A corresponds to the pixel array PIX of the display panel 100 in FIG. 1 . The electrode array 110 in FIG. 10A corresponds to the electrode array 110 on the substrate SUBa or SUBb in FIG. 4 and FIG. 9 . In this case, during the operation of the pixel array PIX, the potential of the electrode array 110 is stabilized by the operation method in the above embodiment, so that the electrode blocks (e.g., electrode blocks 112, 114, 116 and 118) of the electrode array 110 can be used as common electrodes of a pure display panel, thereby improving the uniformity of the display screen of the display panel 100.

In summary, the present disclosure sets some pads in the display panel 100 as floating pads, so that the display panel 100 having the electrode array 110 is used as a pure display panel. Furthermore, the display panel 100 controls the switching of the first switch group 120 and/or the second switch group 130 to transmit the common electrode voltage VCOM to the electrode array 110, thereby improving the uniformity of the display screen of the display panel 100.

Although the present disclosure has been disclosed in the above implementation form, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the attached patent application.

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understandable, the attached symbols are explained as follows 11~14: touch pads 21~22,31,50: pads 40: display pads 32~35: test pads 100: display panel 110: electrode array 120: first switch group 130: second switch group 140: single chip device Vsync: vertical synchronization signal Hsync: horizontal synchronization signal LHM: long time horizontal blanking mode LVM: long time vertical blanking mode HL: high logic level LL: low logic level STP1~STP4: first switch SCT1~SCT4: second switch SUBa,SUBb:substrate SB11,SB12,SB21,SB22:pixel LCL:liquid crystal layer PE:pixel electrode CE:common electrode Cst:pixel capacitor PIX:pixel array G1~G3:gate line D1~D3:data line L1~L4:transmission line TPIN:touch pin DPIN:display pin IPIN:input pin TDDI:touch and display driver integrated chip TED:timing controller embedded driver CS1,CS2:control signal GOA:gate driver circuit FPC:flexible printed circuit board PCBA:printed circuit board assembly PMIC:power management integrated circuit VCOM: common electrode voltage PL: polarizing layer GL: glass substrate LC: filter layer ITO: conductive layer AR: pixel array

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understandable, the attached drawings are described as follows: Figure 1 is a schematic diagram of a display panel drawn according to some embodiments of the present disclosure. Figure 2 is a schematic diagram of a pixel in a pixel array of Figure 1 drawn according to some embodiments of the present disclosure. Figure 3 is a schematic diagram of a substrate drawn according to some embodiments of the present disclosure. Figure 4 is a schematic diagram of a substrate drawn according to some embodiments of the present disclosure. Figure 5A is a schematic diagram of the pins of a touch and display driver integrated chip drawn according to some embodiments of the present disclosure. Figure 5B is a schematic diagram of the pins of a timing controller embedded driver drawn according to some embodiments of the present disclosure. Figures 6 to 8 are schematic diagrams of the timing of horizontal synchronization signals, vertical synchronization signals, and control signals when a single-chip device is implemented by a pure display chip according to some embodiments of the present disclosure. Figure 9 is a schematic diagram of a substrate according to some embodiments of the present disclosure. Figure 10A is a schematic diagram of a stacked configuration of a display panel in Figure 1 according to some embodiments of the present disclosure. Figure 10B is a schematic diagram of a stacked configuration of a display panel according to other embodiments.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

32~35: Test pins

100: Display panel

110:Electrode array

120: First switch group

130: Second switch group

140: Single chip device

SUBa: Substrate

PIX: Pixel array

G1~G3: Gate line

D1~D3: Data line

L1~L4: Transmission line

GOA: Gate-Actuating Circuit

FPC: Flexible Printed Circuit Board

PCBA: Printed Circuit Board Assembly

PMIC: Power Management Integrated Circuit

VCOM: common electrode voltage

Claims (10)

A display panel comprises: a substrate; a pixel array comprising a plurality of pixels disposed in a display area on the substrate; a plurality of display pads disposed in a mounting area on the substrate, electrically coupled to the pixels via a plurality of data lines, the display pads being used to transmit a plurality of data voltages to corresponding ones of the pixels; an electrode array comprising a plurality of electrode blocks disposed in the display area on the substrate; a plurality of touch pads disposed in the mounting area on the substrate, the touch pads being respectively connected to the electrodes via a plurality of data lines. A transmission line electrically coupled to the electrode blocks, wherein the touch pads are floating pads; a first switch group electrically coupled between the electrode array and a wiring of a common electrode voltage, wherein the first switch group is turned on according to a first control signal to transmit the common electrode voltage to the electrode array; and a second switch group electrically coupled between the electrode array and the wiring of the common electrode voltage, wherein the second switch group is turned on according to a second control signal to transmit the common electrode voltage to the electrode array. The display panel as described in claim 1 further comprises: a single chip device disposed in the installation area, wherein the single chip device is electrically insulated from the touch pads so that the touch pads are used as floating pads. A display panel as described in claim 2, wherein the single-chip device is implemented by a display chip. A display panel as described in claim 1, wherein the first switch group is electrically coupled between the first end of the transmission lines and the routing of the common electrode voltage, wherein the first switch group is turned on according to the first control signal to transmit the common electrode voltage to the electrode array via the transmission lines. A display panel as described in claim 4, wherein the second switch set is electrically coupled between the second ends of the transmission lines and the routing of the common electrode voltage, wherein the second switch set is turned on according to the second control signal to transmit the common electrode voltage to the electrode array via the transmission lines. A display panel as described in claim 5, wherein one of the first control signal and the second control signal has a high logic level. A display panel as described in claim 5, wherein one of the first control signal and the second control signal is generated based on a horizontal synchronization signal. A display panel as described in claim 5, wherein the first control signal and the second control signal both have high logic level potentials. A display panel as described in claim 4, wherein the common electrode voltage is provided by a single chip device or a power management integrated circuit. A display panel comprises: a substrate; a pixel array comprising a plurality of pixels disposed in a display area on the substrate; a plurality of display pads disposed in a mounting area on the substrate and electrically coupled to the pixels via a plurality of data lines, the display pads being used to transmit a plurality of data voltages to corresponding ones of the pixels; an electrode array comprising a plurality of electrode blocks disposed in the display area on the substrate; A display area; a plurality of touch pads disposed in the mounting area on the substrate, the touch pads being electrically coupled to the electrode blocks via a plurality of transmission lines; and a single-chip device disposed in the mounting area on the substrate, wherein the single-chip device has no touch function and does not provide a touch signal, and wherein the single-chip device is electrically insulated from the touch pads, so that the touch pads are used as floating pads.

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