TWI671727B - Display panel - Google Patents

Abstract

A display panel includes a capacitor, a compensation circuit, a writing circuit, and a driving circuit. The capacitor includes a first terminal and a second terminal. The compensation circuit is coupled to the first terminal of the capacitor, for resetting the first terminal of the capacitor to a reference voltage level according to the scanning signal, and receiving the high voltage level of the receiving system according to the light-emitting control signal to output a compensation signal to the first terminal of the capacitor. . The writing circuit is coupled to the second terminal of the capacitor, and is used to selectively turn on according to the scanning signal to output a data signal to the second terminal of the capacitor. The driving circuit is coupled to the second terminal of the capacitor, and is used for selectively conducting according to the light emitting control signal to output a driving current to the light emitting element according to the voltage level of the second terminal of the capacitor.

Description

Display panel

The present disclosure relates to a display panel, and more particularly to a display panel with a compensation circuit.

With the increasing demand of digital display devices, Active Matrix Organic Light Emitting Display (AMOLED) is widely used in various digital display devices due to its excellent characteristics.

However, in the operation of an active organic light emitting diode display device, the driving current is affected by the threshold voltage of the driving transistor. Because the threshold voltages of the driving transistors are different from each other, the driving current will be generated accordingly. The difference results in inconsistent luminous brightness of the organic light emitting diode, so that the brightness of the screen is uneven when displaying the image.

One aspect of the present disclosure relates to a display panel. The display panel includes a capacitor, a compensation circuit, a writing circuit, and a driving circuit. The capacitor includes a first terminal and a second terminal. The compensation circuit is coupled to the first terminal of the capacitor, and is used to reset the first terminal of the capacitor to the reference voltage level according to the scanning signal, and according to the light-emitting control signal The receiving system has a high voltage level to output a compensation signal to the first terminal of the capacitor. The writing circuit is coupled to the second terminal of the capacitor, and is used to selectively turn on according to the scanning signal to output a data signal to the second terminal of the capacitor. The driving circuit is coupled to the second terminal of the capacitor, and is used for selectively conducting according to the light-emitting control signal to output a driving current to the light-emitting element according to the voltage level of the second terminal of the capacitor.

100‧‧‧ display panel

PI1, PI2, PI3 ‧‧‧ pixels

120‧‧‧Compensation circuit

140‧‧‧write circuit

160‧‧‧Drive circuit

OLED‧‧‧light-emitting element

TC1, TC2, TC3, TC4‧‧‧ compensating transistors

T1, T2, T3, T4‧‧‧ Transistors

C1‧‧‧capacitor

S1 [N], S1 [1], S1 [2], S1 [K] ‧‧‧Scan signal

EM [N], EM1 [N], EM2 [N], EM [G] ‧‧‧Emission control signal

Vcomp [n] ‧‧‧compensation signal

Vdata [m] ‧‧‧data signal

Vref‧‧‧Reference voltage level

OVDD‧‧‧System High Voltage Level

OVSS‧‧‧System Low Voltage Level

During P1, P2, Poff, Pon‧‧‧

FIG. 1A is a schematic diagram illustrating a display panel according to some embodiments of the present disclosure.

FIG. 1B is a schematic diagram illustrating another display panel according to some embodiments of the present disclosure.

FIG. 2 is a schematic diagram illustrating a pixel signal timing according to some embodiments of the present disclosure.

FIG. 3 is a schematic diagram illustrating states of the transistors in the display panel of FIG. 1A during the first period according to some embodiments of the present disclosure.

FIG. 4 is a schematic diagram showing states of the transistors in the display panel of FIG. 1A during the second period according to some embodiments of the present disclosure.

FIG. 5A is a schematic diagram illustrating another display panel according to other embodiments of the present disclosure.

FIG. 5B is a schematic diagram illustrating another display panel according to other embodiments of the present disclosure.

FIG. 6 is a schematic timing diagram of signals of another display panel according to other embodiments of the present disclosure.

7A and 7B are schematic diagrams illustrating another display panel and its signal timing according to other embodiments of the present disclosure.

The following is a detailed description of the embodiments in conjunction with the drawings, but the specific embodiments described are only used to explain the case, not to limit the case, and the description of the structural operation is not used to limit the order of its implementation. The recombined structure and the devices with equal effects are all covered by the present disclosure.

Please refer to Figure 1A. FIG. 1A is a schematic diagram illustrating a display panel 100 according to some embodiments of the present disclosure. In some embodiments, the display panel 100 may be an active organic light emitting diode display panel (Active Matrix Organic Light Emitting Display, AMOLED). The display panel 100 may include pixels to form a complete display screen. In FIG. 1A, only one of the pixels is shown as an exemplary description for simplicity of description.

As shown in FIG. 1A, the display panel 100 includes a compensation circuit 120 and a pixel PI1. The pixel PI1 includes a writing circuit 140, a driving circuit 160, a capacitor C1, and a light emitting element OLED. The compensation circuit 120 includes compensation transistors TC1, TC2, and TC3. The write circuit 140 includes a transistor T1. The driving circuit 160 includes transistors T2 and T3. The capacitor C1 includes a first terminal and a second terminal.

Structurally, the compensation circuit 120 is coupled to the first terminal of the capacitor C1. The writing circuit 140 is coupled to the second terminal of the capacitor C1. The driving circuit 160 is coupled to the second terminal of the capacitor C1 and the light emitting element OLED. Specifically, the first terminal of the compensation transistor TC1 is coupled to the system high voltage level OVDD. The second terminal of the compensation transistor TC1 Connect the first terminal of the compensation transistor TC2. The second terminal of the compensation transistor TC2 and the control terminal of the compensation transistor TC2 are commonly coupled to the first terminal of the capacitor C1. The first terminal of the compensation transistor TC3 is also coupled to the first terminal of the capacitor C1.

The second terminal of the transistor T1 is coupled to the second terminal of the capacitor C1. The first terminal of the transistor T2 is coupled to the system high voltage level OVDD. The control terminal of the transistor T2 is coupled to the second terminal of the capacitor C1. The second terminal of the transistor T2 is coupled to the first terminal of the transistor T3. The second terminal of the transistor T3 is coupled to the first terminal of the light-emitting element OLED. The second terminal of the light emitting element OLED is coupled to the system low voltage level OVSS.

In operation, the compensation circuit 120 is used to reset the first terminal of the capacitor C1 to the reference voltage level Vref according to the scanning signal S1 [N], and receive the system high voltage level OVDD according to the light-emitting control signal EM [N] to output compensation. The signal Vcomp [n] goes to the first terminal of the capacitor C1. The writing circuit 140 is used to selectively turn on according to the scanning signal S1 [N] to output a data signal Vdata [m] to the second terminal of the capacitor C1. The driving circuit 160 is configured to be selectively turned on according to the light emitting control signal EM [N] to output a driving current I1 to the light emitting element OLED according to a voltage level of the second terminal of the capacitor C1.

Specifically, the control terminal of the compensation transistor TC1 is used to receive the light-emitting control signal EM [N], and is selectively turned on according to the light-emitting control signal EM [N] to receive the high-voltage standard of the first end of the self-compensation transistor TC1 The bit OVDD is output to the first terminal of the compensation transistor TC2 through the second terminal of the compensation transistor TC1. The compensation transistor TC2 is used to generate a compensation signal Vcomp [n] according to the received system high voltage level OVDD, and output the compensation signal Vcomp [n] from the second terminal of the compensation transistor TC2 to the first terminal of the capacitor C1.

The first terminal of the compensation transistor TC3 is used to receive the reference voltage level. Bit Vref. The control terminal of the compensation transistor TC3 is used to receive the scanning signal S1 [N], and is selectively turned on according to the scanning signal S1 [N], so that the second terminal of the compensation transistor TC3 is reset to the reference voltage level Vref.

The first terminal of the transistor T1 in the write circuit 140 is used to receive a data signal Vdata [m]. The control terminal of the transistor T1 is used to receive the scanning signal S1 [N], and is selectively turned on according to the scanning signal S1 [N] to output the data signal Vdata [m] to the second terminal of the capacitor C1 through the second terminal of the transistor T1. end.

The first terminal of the transistor T2 in the driving circuit 160 is used to receive the system high voltage level OVDD. The transistor T2 is used to selectively turn on according to the voltage level of the control terminal of the transistor T2, so as to output the driving current I1 through the second terminal of the transistor T2. The first terminal of the transistor T3 is used to receive the driving current I1 from the second terminal of the transistor T2. The control terminal of the transistor T3 is used to receive the light-emitting control signal EM [N], and is selectively turned on according to the light-emitting control signal EM [N] to output the driving current I1 to the light-emitting element OLED through the second terminal of the transistor T3.

Please refer to Figure 1B. FIG. 1B is a schematic diagram illustrating another display panel 100 according to some embodiments of the present disclosure. As shown in FIG. 1B, in other embodiments, the first ends of the capacitors C1 of two or more pixels PI1, PI2, PI3 in the display panel 100 are coupled to each other to receive the same compensation signal Vcomp [ n]. The pixels PI2 and PI3 can be implemented by the pixel PI1 shown in FIG. 1A. The operation method is as described above, and will not be repeated here.

In other words, two or more pixels PI1, PI2, PI3 share the same compensation circuit 120. In this way, by using the one-to-many shared structure of the compensation circuit 120, the layout area can be reduced. In addition, although three pixels PI1, PI2, and PI3 are shown in FIG. 1B, the number is only an example for convenience of description, and is not intended to be used. To limit this disclosure. Those skilled in the art can set the number of pixels sharing the same compensation circuit 120 in the display panel 100 according to actual needs.

Please refer to Figure 2. FIG. 2 is a schematic diagram of signal timing of a display panel 100 according to some embodiments of the present disclosure. As shown in FIG. 2, in the first period P1, the scanning signal S1 [N] is at a low voltage level. In the second period P2, the scanning signal S1 [N] is at a high voltage level. In addition, during the first period P1, the light emission control signal EM [N] is at the off-voltage level. In the second period P2, the light emission control signal EM [N] is switched from the off-voltage level to the light-emitting voltage level. In other words, in some embodiments, the length of time during which the light-emitting control signal EM [N] is at the off-voltage level is greater than or equal to the length of the first period P1.

For the convenience of description, the specific operations of the various elements in the display panel 100 will be described in conjunction with the drawings in the following paragraphs. Please refer to Figure 2 and Figure 3 together. FIG. 3 is a schematic diagram illustrating states of the transistors in the display panel 100 in FIG. 1A during the first period P1 according to some embodiments of the present disclosure. As shown in FIG. 3, in some embodiments, the first period P1 corresponds to a reset and write period of the display panel 100.

In the first period P1, the light-emitting control signal EM [N] at the off-voltage level causes the compensation transistors TC1, TC2, and transistor T3 to be turned off. The scan signal S1 [N] at the low voltage level makes the compensation transistor TC3 and the transistor T2 conductive. Specifically, during the first period P1, the compensation transistor TC3 is turned on according to the scanning signal S1 [N] to reset the first terminal of the capacitor C1 to the reference voltage level Vref. The transistor T2 is turned on according to the scanning signal S1 [N] to output the data signal Vdata [m] to the second terminal of the capacitor C1. In other words, during the first period P1, the first terminal of the capacitor C1 is located at the reference voltage level Vref, and the second terminal of the capacitor C1 is Voltage level at the data signal Vdata [m].

Next, please refer to Figure 2 and Figure 4 together. FIG. 4 is a schematic diagram showing states of the transistors in the display panel 100 in FIG. 1A during the second period P2 according to some embodiments of the present disclosure. As shown in FIG. 4, in some embodiments, the second period P2 corresponds to a light-emitting period of the display panel 100.

In the second period P2, the scanning signal S1 [N] at the high voltage level causes the compensation transistor TC3 and the transistor T2 to be turned off. The light-emitting control signal EM [N] at the light-emitting voltage level makes the compensation transistors TC1, TC2, and transistor T3 conductive. Specifically, in the second period P2, the compensation transistors TC1 and TC2 are turned on according to the light emission control signal EM [N], and a compensation signal Vcomp [n] is generated according to the system high voltage level OVDD. Among them, since the control terminal and the second terminal of the compensation transistor TC2 are coupled, the voltage level of the compensation signal Vcomp [n] generated is the system high voltage level OVDD minus the threshold voltage of the compensation transistor TC2.

Since the voltage level of the first terminal of the capacitor C1 is changed from the reference voltage level Vref to the voltage level of the compensation signal Vcomp [n], the voltage level of the second terminal of the capacitor C1 is determined by the data signal Vdata [m The voltage level of] is converted into the voltage level of the data signal Vdata [m] plus the voltage level of the compensation signal Vcomp [n] and then subtracting the reference voltage level Vref.

In other words, the voltage level of the control terminal of the transistor T2 at this time is: V _DATA + OVDD- -Vref. Where V _DATA is the voltage level of the data signal Vdata [m], It is to compensate the critical voltage of transistor TC2.

In addition, in the second period P2, the transistor T3 is turned on according to the light emission control signal EM [N]. Therefore, the driving current I1 output according to the voltage level of the control terminal of the transistor T2 is as follows:

Among them, K is a conduction parameter. VSG is the pressure difference between the first terminal and the control terminal of transistor T2. Is the critical voltage of transistor T2.

Because the compensation transistor TC2 and the transistor T2 have the same size and are arranged close to each other, the electrical properties are approximately the same. That is, the threshold voltage of the compensation transistor TC2 is similar to the threshold voltage of the transistor T2.

In this way, the compensation signal Vcomp [n] prevents the driving current I1 from being affected by the aging of the transistor and the change of the threshold voltage. In addition, the writing of the data signal Vdata [m] and the compensation of the critical voltage difference are performed separately, so the resolution and the compensation time do not affect each other. The writing of the data signal Vdata [m] can be completed in a short time, which is suitable for High-resolution display panel for high-frequency operation.

In addition, because the data transmission line connected to the first end of transistor T1 is maintained at the voltage level of the data signal Vdata [m], the voltage level difference between the control end of transistor T2 and the data transmission line is maintained at OVDD- -Vref. Therefore, the reference voltage level Vref can be adjusted to reduce the leakage current between the control terminal of the transistor T2 and the data transmission line. In this way, the voltage level of the control terminal of the transistor T2 during the light-emitting stage can be maintained, and the pressure between the control terminal of the transistor T2 and the data transmission line is large, and flickering occurs in low frequency operation (Idle mode). (Flicker) phenomenon.

Please refer to Figure 5A. FIG. 5A is a schematic diagram illustrating another display panel 100 according to other embodiments of the present disclosure. In the embodiment shown in FIG. 5A, components similar to those in the embodiment shown in FIG. 1A are represented by the same component symbols, and their operations have been described in the previous paragraphs, and will not be repeated here. Compared with the embodiment shown in FIG. 1A, in some embodiments, as shown in FIG. 5A, the compensation circuit 120 in the display panel 100 further includes a compensation transistor TC4.

Structurally, similar to the compensation transistor TC2, the first terminal of the compensation transistor TC4 is coupled to the second terminal of the compensation transistor TC1, and the control terminal of the compensation transistor TC4 and the second terminal of the compensation transistor TC4 are coupled to each other. The second terminal of the compensation transistor TC2. In operation, the compensation transistor TC4 is used to generate a compensation signal Vcomp [n] according to the system high voltage level OVDD received by the second terminal of the self-compensation transistor TC1.

Specifically, the size of the compensation transistor TC4 is the same as that of the compensation transistor TC2. In this way, by compensating the transistors TC4 and TC2 in parallel for compensation, the charging speed can be made faster, and the first end of the capacitor C1 can be pulled to the voltage level of the compensation signal Vcomp [n] more quickly.

Please refer to Figure 5B. FIG. 5B is a schematic diagram illustrating another display panel 100 according to other embodiments of the present disclosure. In the embodiment shown in FIG. 5B, components similar to those in the embodiment shown in FIG. 1A are represented by the same component symbols, and their operations have been described in the previous paragraphs, and will not be repeated here. Compared with the embodiment shown in FIG. 1A, in some embodiments, as shown in FIG. 5B, the display panel 100 further includes a transistor T4.

Structurally, the first terminal of the transistor T4 is coupled to the control terminal of the transistor T4. The second terminal of the transistor T4 is coupled to the first terminal of the light-emitting element OLED. In operation, the first end of the transistor T4 is used to receive the scanning signal S1 [N]. The transistor T4 is used to selectively turn on according to the scanning signal S1 [N] to reset the anode of the light-emitting element OLED to a low voltage level through the second terminal of the transistor T4. In this way, the voltage level of the anode of the light-emitting element OLED is controlled by the transistor T4, so that the light-emitting element OLED remains off during the writing phase.

Please refer to Figure 6. FIG. 6 is a schematic timing diagram of signals of another display panel 100 according to other embodiments of the present disclosure. As shown in FIG. 6, in other embodiments, during the writing period Poff, the scanning signals S1 [1] to S1 [K] of the display panel 100 are sequentially turned on, and the light emission control signal EM [G] is at the off voltage. Level. During the light emission period Pon, the scanning signals S1 [1] to S1 [K] of the display panel 100 are turned off, and the light emission control signal EM [G] is at the light emission voltage level. For example, the scanning signal S1 [1] can be used to drive the pixel PI1 in Figures 1A and 1B. In this embodiment, the scanning signal S1 [1] in Figure 6 can be used to drive the transistor The gate of T1 (like the scanning signal S1 [N] in FIG. 1A and FIG. 1B). The scanning signal S1 [2] can be used to drive the pixel PI2 in FIG. 1B. By analogy, subsequent scanning signals can be used to drive other pixels in the display panel 100. The light emission control signal EM [G] is used to control the above pixels in the display panel 100 (for example, pixels PI1-PI3 in FIG. 1B) to emit light (like the light emission control signals EM in FIGS. 1A and 1B) [N]).

In other words, each pixel in the display panel 100 sequentially turns on the respective writing circuits 140 according to the scanning signals S1 [1] to S1 [K] to write data signals Vdata [m] respectively. After that, each pixel in the display panel 100 emits light according to The control signal EM [G] turns on the driving circuit 160 to light up and display together.

It is worth noting that those with ordinary knowledge in the technical field can directly understand how the signal timing of FIG. 6 is intended to perform such operations and functions based on the display panel 100 in the multiple different embodiments described above, and will not be repeated here.

Please refer to Figures 7A and 7B. 7A and 7B are schematic diagrams illustrating another display panel 100 and its signal timing according to other embodiments of the present disclosure. In the embodiment shown in Figs. 7A and 7B, components similar to those in the embodiment shown in Fig. 1A are represented by the same component symbols, and their operations have been described in the previous paragraphs, and will not be repeated here. Compared with the embodiment shown in FIG. 1A, in other embodiments, as shown in FIG. 7A, the transistor T3 is used to receive the first light emission control signal EM1 [N]. The control terminal of the compensation transistor TC1 is used to receive the second light-emitting control signal EM2 [N].

As shown in FIG. 7B, in a corresponding embodiment, during the first period P1, the first light-emitting control signal EM1 [N] and the second light-emitting control signal EM2 [N] are at the off-voltage level. During the second period P2, the second light-emitting control signal EM2 [N] changes from the off-voltage level to the light-emitting voltage level, and the first light-emitting control signal EM1 [N] can be switched to the light-emitting display demand of the display panel 100 to Light-emitting voltage level or shutdown voltage level.

In this way, by dividing the light emission control signal into two types, during the second period P2, the compensation transistor TC1 can maintain the conduction according to the second light emission control signal EM2 [N] to output the compensation signal Vcomp [n]. And enables the transistor T2 in the driving circuit 160 to be selectively turned on or off according to the first light-emitting control signal EM1 [N] to switch the bright and dark display.

Although the disclosed methods are shown and described herein as a series Steps or events, but it should be understood that the order of the steps or events shown should not be construed as limiting. For example, some steps may occur in a different order and / or concurrently with steps or events other than those shown and / or described herein. In addition, not all steps shown herein are necessary to implement one or more aspects or embodiments described herein. In addition, one or more steps herein may also be performed in one or more separate steps and / or stages.

In summary, the present application can save the layout area by applying the architecture of the compensation circuit 120 to two or more pixels in each of the above embodiments. In addition, the data signal is written and compensated separately through the display panel 100, so that the compensation time does not affect the resolution, so the data signal write time can be shortened, which is suitable for a high-resolution display device.

Although the present disclosure has been disclosed as above by way of implementation, it is not intended to limit the present disclosure. Persons with ordinary knowledge in the technical field can make various changes and decorations without departing from the spirit and scope of the present disclosure. The scope of protection of the disclosure shall be determined by the scope of the attached patent application.

Claims (10)

A display panel includes: a capacitor, the capacitor including a first terminal and a second terminal; a compensation circuit, coupled to the first terminal of the capacitor, for using the first terminal of the capacitor according to a scanning signal Reset to a reference voltage level, and receive a system high voltage level according to a light-emitting control signal to output a compensation signal to the first end of the capacitor; a write circuit coupled to the second end of the capacitor For selectively turning on to output a data signal to the second terminal of the capacitor according to the scanning signal; and a driving circuit coupled to the second terminal of the capacitor for selectively selecting the light-emitting control signal It is turned on to output a driving current to a light-emitting element according to the voltage level of the second terminal of the capacitor. The driving circuit includes a second transistor and a third transistor, and one of the first terminals of the second transistor For receiving the high voltage level of the system, a control terminal of the second transistor is coupled to the second terminal of the capacitor, a first terminal of the third transistor is coupled to a second terminal of the second transistor End, one of the third transistors is controlled Receiving said light emission control signal, one of the third transistor is coupled to the second terminal of the light emitting element. The display panel according to claim 1, wherein the writing circuit includes a first transistor, a first terminal of the first transistor is used for receiving the data signal, and a control terminal of the first transistor is used for After receiving the scanning signal, a second terminal of the first transistor is used to output the data signal to the second terminal of the capacitor. The display panel according to claim 1, further comprising: a fourth transistor, a first terminal of the fourth transistor is used to receive the scanning signal, and a control terminal of the fourth transistor is coupled to the fourth transistor. The first terminal of the transistor and a second terminal of the fourth transistor are coupled to the light emitting element. The display panel according to claim 2, wherein the compensation circuit comprises: a first compensation transistor, a first terminal of one of the first compensation transistors is coupled to the system high voltage level, and the first compensation transistor A control terminal is used to receive the light-emitting control signal; a second compensation transistor, a first terminal of the second compensation transistor is coupled to a second terminal of the first compensation transistor, and a second compensation transistor A control terminal is coupled to a second terminal of the second compensation transistor to generate the compensation signal; and a third compensation transistor, a first terminal of the third compensation transistor is used to receive the reference voltage level. A control terminal of the third compensation transistor is used to receive the scanning signal, and a second terminal of the third compensation transistor is coupled to the second terminal of the second compensation transistor. The display panel according to claim 4, wherein the compensation circuit further includes: a fourth compensation transistor, a first terminal of the fourth compensation transistor is coupled to the second terminal of the first compensation transistor, the A control terminal of the fourth compensation transistor and a second terminal of the fourth compensation transistor are coupled to the second terminal of the second compensation transistor. The display panel according to claim 4, wherein in a first period, the scanning signal makes the third compensation transistor and the second transistor conductive at a low voltage level, and in a second period, the scanning signal At a high voltage level, the third compensation transistor and the second transistor are turned off. The display panel according to claim 6, wherein when the light-emitting control signal is at a turn-off voltage level, the first compensation transistor, the second compensation transistor, and the third transistor are turned off. The signal is at a light-emitting voltage level, the first compensation transistor, the second compensation transistor, and the third transistor are turned on, and the light-emitting control signal is located at the turn-off voltage level for a length of time greater than the first period. The display panel according to claim 6, wherein the control terminal of the third transistor is used to receive a first light-emitting control signal, and the control terminal of the first compensation transistor is used to receive a second light-emitting control signal, The length of time that the first light-emitting control signal and the second light-emitting control signal are at the off-voltage level is greater than the first period, and during the second period, the first light-emitting control signal is at the light-emitting voltage level or the off Off voltage level. The display panel according to claim 1, wherein the display panel includes a plurality of pixels. During a writing period, the light-emitting control signal is at a turn-off voltage level, and the plurality of scanning signals of the pixels are sequentially turned on. During a light emitting period, the light emitting control signal is at a light emitting voltage level, and the scanning signals of the pixels are turned off. The display panel according to claim 1, wherein the display panel includes a plurality of pixels, and the first ends of the capacitors of two or more of the pixels are coupled to each other to receive the same Compensation signal.