TWI670226B - Multi-trench semiconductor devices - Google Patents

Abstract

A MOSFET device or a rectifier device having improved R _DSON and BV performance has a repeating pattern of field plate trenches disposed in a semiconductor wafer. The semiconductor wafer includes a doped epitaxial layer wherein the dopant concentration gradually decreases from the top of the wafer surface toward the bottom of the wafer. The doped epitaxial layer can comprise a layer of epitaxial layers having different dopant concentrations and the field plate trenches each terminate at a predetermined point in the hierarchy.

Description

Multi-trench semiconductor device

The performance of a power semiconductor device is generally defined by a number of parameters and the performance of the trench (vertical) device is also specifically defined by a number of parameters. Among these parameters, the on-resistance R _DSON and the breakdown voltage BV seem to cancel each other out: one improvement often comes at the expense of the other. For example, when the dopant concentration in the current path increases (which leads to an improvement in the on-resistance R _DSON ), the breakdown voltage BV drops, which is disadvantageous for device performance. Several approaches have been proposed to advance the balance between on-resistance and breakdown voltage.

Texas Instruments (TI) has proposed a method in US 2010/0264486 A1 and this method is later recorded by Toshiba (Kobayashi et al., 27th International Power Semiconductor Device and IC Conference) , 2015) Argument. The method proposes varying the thickness of the oxide of the field plate in the trench. Specifically, the oxide of the field plate structure is gradually thicker from the top end of the trench toward the bottom of the trench in different steps. There is a five-year leap between the TI publication and the Toshiba argument.

Another approach proposed by Maxpower (US 8,354,711 B2) is to divide the field plate structure into a plurality of isolated portions, each of which has an independent field plate that is biasable independently of the other portions of each trench.

The inventors have recognized that while the theory behind the proposed method seems reasonable, there are significant manufacturing challenges that would make such devices difficult to mass produce. For example, in the TI process, there are at least two transition points in the field plate trench: dividing the field plate structure into multiple parts The fractions, and portions, each have a narrowly defined length and oxide thickness. Controlling multiple etch processes and controlling different oxide thicknesses is critical and challenging.

The Power Proposal requires that a plurality of field plates in the trench be isolated from one another and the field plates separated by a thin layer of ruthenium dioxide film. To be effective, it is necessary to electrically bias a plurality of field plates individually. The bias voltage must add complexity to the design and operation of the device. In addition, the device depends on the precise placement of the oxide film in the trench relative to the doped layer and this adds difficulty to device fabrication.

The inventors have also recognized that certain processes can be more easily controlled in modern semiconductor process technology. It is an epitaxial layer growth, trench etching, and oxide film formation on the surface of the crystalline germanium. By utilizing an easier control process, the inventors have invented a novel method that can be readily adapted to fabricate devices such as power MOSFETs and power rectifiers.

The novel process is based on placing a field plate trench having a predefined depth into the hierarchy of a semiconductor epitaxial layer having a specific resistivity. In its simplest implementation, field plate trenches having two alternating different depths are placed in a repeating pattern. The depth of the shallower trench is approximately equal to the thickness of the first epitaxial layer, and the depth of the deeper trench is less than the accumulated thickness of the first epitaxial layer and the second epitaxial layer immediately below the first epitaxial layer. In other words, the shallower trenches traverse the first epitaxial layer and the deeper trenches completely penetrate the first epitaxial layer and partially penetrate the second epitaxial layer. The first and second epitaxial layers have different dopant concentrations--the first epitaxial layer is more heavily doped than the second epitaxial layer. The main dopants in the two epitaxial layers have the same polarity.

The field plate trenches are configured to approximate p-n junctions designed to maintain high reverse bias and depletion regions associated with p-n junctions in the epitaxial layer. One such configuration is a trench having a doped polysilicon core electrically insulated from the trench walls by a hafnium oxide layer. In the case where the polycrystalline germanium core is suitably biased with respect to the p-n junction, the peak electric field that tends to reach the site of collapse early will decrease, so the p-n junction can maintain a higher reverse bias voltage across it.

The inventive concept can be easily extended to three or more trenches and three or more epitaxial layer levels after the two trench configurations. The illustrative implementations in the following sections will be used to more fully explain this inventive concept.

It can be said that those skilled in the art of semiconductor processing can read the present invention and understand the stability of the process in which the present invention can be implemented and thus understand the predictable good device performance. This is because the implementation of the present invention does not depend on the difficulty of controlling the steps as set forth in the known art and the implementation stability of the embodiments described below will be apparent.

definition

The terms used in the present invention generally have the ordinary meanings of the art within the scope of the present invention. Certain terms are discussed below to provide additional guidance to practitioners considering the specification of the present invention. It will be understood that the same thing can be described in more than one way. Therefore, alternative languages and synonyms can be used.

Semiconductor wafers are thick blocks of semiconductive materials such as tantalum, niobium, tantalum carbide, diamond, gallium arsenide, and gallium nitride. Semiconductor wafers typically have two parallel surface planes that are primarily crystalline planes. The integrated circuit is built into the semiconductor wafer and on the top surface; more recently, some of the integrated circuit components have been built into the bulk of the semiconductor wafer perpendicular to the top surface. In the present invention, the term top surface or wafer surface of a wafer is used to mean the top parallel surface of a semiconductor wafer in which the semiconductor material contacts other materials such as dielectric or conductive materials.

Trench is a structural component in some integrated circuit wafers. The trenches are typically formed from a patterned image in a photoresist film on the surface of a semiconductor wafer, followed by removal of material from the wafer where no photoresist is present. Material removal is typically accomplished using a reactive ion etching process. The trench typically has a long stripe repeating pattern when viewed from the surface of the wafer. The walls of the trench are the vertical surfaces of the semiconductor material that extend from the surface of the wafer to the bottom of the trench. In the present invention, the width of the groove is the distance between the two opposing groove walls and the length of the groove is a long dimension orthogonal to the width and depth of the groove. The depth of the trench is measured in a direction perpendicular to the top surface of the wafer and is a measure from the top surface of the wafer to the end of the etching step (ie, the bottom of the trench).

The MOSFET is a four-terminal electronic circuit component. Current can flow in the channel between the source and drain terminals, and the magnitude of the current can be controlled by the voltage at the gate terminal and the body region. In a MOSFET, current can flow in both directions of the channel. In many trench MOSFETs, the gate is built into the trench and the body region is internally shorted to the source region.

The rectifier is a two-terminal circuit component. Depending on the polarity of the voltage across the terminals, current may or may not flow between the anode and the cathode. In SBR rectifiers made by diode incorporation, there is also a gate structure. The SBR rectifier can also be built vertically with the trench in which the gate or field plate or both are placed.

The epitaxial layer (epi-layer) refers to a single crystal semiconductor layer formed on a substrate of, for example, another single crystal semiconductor layer by epitaxial growth in the present invention. The substrate can be heavily doped to reduce device resistance. The dopant can be incorporated into the epitaxial layer by ion implantation during its formation or after its formation. Integrated circuit components are typically built into the epitaxial layer. In the present invention, a semiconductor wafer comprises an epitaxial layer hierarchy having different dopant concentrations. When the epitaxial layer is initially formed, the difference in dopant concentration between the two adjacent epitaxial layers can be as little as 5%. During the fabrication of the device, the high temperature process can cause dopant diffusion in the epitaxial layer, so that at the completion of the fabrication process, the interface between adjacent epitaxial layers can lose its sharpness and become an interface region where the dopant concentration changes stepwise. Or district . The region may occupy up to 30% of the thickness of the epitaxial layer under some conditions.

The source and drain in the MOSFET refer to the source and drain terminals or two regions in the semiconductor wafer connected to the respective terminals. In a vertical MOSFET, the drain can have a configuration called a lower source at the top of the wafer surface or a configuration called a lower drain at the bottom of the wafer.

The forward voltage (V _F ) of a MOSFET or rectifier is a measure of the voltage at a device when a certain amount of current flows through the device. It is a figure of merit in power devices because it represents the power loss (IV _F ) due to ohmic heating when driving forward.

The on-resistance (R _DSON ) of the MOSFET or rectifier is the current measurement of the device that is driving forward at a set voltage. It is the figure of merit in power devices because it represents the power loss due to ohmic heating.

The blocking voltage (BV) of a MOSFET or rectifier is the maximum voltage measurement across the reverse bias junction of the device before the device enters a "crash" mode. It is the figure of merit in power devices because it represents the maximum operating voltage of the device.

The field plate in the power MOSFET or rectifier is a conductive element placed close to the pn junction and when properly biased, it can effectively alter the electric field distribution near the pn junction to increase its breakdown voltage. The field plate can be a polycrystalline structure at the surface of the device or inside the trench of the field plate. The field plate trench in the vertical MOSFET or rectifier has a conductive element such as a doped polysilicon disposed inside the trench and shielded by a layer of dielectric material from the MOSFET channel. It is configured to increase the breakdown voltage between the body region and the substrate.

100‧‧‧ partially completed device

110‧‧‧Field plate trench

112‧‧‧lower part/field plate electrode

114‧‧‧Upper part/gate electrode

116‧‧‧Dielectric layer

118‧‧‧ gate oxide layer

120‧‧‧Other field plate trenches

122‧‧‧lower part/field plate electrode

124‧‧‧Upper part/gate electrode

126‧‧‧ dielectric layer

128‧‧‧ gate oxide layer

130‧‧‧ epitaxial layer

140‧‧‧ epitaxial layer

141‧‧‧ wafer surface

170‧‧‧ dielectric material layer

180‧‧‧metal layer

200‧‧‧ another device

210‧‧‧Field plate trench

220‧‧‧Field plate trench

230‧‧‧ epitaxial layer

240‧‧‧Elevation layer

241‧‧‧ wafer surface

300‧‧‧ another device

310‧‧‧Field plate trench

312‧‧‧ Field plate electrode

314‧‧‧gate electrode

318‧‧‧gate dielectric

320‧‧‧Field plate trench

322‧‧‧Field plate electrode

330‧‧‧ epitaxial layer

340‧‧‧ epitaxial layer

380‧‧‧Metal components

390‧‧ ‧ gate trench

400‧‧‧ another device

410‧‧‧Field plate trench

414‧‧‧gate electrode

418‧‧‧gate oxide

420‧‧‧Field plate trench

430‧‧‧ epitaxial layer

440‧‧‧ epitaxial layer

441‧‧‧ wafer surface

500‧‧‧ another device

510‧‧‧Field plate trench

520‧‧‧Field plate trench

530‧‧‧Elevation layer

540‧‧‧ epitaxial layer

541‧‧‧ wafer surface

600‧‧‧Another device

610‧‧‧Field plate trench

620‧‧‧Field plate trench

630‧‧‧ epitaxial layer

640‧‧‧ epitaxial layer

641‧‧‧ wafer surface

700‧‧‧trench mask

710‧‧‧Field plate trenches/stripe

720‧‧‧Field plate trenches/stripe

5110‧‧‧Field plate trench

5440‧‧‧ epitaxial layer

6110‧‧‧Field plate trench

6440‧‧‧ epitaxial layer

1 depicts a cross-sectional view of a partially completed device embodying certain aspects of the present invention.

2 depicts a cross-sectional view of a partially completed device embodying certain aspects of the present invention.

3 and 3A depict cross-sectional views of a partially completed device embodying certain aspects of the present invention.

4 and 4A depict cross-sectional views of a partially completed device embodying certain aspects of the present invention.

Figure 5 depicts a cross-sectional view of a partially completed device embodying certain aspects of the present invention.

Figure 6 depicts a cross-sectional view of a partially completed device embodying certain aspects of the present invention.

Figure 7 depicts a portion of a trench mask that includes a repeating pattern of two trenches.

Example 1

1 depicts a schematic cross-sectional view of a partially completed device 100 embodying aspects of the present invention. The device can be a power MOSFET or a power rectifier and is built into a germanium wafer comprising two epitaxial layers 130 and 140 . The two epitaxial layers are mainly doped with an n-type dopant and the epitaxial layer 140 is more heavily doped than the epitaxial layer 130 . In the middle of FIG. 1 is a field plate trench 110 and two other field plate trenches 120 that are laterally coupled to the field trench 110 . The trenches 110 and 120 are etched downward from the wafer surface 141 . The bottom of the trench 110 is at the interface region of the two epitaxial layers 140 and 130 . The trench 120 is deeper etched than the trench 110 and its bottom penetrates into the epitaxial layer 130 , passing through the interfacial layer 130 and the interfacial region of the epitaxial layer above it.

In each of the plate trenches depicted in Figure 1, there are two portions of polycrystalline germanium material. In the trench 110 , the lower portion 112 is a field plate electrode and the upper portion 114 is a gate electrode. The two portions are insulated from each other by a dielectric layer (which in this example contains cerium oxide). Other dielectric materials such as bismuth oxynitride may also be used.

Field plate electrode 112 by a dielectric layer 116 and the epitaxial layer 140 and spaced apart from the gate electrode 114 and the gate oxide layer 118 epitaxial layer 140 spaced apart. In this example, the gate oxide layer comprises hafnium oxide. Other dielectric materials such as bismuth oxynitride and other metal oxides may also be used. The epitaxial layer 140 adjacent to the gate oxide 118 may be relatively doped with a p-type dopant such as boron. This area is referred to in the art as the body region of a MOSFET or rectifier. Dielectric layer 116 is thicker than gate oxide 118 as depicted in FIG.

The side field plate trenches 110 are two field plate trenches 120 that are deeper than the field plate trenches 110 . In the trench 120 , the lower portion 122 of the polysilicon material is the field plate electrode and the upper portion 124 is the gate electrode. The two portions are also insulated from each other by a dielectric layer (which in this example contains cerium oxide). Other dielectric materials such as bismuth oxynitride may also be used.

The field plate electrode 122 by a dielectric layer 126 and the epitaxial layer 140 and spaced apart gate electrode 124 and the epitaxial layer 140 is spaced apart from the gate oxide layer 128. In this example, the gate oxide layer comprises hafnium oxide. Other dielectric materials such as bismuth oxynitride and other metal oxides may also be used. The epitaxial layer 140 adjacent to the gate oxide 118 may be relatively doped with a p-type dopant such as boron. This area is referred to in the art as the body region of a MOSFET or rectifier. Dielectric layer 126 is thicker than gate oxide 128 as depicted in FIG. The thickness of the dielectric layer 126 is similar to the thickness of the dielectric layer 116 , and the thickness of the gate oxide layer 128 is similar to the thickness of the gate oxide layer 118 .

On the gate electrodes 114 and 124 is a layer of dielectric material 170 (which in this example is hafnium oxide). Other dielectric materials such as tantalum nitride and niobium oxynitride and other metal oxides may also be used. The dielectric material layer 170 insulates the gate electrodes 114 and 124 from the metal layer 180 that contacts the epitaxial layer 140 and the body region adjacent the wafer surface 141 .

Metal layer 180 may comprise a metal such as aluminum, copper, titanium, platinum, or a combination of metals. Depending on the concentration and the dopant metal and epitaxial layer 140 at the contact, the metal 180 at the interface with the epitaxial layer 140 may be formed Schottky diode, tunnel diode, or an ohmic contact.

If the epitaxial layer near the gate electrodes 114 and 124 at the top of the body region is relatively doped with an n-type dopant such as phosphorus and arsenic to form the source region, the device 100 is a MOSFET. If the source region is not present, device 100 can be a rectifier.

Example 2

FIG. 2 depicts a schematic cross section of another apparatus 200 that also embodys aspects of the present invention. Device 200 can be a MOSFET or a rectifier.

Device 200 includes a repeating pattern of field plate trenches 210 and 220 that are both etched from wafer surface 241 into the semiconductor wafer. When the bottom reaches the interface region of the epitaxial layers 230 and 240 , the etching of the field plate trench 210 is stopped. Field plate trenches 220 are etched deeper than trenches 210 . Embodiment, the etching is continued and then stopped at the bottom penetrates into the epitaxial layer 230 through epitaxial layer 230 and the interface region of epitaxial layer 230 over the epitaxial layer 240 in this embodiment. In this aspect, device 200 is similar to device 100 described in the previous paragraph.

Device 200 differs from device 100 in that two shallow field plate trenches 210 are disposed adjacent one another in device 200 , and in device 100 , both sides of each shallow field plate are flanked by deeper field plate trenches 120 .

Example 3

3 and 3A depict schematic cross sections of another device 300 that also embodys aspects of the present invention. Device 300 can be a MOSFET or a rectifier.

In device 300 , the gate electrode and field plate electrodes are not disposed in the common trenches of devices 100 and 200 , but are disposed in the separation trenches.

The repeating pattern of the field plate trenches of device 300 is similar to the pattern depicted in FIG. The field plate trench 310 corresponds to the field plate trench 110 of FIG. 1 and the field plate trench 320 corresponds to the field plate trench 120 . However, gate electrode 314 is disposed in gate trench 390 between adjacent field plate trenches 310 and 320 . Gate electrode 314 is separated from epitaxial layer 340 by gate dielectric 318 . Field plate electrode 322 contacts metal element 380 , which in this example also contacts epitaxial layer 340 near the top surface of the wafer. If it is desired to bias the field plate electrodes 322 and 312 at a potential different from the source potential, the electrodes will be electrically insulated from each other.

Similar to devices 100 and 200 , the bottom of field plate trench 310 is near the boundary of two epitaxial layers 340 and 330 , and the deeper plate trench passes through the transition region between two adjacent epitaxial layers.

Example 4

4 and 4A depict schematic cross sections of another device 400 that also embodys aspects of the present invention. Device 400 can be a MOSFET or a rectifier.

Device 400 is similar to device 300 depicted in FIG. The two devices differ in the structure of the gate. Although the gate electrode in device 300 is disposed in gate trench 390 , the gate structure in device 400 is on wafer surface 441 . Gate oxide gate electrode 418 disposed under the upper surface 414 of the wafer 441, and the gate electrode 414 so that the separated epitaxial layer 440 and 430. Each side of each gate structure is connected to field plate trenches 410 and 420 . The structure of the field plate trench of device 400 is similar to the structure of the field plate trench of device 300 .

Example 5

FIG. 5 depicts a schematic cross section of another apparatus 500 that also embodys aspects of the present invention. Device 500 can be a MOSFET or a rectifier.

Device 500 is built into a semiconductor wafer containing three epitaxial layers having different dopant concentrations. The epitaxial layer 5440 is more heavily doped than the epitaxial layer 530 but is lightly doped than the epitaxial layer 540. The epitaxial layer 540 is closest to the wafer surface 541 compared to the epitaxial layers 5440 and 530 .

Device 500 includes a repeating pattern of field plate trenches 510 , 520, and 5110 , all of which are etched from wafer surface 541 into the semiconductor wafer. When the bottom reaches the interface region of the epitaxial layers 540 and 5440 , the etching of the field plate trench 510 is stopped. Field plate trench 5110 is etched deeper than trench 510 and its bottom reaches the interface region of epitaxial layers 5440 and 530 . Field plate trench 520 is etched deeper than trench 5110 . After stopping this embodiment, the field plate grooves 530 continue through the interface region of the epitaxial layer above the epitaxial layer 5440 and epitaxial layer 530, and at the bottom penetrates into epitaxial layer 530 in this embodiment.

In the repeating pattern of the field plate trenches of the exemplary device 500 , each of the field plate trenches 5110 is flanked by two shallower field plate trenches 510 and two deeper field plate trenches. The 520 is disposed on the other side of each of the field plate trenches 510 remote from the field plate trench 5110 .

Example 6

FIG. 6 depicts a schematic cross section of another apparatus 600 that also embodys aspects of the present invention. Device 600 can be a MOSFET or a rectifier.

Similar to device 500 , device 600 is built into a semiconductor wafer containing three epitaxial layers having different dopant concentrations. The epitaxial layer 6440 is more heavily doped than the epitaxial layer 630 but is lightly doped than the epitaxial layer 640. The epitaxial layer 640 is closer to the wafer surface 641 than the epitaxial layers 6440 and 630 .

Device 600 includes a repeating pattern of field plate trenches 610 , 620, and 6110 , all of which are etched from wafer surface 641 into the semiconductor wafer. When the bottom reaches the interface region of the epitaxial layers 640 and 6440 , the etching of the field plate trench 610 is stopped. The field plate trenches 6110 are deeper etched than the trenches 610 and the bottoms reach the interfacial regions of the epitaxial layers 6440 and 630 . Field plate trench 620 is etched deeper than trench 6110 . After stopping this embodiment, the field plate grooves 630 continue through the interface region of the epitaxial layer over the epitaxial layer 630 and the epitaxial layer, and at the bottom penetrates into epitaxial layer 630 in this embodiment.

In the repeating pattern of the field plate trenches of this exemplary device 600 , each of the other field plate trenches has its bottom portion at a transition region of two epitaxial layers having the same dopant polarity and having different dopant concentrations. Line field plate trenches.

Example 7

FIG. 7 depicts a schematic representation of a portion of a trench mask 700 that includes a repeating pattern of two field plate trenches 710 and 720 . This mask can be used to fabricate MOSFETs or rectifiers as depicted in Figures 1 through 6. For example, strip 710 can correspond to trench 110 and strip 720 can correspond to trench 120 . Depending on the particular design, strips 710 and 720 may or may not have equal widths.

Claims (16)

A semiconductor device comprising: a semiconductor wafer comprising: a top surface; two adjacent epitaxial layers, a first epitaxial layer having a first thickness and doped with a first dopant to a specific first concentration a second epitaxial layer having a second thickness and doped the first dopant to a specific second concentration, which is different from the specific first concentration; an interface region located in the first epitaxial layer And the second epitaxial layer, and wherein the dopant concentration transitions from the first concentration to the second concentration; a first field plate trench having a bottom having a smaller depth at one of the interface regions; a second field plate trench having a greater depth penetrating the interface region and greater than one of the first field plate trenches. The device of claim 1, further comprising a repeating pattern of a gate structure of a MOSFET device or a rectifier device. The device of claim 2, wherein each of the gate structures comprises a gate electrode disposed within a trench. The device of claim 3, wherein the gate electrode is disposed within a trench of a field. The device of claim 4, further comprising a field plate electrode in each of the plate trenches. The device of claim 5, wherein the gate electrode and the field plate electrode in each of the plate trenches comprise doped polysilicon, and the gate electrode and the field plate electrode are separated by a dielectric film. The device of claim 1, further comprising one of the adjacent epitaxial layers Touch one of the metal components. The device of claim 7, wherein the contact of the metal to the epitaxial layer forms a device selected from the group consisting of a Schottky diode, a tunneling diode, and an ohmic contact. A semiconductor wafer comprising: two adjacent epitaxial layers, a first epitaxial layer having a first thickness and a first specific resistivity, a second epitaxial layer having a second thickness and a second specific resistivity Corresponding to the first specific resistivity; an interface region between the first epitaxial layer and the second epitaxial layer, and wherein the dopant concentration transitions from the first dopant concentration to the first a second dopant concentration; a first field plate trench having a bottom at a depth of the interface region; and a second deeper field plate trench penetrating the interface region. The device of claim 9, further comprising a repeating pattern of a rectifier device or a gate structure of a MOSFET device. The device of claim 10, wherein each of the gate structures comprises a gate electrode disposed within a trench of a field. The device of claim 11 further comprising a field plate electrode in each of the field plate trenches. The device of claim 12, wherein the gate electrode and the field plate electrode in each of the plate trenches comprise doped polysilicon, and the gate electrode and the field plate electrode are separated by a dielectric film. The device of claim 10, wherein a gate structure is disposed between the two field plate trenches. The device of claim 14, wherein the gate structure is disposed adjacent a surface of the wafer. The device of claim 15 wherein the gate structure is disposed within a trench of a field.