TWI667741B - Three dimensional memory device and method for fabricating the same - Google Patents

Abstract

A memory component includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer, and a channel layer. The insulating layer and the conductive layer are alternately stacked on the substrate to form a multilayer stacked structure, wherein the multilayer stacked structure has at least one trench passing through the conductive layer and the insulating layer. The memory layer covers the multilayer stack structure and extends at least to the sidewalls of the trench. The channel layer covers the memory layer, wherein the channel layer includes an upper portion, a tandem portion, and a lower portion. The upper portion abuts the opening of the trench; the lower portion is located at the bottom of the trench; the tandem portion is located above the sidewall for connecting the upper portion and the lower portion, and has an ion doping concentration substantially smaller than the upper portion and the lower portion.

Description

Stereo memory element and manufacturing method thereof

The present disclosure relates to a non-volatile memory element and a method of fabricating the same. In particular, there is a three-dimensional (3D) non-volatile memory element and a method of fabricating the same.

Non-Volatile Memory (NVM) components, such as flash memory, have the property of not losing information stored in the memory unit when the power is removed. It has been widely used in solid-state mass storage applications for portable music players, mobile phones, digital cameras, and the like. Three-dimensional non-volatile memory components, such as vertical-channel (VC) stereo NAND flash memory components, have many layer stack structures for higher storage capacity and superior electronic characteristics, such as Good data retention reliability and speed of operation.

A typical vertical channel type stereoscopic non-volatile memory element includes a plurality of multi-layer stacks in which an insulating layer and a conductive layer which are parallel to each other are alternately stacked. The multi-layer stack structure includes at least one trench, and the multi-layer structure is divided into a plurality of ridge-shaped stacks to make each ridge The multilayer laminate has a plurality of conductive strips formed from patterned conductive layers. The three-dimensional non-volatile memory component also includes a memory layer and a channel layer. Wherein, the memory layer is located on the sidewall of the trench; the channel layer covers the ridge multilayer stack and the memory layer, and a plurality of memory cells are defined at a position where each of the conductive strips overlaps the memory layer and the channel layer. . The vertically aligned memory cells are formed by vertically connecting the channel layers in series to form a memory cell string and electrically connected to the corresponding bit line through the metal contact structure located in the multi-layer structure.

However, as the number of insulating layers and conductive layers in the multilayer structure increases, the number of memory cells in the memory cell series also increases. Not only the current input to the memory string via the bit line must be increased during operation, but also the size of the bottom of the trench is reduced by the etching step of forming the trench, and the width of the channel layer at the bottom of the trench is reduced. The resistance of the component channel and the bit line is high, which seriously affects the operation quality and reliability of the vertical channel type stereoscopic non-volatile memory component.

Therefore, there is a need to provide a more advanced three-dimensional memory component and a method of fabricating the same to improve the problems faced by conventional techniques.

According to an embodiment of the present specification, a stereo memory device is provided that includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer, and a channel layer. The insulating layer and the conductive layer are alternately stacked on the substrate to form a multi-layer stack, wherein the multilayer stack structure has at least one trench, which is worn These conductive layers and insulating layers pass through. The memory layer covers the multilayer stack structure and extends over at least one sidewall of the trench. The channel layer covers the memory layer, wherein the channel layer includes an upper portion, a tandem portion, and a lower portion. The upper portion abuts the opening of the trench; the lower portion abuts the bottom of the trench; the tandem portion is located above the sidewall of the trench for connecting the upper portion and the lower portion, and has an ion doping concentration substantially smaller than the upper portion and the lower portion.

According to another embodiment of the present specification, a method of fabricating a stereo memory device is provided, comprising the steps of: firstly providing a multi-layer stack structure on a substrate, the multi-layer stack structure comprising a plurality of insulating layers and a plurality of staggered stacks Conductive layers. The multilayer stack structure is then patterned, whereby at least one trench is formed in the multilayer stack structure, passing through the conductive layer and the insulating layer. A memory layer is formed covering the multilayer stack structure and extending over at least one sidewall of the trench. Subsequently, a channel layer is formed to cover the memory layer. Before filling the trench with a dielectric material, an ion doping process is performed on the channel layer, a plurality of ion dopants are implanted into the channel layer, and the channel layer is at least divided into an upper portion, a tandem portion and a lower portion. unit. Wherein the upper portion abuts the opening of the trench; the lower portion abuts the bottom of the trench; the tandem portion is located above the sidewall of the trench for connecting the upper portion and the lower portion; and the tandem portion has substantially smaller portions than the upper portion and the lower portion Ion doping concentration.

According to the above embodiment, the present invention provides a three-dimensional memory element and a method of fabricating the same. The method of fabricating the three-dimensional memory element provides a patterned multilayer stack structure on a substrate, and sequentially forms a memory layer and a channel layer on at least one trench sidewall of the multilayer stack structure. Before the trench is filled with the dielectric material, an ion doping process is performed on the channel layer to mix the plurality of ions Implanting the channel layer such that the first string portion of the channel layer on the sidewall of the trench has an ion doping concentration substantially smaller than the channel layer adjacent to the upper portion of the trench opening and the lower portion of the trench bottom portion Doping concentration.

Since the doping process can have charged ion dopants in the upper and lower portions of the channel layer at the bottom of the trench, the resistance of the channel layer can be effectively reduced, and the three-dimensional memory device can be improved because of the insulating layer and the conductive layer in the multilayer structure. The increase in the number of layers causes a partial contraction of the width of the channel, causing a problem that the channel resistance is rapidly increased.

100, 200‧‧‧ stereo memory components

101, 201‧‧‧ substrate

101a‧‧‧Dielectric isolation layer

104, 204‧‧‧ trench

104a, 204a‧‧‧ trench sidewall

104b, 204b‧‧‧ trench opening

104c, 204c‧‧‧ trench bottom

109, 209‧‧‧ channel layer

109a, 209a‧‧‧ upper part

109c, 209c‧‧‧ series

109b, 209c‧‧‧ lower part

110‧‧‧Multilayer stacking structure

111-115‧‧‧ Conductive layer

111a‧‧‧Top surface of the conductive layer

120‧‧‧Protective layer

128, 228‧‧‧ dielectric layer

129A-129E, 229A-229F‧‧‧ contact plug

109a1-109a5, 209a1-209a6‧‧‧ solder pads

110a, 110b, 110c, 210a, 210b, 210c‧‧‧ ridge multilayer laminate

121-125‧‧‧Insulation

130, 230‧‧‧ ion doping process

131, 1231‧‧‧ memory cells

132, 133, 232‧‧‧ memory cell series

134, 135, 136, 137, 234, 235‧‧‧ transistors

201a‧‧‧Polysilicon layer

106, 206‧‧‧ memory layer

219a, 219b‧‧‧ channel membrane

The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood. A cross-sectional view of a series of process structures for a three-dimensional memory device according to an embodiment of the present invention; and FIGS. 2A to 2G are diagrams of a three-dimensional memory device according to another embodiment of the present invention. A schematic diagram of a series of process structures.

The invention provides a stereo memory component and a manufacturing method thereof, which can Improvement of the three-dimensional memory element due to an increase in the number of insulating layers and conductive layers in the multi-layered structure causes the channel width to be tightened, and the resulting channel resistance is rapidly increased. The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.

However, it must be noted that these specific embodiments and methods are not intended to limit the invention. The invention may be practiced with other features, elements, methods and parameters. The preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the invention. Equivalent modifications and variations will be made without departing from the spirit and scope of the invention. In the different embodiments and the drawings, the same elements will be denoted by the same reference numerals.

Please refer to FIG. 1A to FIG. 1F. FIG. 1A to FIG. 1F are schematic cross-sectional views showing a series of process structures of the three-dimensional memory device 100 according to an embodiment of the invention. The method of fabricating the stereoscopic memory element 100 includes the steps of first providing a substrate 101 and forming a multilayer stack structure 110 on the substrate 101 (as depicted in FIG. 1A). In some embodiments of the present invention, the substrate 101 may include a dielectric isolation layer 101a formed on the dielectric isolation layer 101a and in contact with the dielectric isolation layer 101a.

The multilayer stack structure 110 includes a plurality of conductive layers 111-115 and a plurality of insulating layers 121-125. The insulating layers 121-125 and the conductive layers 111-115 are staggered on the substrate 101 along the Z-axis direction depicted in FIG. 1A. And parallel to each other. In the present embodiment, the conductive layer 111 is located at the bottommost layer of the multilayer stack structure 110, and the insulating layer 125 is located at the top layer of the multilayer stack structure 110.

The conductive layers 111-115 may be composed of a metal such as gold, copper, aluminum, an alloy material, a metal oxide or other suitable metal material. Furthermore, the conductive layers 111-115 may also be composed of an undoped polycrystalline or single crystal semiconductor material, such as polycrystalline or single crystal germanium/iridium. Alternatively, it may be composed of a doped semiconductor material such as an n-type polycrystalline germanium doped with phosphorus (Porus) or arsenic (As) or a p-type polycrystalline germanium doped with boron (boron, B). In the present embodiment, the conductive layers 111-115 are composed of undoped polysilicon. The insulating layers 121-125 may be composed of a dielectric material such as an oxide, a nitride, an oxynitride, a silicate or the like.

In some embodiments of the present invention, the conductive layers 111-115 and the insulating layers 121-125 may be fabricated by, for example, a Low Pressure Chemical Vapor Deposition (LPCVD) process. The thickness of the insulating layers 121-125 may be substantially between 30 angstroms (Åstroms) and 800 angstroms. The conductive layer 111 at the bottommost layer and the conductive layer 115 at the uppermost layer have a thickness thicker than the other conductive layers 112-114. The thickness of the conductive layers 112-114 may be substantially between 30 angstroms and 800 angstroms. The thickness of the conductive layers 111 and 115 may be substantially between 50 angstroms and 3000 angstroms. However, in other embodiments, the thickness of the insulating layer and the conductive layer are not limited thereto.

Next, the multi-layer stack structure 110 is patterned to form a plurality of ridge-like multilayer stacks 110a, 110b, and 110c (as shown in FIG. 1B). In some embodiments of the invention, the patterning process 103 of the multilayer stack structure 110 includes forming a hard mask layer 102 on the multilayer stack structure 110 and patterning the hard mask layer 102. Then, the patterned hard mask layer 102 is used as an etching mask, and a part of the multilayer stack structure is removed by an anisotropic etching process, such as a reactive ion etching (RIE) process. 110, by forming a trench 104 extending along the Z-axis direction among the multilayer stacked structures 110, dividing the multilayer stacked structure 110 into a plurality of ridge-shaped multilayer stacks extending along the Y-axis (vertical X-axis) direction, for example The ridge multilayer laminates 110a, 110b, and 110c expose a portion of the dielectric isolation layer 101a in the substrate 101 to the outside via the trenches 104. The hard mask layer 102 may be a tantalum nitride layer formed on the topmost insulating layer 125 of the multilayer stack structure 110.

A memory layer 106 is then formed over the multilayer stack structure 110 to cover the top of the ridge multilayer stacks 110a, 110b, and 110c and extend into the bottom portion 104c of the trench 104 (i.e., a portion of the dielectric exposed by the trenches 104) The isolation layer 101a) and the trench sidewalls 104a. Conformal deposition is then performed on the ridge multilayer laminates 110a, 110b, and 110c to form a channel layer 109 overlying the memory layer 106 (as depicted in FIG. 1C).

In some embodiments of the invention, the memory layer 106 comprises at least a composite layer of a silicon oxide layer, a silicon nitride layer, and a hafnium oxide layer (ie, an ONO structure). However, the structure of the memory layer 106 is not limited thereto. In still other embodiments of the present specification, the composite layer of the memory layer 106 may also be selected from the group consisting of a tantalum oxide-cerium nitride-cerium oxide-cerium nitride-cerium oxide. (oxide-nitride-oxide-nitride-oxide, ONONO) structure, silicon-oxide-nitride-oxide-silicon (SONOS) structure, energy gap engineering Band-gap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS) structure, niobium nitride-alumina-tantalum nitride-rhenium oxide- Tantalum nitride (aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS) structure and a metal high dielectric constant energy gap engineering 矽-矽 oxide-tantalum nitride-矽 oxide-矽 (metal-high-k Bandgap-engineered silicon-oxide-nitride-oxide-silicon, MA BE-SONOS) is a group of structures. In this embodiment, the memory layer 106 may be an ONO composite layer fabricated by a low pressure chemical vapor deposition process, and has a thickness substantially between 60 angstroms and 600 angstroms.

The material constituting the channel layer 109 may include a semiconductor material such as an n-type polycrystalline germanium doped with phosphorus or arsenic (or an n-type epitaxial single crystal germanium), and a p-type polycrystalline germanium doped with boron (or a p-type epitaxial single crystal germanium). , undoped polysilicon, metal silicides such as titanium telluride (TiSi), cobalt (CoSi) or germanium (SiGe), oxide semiconductors, such as indium zinc oxide (InZnO) or Indium gallium zinc oxide (InGaZnO) or a combination of two or more of the above materials. In the present embodiment, the channel layer 109 is formed as an undoped polysilicon layer, and its thickness is substantially between 30 angstroms and 500 angstroms.

Thereafter, the channel layer 109 is subjected to an ion doping process 130, a plurality of ion dopants are implanted into the channel layer 109, and the channel layer is at least separated into one. An upper portion 109a, a tandem portion 109c and a lower portion 109b (as shown in FIG. 1D). Due to the characteristics of the etching process, the formed trenches 104 have an upper and lower narrow outline, so that most of the doping ions in the ion doping process 130 have a chance to be implanted into the channel layer 109 adjacent to the trench. The upper portion 109a of the opening 104b of the groove 104 and the lower portion 109b of the bottom portion 104c of the groove 104 are less capable of being doped with the tandem portion 109c for connecting the upper portion 109a and the lower portion 109b on the side wall 104a of the groove 104. Therefore, the ion doping concentration in the tandem portion 109c of the channel layer 109 has substantially smaller ion doping concentration than the upper portion 109a and the lower portion 109b. In some embodiments of the present specification, the lower portion 109b may extend upward from the trench bottom portion 104c, but does not substantially exceed the top surface 111a of the bottommost conductive layer 111 of the multilayer stack structure 110.

In some embodiments of the present specification, a protective layer 120 may be selectively formed on the sidewalls 104a and the bottom portion 104c of the trench 104 prior to performing the ion doping process 130 (as shown in FIG. 1D). . In this embodiment, the protective layer 120 may be a germanium dioxide layer formed by a thermal oxidation process or a deposition process. The protective layer 120 covers the upper portion 109a, the lower portion 109b and the tandem portion 109c of the channel layer 109 for regulating the doping depth of the doping ions of the ion doping process 130, and protecting the channel layer 109 from ions. The bombardment was damaged.

Next, a dielectric layer 128 is formed to fill the trenches 104 and cover the channel layer 109 (as depicted in FIG. 1E). In some embodiments of the present specification, the formation of the dielectric layer 128 may include the steps of first filling the trench 104 with an insulating material, such as tantalum oxide, and overlying the multilayer stack structure 110. After that, then flatten A canonization step, such as chemical mechanical polishing, removes a portion of the insulating material over the multilayer stack structure 110.

Thereafter, at least one contact plug is formed over each of the ridge multilayer laminates 110a, 110b, and 110c, respectively, through the dielectric layer 128 and the protective layer 120, and over the ridge multilayer laminates 110a, 110b, and 110c. The upper portion 109a of the channel layer 109 is in contact. For example, in the present embodiment, contact plugs 129A and 129B are formed on the ridge multilayer laminate 110a; contact plugs 129C are formed on the ridge multilayer laminate 110b; contact plugs 129D and 129E are formed in the ridge multilayer laminate On layer 110c.

Next, an etching process is performed to remove a portion of the dielectric layer 128 on the top of the ridge multilayer laminates 110a and 110c and a portion 109a above the channel layer 109, which will be located above the channel layer 109 of the ridge multilayer laminate 110a. The first pads 109a1 and the second pads 109a2 separated from each other are respectively cut, thereby electrically isolating the contact plugs 129A and 129B; and the upper portions 109a of the channel layer 109 located in the ridge multilayer laminate 110c are respectively cut into each other. The separated fourth pads 109a4 and fifth pads 109a5 further electrically isolate the contact plugs 129D and 129E.

In the present embodiment, the contact plugs 129A and 129B on the top of the ridge multilayer laminate 110a are in electrical contact with the first pad 109a1 and the second pad 109a2, respectively; the contact plug on the top of the ridge multilayer laminate 110b. 129C is in electrical contact with the upper portion 109a (hereinafter referred to as the third pad 109a3) of the channel layer 109 at the top of the ridge multilayer laminate 110b; and the contact plugs 129D and 129E at the top of the ridge multilayer laminate 110c, respectively The four pads 109a4 are electrically connected to the fifth pad 109a5 touch.

The second pad 109a2 is electrically connected to the third pad 109a3 through a portion of the channel layer 109 (including the lower portion 109b and the tandem portion 109c) between the ridge multilayer laminates 110a and 110b, thereby forming a U-shaped channel, which will be formed. A plurality of memory cells 131 at the intersection of the U-shaped channel layer 109, the memory layer 106 and the conductive layers 112-114 are connected in series to form a U-shaped memory cell string 132 between the ridge multilayer laminates 110a and 110b. Similarly, the fourth pad 109a4 passes through a portion of the channel layer 109 (including the lower portion 109b and the tandem portion 109c) between the ridge multilayer laminates 110b and 110c and the third pad on the top of the ridge multilayer laminate 110b. 109a3 is turned on to form another U-shaped memory cell string 133 between the ridge-like multilayer stacks 110b and 110c.

In the present embodiment, the transistor 134 formed at the intersection of the channel layer 109 of the ridge multilayer laminate 110a, the memory layer 106 and the conductive layer 115 is connected in series with a plurality of memory cells 131, and can be used as a U-shaped memory cell string. Column 132's String Select Line (SSL) switch. The transistor 135 formed at the intersection of the channel layer 109 of the ridge multilayer laminate 110b, the memory layer 106 and the conductive layer 115 is connected in series with a plurality of memory cells 131 and can serve as a ground selection line for the U-shaped memory cell string 132. (Ground Select Line, GSL) switch. The transistors 136 and 137 formed at the intersections of the channel layer 109 of the ridge multilayer laminates 110a and 110b, the memory layer 106 and the conductive layer 111, respectively, are connected in series with a plurality of memory cells 131, and can be used as U-shaped memory cells. 132 Inversion Assist Gate (IG) switch.

Subsequently, through a series of back-end processes, the contact plugs 129B and 129D are respectively connected to corresponding bit lines (not shown), and the contact plugs 129C are connected. The connection to the common source line (not shown) completes the preparation of the stereo memory element 100 (as shown in FIG. 1F).

Since, as previously mentioned, the trench 104 has an upper and lower narrow outline, it will tighten the channel width of the U-shaped memory cell strings 132 and 133 at the trench bottom 104c, causing the channel resistance to rise sharply. By implanting the charged ion dopant into the lower portion 109b of the channel layer 109 at the bottom 104b of the trench by the ion doping process 130, the channel resistance values of the U-type memory cell strings 132 and 133 can be effectively reduced. Similarly, the implantation of the ion doping process 130 into the upper portion 109a of the charged ion dopant can further reduce the overall channel resistance of the U-shaped memory cell strings 132 and 133, and improve the operational quality of the stereo memory device 100. The technical advantage of reducing power consumption.

However, it should be noted that although the three-dimensional memory element 100 illustrated in FIG. 1F is a three-dimensional memory element having a U-shaped memory cell serial structure, it is reduced by the ion doping process 130 described in the foregoing embodiment. The method of the memory cell serial channel resistance of the stereo memory device 100 is not limited to the stereo memory element having the U-shaped memory cell string structure. For example, in other embodiments of the present specification, this method is also suitable for use in a stereo memory element having a bottom source structure.

Please refer to FIG. 2A to FIG. 2G. FIG. 2A to FIG. 2G are schematic cross-sectional views showing a series of process structures of the three-dimensional memory device 200 according to another embodiment of the present invention. A method of fabricating a stereo memory device 200 includes the steps of first providing a substrate 201 and forming a multilayer stack on the substrate 201. Structure 110 (as shown in Figure 2A). In some embodiments of the present invention, the substrate 201 may include a polysilicon layer 201a formed on the polysilicon layer 201a and in contact with the polysilicon layer 201a. Since the materials and manufacturing procedures of the multilayer stack structure 110 are detailed as above, they are not described herein.

Next, the multi-layer stack structure 110 is patterned to form a plurality of ridge-like multilayer stacks 210a, 210b, and 210c (as shown in FIG. 2B). In some embodiments of the invention, the patterning process 203 of the multilayer stack structure 210 includes forming a hard mask layer 202 on the multilayer stack structure 110 and patterning a hard mask layer (not shown). Then, the patterned hard mask layer 202 is used as an etching mask, and the multilayer stacked structure 110 is etched by an anisotropic etching process, such as a reactive ion etching process, thereby forming a Z-axis direction among the multilayer stacked structures 110. The extended trench 204 divides the multilayer stack structure 110 into a plurality of ridge multilayer stacks extending along the Y-axis direction, such as ridge-like multilayer stacks 210a, 210b, and 210c, and a portion of the polycrystalline germanium layer in the substrate 201. 201a is exposed outside via trench 204.

A memory layer 206 is then formed over the ridge multilayer stacks 210a, 210b, and 210c overlying the top of the ridge multilayer stacks 210a, 210b, and 210c and extending into the bottom 204c of the trench 204 (ie, exposed by the trench 204) A portion of the outer polysilicon layer 201a) and the trench sidewall 204a. Conformal deposition is then performed on the ridge multilayer stacks 210a, 210b, and 210c to form a first channel film 219a overlying the memory layer 206 (as depicted in Figure 2C).

Next, a portion of the first channel film 219a and the memory layer 206 located at the bottom of the trench 204 are removed by an etching process to be partially polycrystalline at the bottom of the trench 204. The ruthenium layer 201a is exposed to the outside. Thereafter, a conformal deposition is performed again to form a second channel film 219b on the first channel film 219a and the bottom 204c of the trench 204, integrated with the first channel film 219a into the channel layer 209, and at the bottom of the trench 204. A portion of the polysilicon layer 201a exposed by 204c is turned on (as shown in FIG. 2D).

An ion doping process 230 is performed to implant a plurality of ion dopants into the channel layer 209 (as depicted in FIG. 2E). Since the channel layer 209 covers the top of the ridge multilayer stacks 210a, 210b, and 210c and extends into the trench sidewalls 204a and 204c of the trenches 204, most of the dopant ions in the ion doping process 230 have a chance to be implanted. The inlet channel layer 209 is adjacent to the upper portion 209a of the opening 204b of the trench 204 and the lower portion 209b adjacent to the bottom 204c of the trench 204; and is less capable of being doped on the sidewall 204a of the trench 204 for connecting the upper portion 209a and the lower portion The string portion 209c of 209b. Therefore, the ion doping concentration in the tandem portion 209c of the channel layer 209 has substantially smaller ion doping concentration than the upper portion 209a and the lower portion 209b. In some embodiments of the present specification, the lower portion 209b may extend upward from the trench bottom 204c, but does not substantially exceed the top surface 111a of the bottommost conductive layer 111 of the multilayer stack structure 110.

Thereafter, a dielectric layer 228 is formed to fill the trench 204 and cover the channel layer 209 (as depicted in FIG. 2F).

Next, a plurality of contact plugs 229A-229F are formed on each of the ridge multilayer stacks 210a, 210b, and 210c, respectively, through the dielectric layer 228, and with channels above the ridge multilayer stacks 210a, 210b, and 210c. The upper portion 209a of the layer 209 is in contact. For example, in the present embodiment, the contact plugs 229A and 229B are formed. On the ridge multilayer laminate 210a; contact plugs 229C and 229D are formed on the ridge multilayer laminate 210b; contact plugs 229E and 229F are formed on the ridge multilayer laminate 210c.

Then, an etching process is performed to remove a portion of the dielectric layer 228 and a portion of the upper portion 209a of the channel layer 209 at the top of the same ridge multilayer stack, which will be located above the channel layer 209 of the same ridge multilayer stack. Cut into a plurality of pads separated from each other. Further, a plurality of contact plugs located above the same ridge multilayer stack are electrically isolated. For example, in the present embodiment, the etching process may divide the upper portion 209a of the channel layer 209 on the ridge multilayer laminate 210a into the first pad 209a1 and the second pad 209a2, thereby contacting the contacts 229A and 229B. Electrically isolated. The above etching process can divide the upper portion 209a of the channel layer 209 on the ridge multilayer laminate 210b into the third pad 209a3 and the fourth pad 209a4, thereby electrically isolating the contact plugs 229C and 229D. The etching process may divide the upper portion 209a of the channel layer 209 on the ridge multilayer laminate 210c into the fifth pad 209a5 and the sixth pad 209a6, thereby electrically isolating the contact plugs 229E and 229F.

Two contact plugs 229A and 229B on the top of the ridge multilayer laminate 210a are in electrical contact with the first pad 209a1 and the second pad 209a2, respectively. Two contact plugs 229C and 229D on the top of the ridge multilayer laminate 210b are in electrical contact with the third pad 209a3 and the fourth pad 209a4, respectively. Two contact plugs 229E and 229F on the top of the ridge multilayer laminate 210c are in sexual contact with the fifth pad 209a5 and the sixth pad 209a6, respectively. First to sixth pads 209a1 to 209a6 Each of the plurality of channel layers 209 (including the lower portion 209b and the string portion 209c) on the sidewalls of the trenches 204, respectively, will form a plurality of intersections at the intersection of the channel layer 209, the memory layer 206, and the conductive layers 112-114. The memory cells 231 are connected in series to form a parallel string Z of memory cells 232. Wherein, a plurality of transistors 234 formed at intersections of the channel layer 209, the memory layer 206 and the conductive layer 115 of the ridge multilayer laminates 210a, 210b and 210c, and the plurality of memory cells 231 corresponding to the memory cell string 232, respectively The series connection can be used as a serial select line (SSL) switch corresponding to the memory cell string 232, respectively. A plurality of transistors 235 formed at intersections of the channel layer 209, the memory layer 206, and the conductive layer 111 of the ridge multilayer laminates 210a, 210b, and 210c are respectively connected in series with the plurality of memory cells 231 of the corresponding memory cell string 232. It can be used as a ground selection line (GSL) switch corresponding to the memory cell string 232, respectively. The polysilicon layer 201a can serve as the bottom common source line of these memory cell strings 232.

Subsequently, through a series of back-end processes (not shown), the contact plugs 229A-229F are respectively connected to corresponding bit lines (not shown) to complete the preparation of the stereo memory device 200 as shown in FIG. 2G. .

By implanting the charged ion dopant into the upper portion 209a and the lower portion 209b of the channel layer 209 by the ion doping process 230, the resistance value of the overall channel can be effectively reduced to improve the operational quality of the stereo memory device 200 while reducing power. Loss.

According to the above embodiment, the present invention provides a three-dimensional memory element and a method of fabricating the same. The method of fabricating the three-dimensional memory component provides a patterned multilayer stack structure on the substrate and at least one of the multilayer stack structures A memory layer and a channel layer are sequentially formed on the sidewalls of the trenches. Before the trench is filled with the dielectric material, an ion doping process is performed on the channel layer, and a plurality of ion dopants are implanted into the channel layer, so that the channel layer is located on the first series of the trench sidewalls. The ion doping concentration is substantially less than the ion doping concentration of the channel layer adjacent to the first upper portion of the trench opening and the lower portion of the trench bottom portion.

Since the doping process can have charged ion dopants in the lower portion of the channel layer at the bottom of the trench, the resistance of the channel layer can be effectively reduced, and the number of insulating layers and conductive layers in the multilayer memory structure can be improved. The increase, causing the channel width to be partially tightened, causes the channel resistance to rise rapidly.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (10)

A three-dimensional memory component comprises: a substrate; a plurality of conductive layers on the substrate; a plurality of insulating layers on the substrate, and the conductive layers are alternately stacked to form a multi-layer stacked structure (multi- Layer stacks), wherein the multilayer stack structure has at least one trench passing through the conductive layers and the insulating layers; a memory layer covering the multilayer stack structure and extending at least to a first sidewall of the trench And a channel layer covering the memory layer, wherein the channel layer comprises a first upper portion, a first series portion and a lower portion, the first upper portion abutting an opening of the trench; the lower portion The portion is adjacent to the bottom of the trench; the first string portion is located above the first sidewall for connecting the first upper portion and the lower portion, and has an ion substantially smaller than the first upper portion and the lower portion Doping concentration. The three-dimensional memory component of claim 1, wherein the channel layer further comprises: a second upper portion adjacent to the opening of the trench and isolated from the first upper portion; and a second serial portion a second side wall of the trench is connected to the second upper portion, and the other end of the second string portion is connected to the first string portion by the lower portion. And the second serial portion has substantially less than the second An ion doping concentration of the upper portion and the lower portion. The three-dimensional memory component of claim 2, wherein the substrate comprises a dielectric isolation layer in contact with the multilayer stack structure, and the trench bottom is located in the dielectric isolation layer. The three-dimensional memory device of claim 1, wherein the substrate comprises a polysilicon layer in contact with the multilayer stack structure, and the bottom of the trench is located in the polysilicon layer. The three-dimensional memory component of claim 1, wherein the lower portion extends upward from the bottom of the trench but does not substantially exceed a top surface of one of the lowermost layers of the conductive layers. The three-dimensional memory device of claim 1, further comprising: a dielectric layer filling the trench and covering the channel layer; and a contact plug passing through the dielectric layer and The first upper portion is in contact. A method for fabricating a three-dimensional memory device, comprising: forming a multi-layer stack structure on a substrate, the multi-layer stack structure comprising a plurality of insulating layers and a plurality of conductive layers staggered; Patterning the multi-layer stack structure, wherein at least one trench is formed in the multi-layer stack structure, passing through the conductive layers and the insulating layers; forming a memory layer covering the multi-layer stack structure and extending at least to the trench Forming a channel layer covering the memory layer; and performing an ion doping process on the channel layer before filling the trench with a dielectric material, implanting a plurality of ion dopants into the channel layer And the channel layer is at least divided into an upper portion, a series of portions and a lower portion; wherein the upper portion abuts an opening of the groove; the lower portion is located at the bottom of the groove; the string portion is located at the Above the sidewall, the upper portion and the lower portion are connected; and the series portion has an ion doping concentration substantially smaller than the upper portion and the lower portion. The method for fabricating a three-dimensional memory device according to claim 7, further comprising: forming a dielectric layer to fill the trench and covering the channel layer; and forming at least two contact plugs through the dielectric layer And electrically contacting the upper portion; and performing an etching process to remove a portion of the dielectric layer and a portion of the via layer on top of one of the multilayer stacked structures to electrically isolate the at least two contact plugs. The three-dimensional memory component as described in claim 7 The method of fabricating, wherein the substrate comprises a dielectric isolation layer in contact with the multilayer stack structure, and the bottom of the trench is located in the dielectric isolation layer. The method of fabricating a three-dimensional memory device according to claim 7, wherein the substrate comprises a polysilicon layer in contact with the multilayer stack structure, and the bottom of the trench is located in the polysilicon layer.