TWI667656B - Decoding method and associated flash memory controller and electronic device - Google Patents

Abstract

The invention discloses a decoding method applied to a flash memory controller, which comprises the steps of: reading a first data from a flash memory module; decoding the first data, and according to the Decoding the first data to mark at least one specific address in the flash memory module, wherein the specific address corresponds to the data with high reliability error in the first data; reading from the flash memory module Taking a second data; and decoding the second data with reference to the specific address.

Description

Decoding method and related flash memory controller and electronic device

The present invention relates to a decoding method, and more particularly to a decoding method applied to a flash memory controller.

In order to further increase the capacity of the storage device, a stereoscopic NAND-type flash memory (3D NAND-type flash) module has been developed to enhance the storage density of the flash memory through a multi-layer stacking process. However, since the bit line in the stereo NAND type flash memory module is a vertical line having a large aspect ratio, the etching process does not allow each of the bit lines. The segments all have the same width, for example, the upper end of the bit line has a thicker width, and the upper end of the bit line is thinner, so it is easy to cause a short between the bit line and the word line. , or other short circuit / open circuit problems. In particular, the short-circuit problem described above may cause high reliability errors (HRE) for certain specific addresses in the stereo NAND type flash memory, that is, when reading information on the specific addresses and performing In the process of soft decoding, some error bits with higher reliability will appear, and these error bits with higher reliability will seriously affect the decoding operation and may cause decoding failure.

Accordingly, it is an object of the present invention to provide a decoding method that solves the problem of a decoding burden caused by a high reliability error of a flash memory module.

In an embodiment of the present invention, a decoding method for a flash memory controller is disclosed, which includes the steps of: reading a first data from a flash memory module; Decoding a data, and marking at least one specific address in the flash memory module according to the decoding result of the first data, wherein the specific address corresponds to the data with high reliability error in the first data; Reading a second data in the flash memory module; and decoding the second data by referring to the specific address.

In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes a read-only memory, a microprocessor, and a decoder, wherein the read-only memory system is configured to store a code, and the microprocessor is configured to execute the code to control the flash memory module Access. In the operation of the flash memory controller, the decoder decodes the first data after reading the first data from the flash memory module, and marks the first data according to the decoding result of the first data. At least one specific address in the flash memory module, wherein the specific address corresponds to data with a high reliability error in the first data; the decoder reads a second data from the flash memory module And referencing the specific address to decode the second data.

In another embodiment of the invention, an electronic device is disclosed that includes a flash memory module and a flash memory controller. In the operation of the electronic device, the flash memory controller decodes the first data after reading the first data from the flash memory module, and marks the first data according to the decoding result of the first data. At least one specific address in the flash memory module, wherein the special The location address corresponds to the data with high reliability error in the first data; the flash memory controller reads a second data from the flash memory module, and refers to the specific address to the The second data is decoded.

110‧‧‧Flash Memory Controller

112‧‧‧Microprocessor

112C‧‧‧ Code

112M‧‧‧Reading memory

114‧‧‧Control logic

116‧‧‧Buffered memory

118‧‧‧Interface logic

120‧‧‧Flash Memory Module

130‧‧‧Main device

132‧‧‧Encoder

134‧‧‧Decoder

202, 202_1~202_8‧‧‧Floating transistor

134‧‧‧Decoder

310‧‧‧Digital processing circuit

320‧‧‧LDPC decoding circuit

330‧‧‧High reliability error judgment circuit

340‧‧‧ storage unit

342‧‧‧Form

600~614‧‧‧ steps

BL1~BL3‧‧‧ bit line

WL0~WL2, WL4~WL6‧‧‧ character line

D_soft‧‧‧soft information

D_hard‧‧‧ final bit value

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.

Figure 2 is a schematic diagram of an example of a stereo NAND type flash memory.

FIG. 3 is a schematic diagram of a decoder according to an embodiment of the present invention.

Figure 4 is a schematic diagram of the decoder sequentially processing the data read from the eight floating gate transistors.

Figure 5 is a schematic diagram of a table in accordance with an embodiment of the present invention.

Figure 6 is a flow chart of a decoding method according to an embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to the embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory 112M is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the flash memory module 120. Control logic 114 includes an encoder 132 and a decoder 134. In this embodiment, the encoder 132 and the decoder 134 are used to perform a codec operation of a Quasi-Cyclic Low Density Party-Check (QC-LDPC) code.

In a typical situation, the flash memory module 120 includes a plurality of flash memory chips, and each of the flash memory chips includes a plurality of blocks (eg, through a microprocessor). The operation of erasing the flash memory module 120 by the flash memory controller 110 of the execution code 112C is performed in units of blocks. In addition, a block can record a specific number of pages, wherein the controller (eg, the memory controller 110 executing the code 112C through the microprocessor 112) writes to the flash memory module 120. The operation of the data is written in units of data pages. In this embodiment, the flash memory module 120 is a stereo NAND-type flash (3D NAND-type flash).

In practice, the flash memory controller 110 executing the code 112C through the microprocessor 112 can perform various control operations by using its own internal components, for example, using the control logic 114 to control the flash memory module 120. Access operations (especially for at least one block or at least one data page), buffer memory 116 for buffering, and interface logic 118 for communication with a host device 130 . The buffer memory 116 may be a static random access memory (SRAM), but the present invention is not limited thereto.

In an embodiment, the memory device 100 can be a portable memory device (for example, a memory card conforming to the SD/MMC, CF, MS, and XD standards), and the main device 130 is an electronic device connectable to the memory device. For example, mobile phones, notebook computers, desktop computers, etc. In another embodiment, the memory device 100 can be a solid state hard disk or an embedded storage device conforming to the Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications. The device is disposed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, and the main device 130 can be a processor of the electronic device.

In this embodiment, the flash memory module 120 is a stereo NAND type flash memory (3D NAND-type flash) module. Please refer to FIG. 2, which is a stereo NAND flash memory. A schematic diagram of the example. As shown in FIG. 2, the stereo NAND type flash memory includes a plurality of floating gate transistors 202, which pass through a plurality of bit lines (only shown as BL1 to BL3) and a plurality of word lines (for example, The illustrated WL0~WL2, WL4~WL6) constitute a stereo NAND type flash memory architecture. In Fig. 2, taking the uppermost one plane as an example, all the floating gate transistors on the word line WL0 constitute at least one data page, and all the floating gate transistors on the word line WL1 constitute at least one other data. The page, while all the floating gate transistors of the word line WL2 constitute another at least one data page... such a heap. In addition, depending on the way the flash memory is written, the definition between the word line WL0 and the data page (logical data page) will be different. In detail, when using single-level storage (Single-Level Cell) , SLC) mode, all floating gate transistors on word line WL0 only correspond to a single logical data page; when writing using Multi-Level Cell (MLC), word line All floating gate transistors on WL0 correspond to two, three or four logical data pages, wherein the case where all floating gate transistors on word line WL0 correspond to three logical data pages may be referred to as three layers. The Triple-Level Cell (TLC) architecture, and the case where all of the floating gate transistors on the word line WL0 correspond to four logical data pages may be referred to as a Quad-Level Cell (QLC) architecture. Since the person having ordinary knowledge in the art should be able to understand the structure of the stereo NAND type flash memory and the relationship between the word line and the data page, the related details will not be described herein. In addition, in the operation of the flash memory controller 110, the "data page" is a minimum write unit, and the "block" is a minimum erase unit.

In one embodiment, the gate and floating gate of each of the floating gate transistors are gated around the source and the drain to enhance channel sensing capability.

It should be noted that FIG. 2 is only an example of a stereo NAND type flash memory and a floating gate transistor 202, and is not intended to be a limitation of the present invention. Those skilled in the art should be able to understand the stereoscopic image. There are other types of NAND flash memory, for example, some of the word lines can be connected to each other.

As described in the prior art, the bit lines BL1 BL BL3 in the stereo NAND type flash memory module have a large aspect ratio, so the etching process does not make each segment of the bit line have the same The width is therefore likely to cause a short circuit between the bit lines BL1 BLBL3 and the word lines WL0 WL WL2, WL4 WL WL6, or other short circuit / open circuit problems, which may cause some of the floating gate transistors 202 A high reliability error (HRE) occurs in the bit stored thereon, that is, in the process of reading the information on the floating gate 202 and performing soft decoding, some high reliability occurs. The error bit, and these error bits with higher reliability will seriously affect the decoding operation and may cause decoding failure. In particular, the short-circuit problem described above becomes severe as the number of write/erase cycles (P/E cycle) increases, that is, when the number of write erases increases, a floating gate with high reliability error occurs. The number of transistors 202 also increases, which is a problem in decoding. Therefore, the decoder 134 in this embodiment is designed to record the physical address of the floating gate transistor 202 with high reliability errors during decoding to increase the probability of successful decoding as an aid in decoding.

Figure 3 is a schematic diagram of a decoder 134 in accordance with one embodiment of the present invention. As shown in FIG. 3, the decoder 134 includes a digital processing circuit 310, a low-density parity-check code (LDPC) decoding circuit 320, a high-reliability error determining circuit 330, and a storage. Unit 340, wherein storage unit 340 includes a table 342. In the operation of the decoder 134, first, the decoder 134 reads a first data from the flash memory module 120, wherein the first data may be fast. A sector or a chunk of a data page in a block in the flash memory module 120. In this embodiment, the first data is obtained by accessing the floating gate transistor 202 in the flash memory module 120 by using at least two different sensing voltages, and the first data includes The soft information D_soft of multiple bits, and the soft information D_soft of each bit contains an initial bit value (or may be called a sign bit) and at least two soft bits (soft bit) The initial bit value in the information of each bit is "0" or "1", and the at least two soft bits in the information of each bit are used to represent/calculate the initial The reliability of the bit value, for example, assuming that the initial bit value is "1" and the two soft bits are (1, 1), it means that the initial bit value "1" has high reliability. (or can be called a very high probability); assuming that the initial bit value is "1" and the two soft bits are (1, 0), it means that the initial bit value "1" has higher reliability. Assuming that the initial bit value is "1" and the two soft bits are (0, 1), it means that the initial bit value "1" has lower reliability; and the initial bit is assumed A value of "1" and two soft bit is (0, 0), it indicates that the initial bit value of "1" having the lowest reliability. In another example, assuming that the initial bit value is "0" and the two soft bits are (1, 1), it indicates that the initial bit value "1" has a very low reliability (or may be called Very high probability); assuming the initial bit value is "0" and the two soft bits are (1,0) or (0,1), it means that the initial bit value "0" has medium reliability. Assuming that the initial bit value is "0" and the two soft bits are (0, 0), it means that the initial bit value "0" has the highest reliability.

It should be noted that the above manner of using two soft bits to determine the reliability is merely an illustrative example and is not intended to be a limitation of the present invention. In other embodiments of the present invention, the two soft bits may be converted to different reliability representations and/or reliability in the flash memory module 120 according to a mapping table or other calculation manner. The judgment can be judged based on both the initial bit value and the bit value of the soft bit.

Next, the LDPC decoding circuit 320 decodes the soft information D_soft to generate the first resource. Multiple final bit values D_hard of the material.

The detailed operation of the soft information D_soft or the LDPC decoding circuit 320 is not the focus of the present invention, and the related details can refer to the Republic of China patent application: application number 100102086, or other related documents, so the digital processing circuit 310 The details of the LDPC decoding circuit 320 are not described herein.

Next, the high reliability error judging circuit 330 compares the soft information D_soft and the final bit value D_hard of the first data bit by bit to determine which bits in the first data have high reliability but the bit value thereof. It is erroneous, and these physical addresses corresponding to the bits with high reliability but whose bit values are erroneous are recorded in the table 342. 4 is taken as an example for illustration. FIG. 4 is a schematic diagram of the decoder 134 sequentially processing data read from the eight floating gate transistors 202_1 202 202_8. In FIG. 4, first, the decoder 134 reads the floating gate transistor 202_1, assuming that the initial bit value in the soft information D_soft generated is "1" and the two soft bits are (1, 1), The final bit value D_hard output by the LDPC decoding circuit 320 is "0", therefore, since the initial bit value is different from the final bit value (that is, the initial bit value is erroneous), plus two soft bits The element (1, 1) represents high reliability, so the floating gate transistor 202_1 is judged to correspond to a bit having a high reliability error (i.e., the information recorded by the floating gate transistor 202_1 is read out) It is an error bit with high reliability), and the physical address of the floating gate 202_1 is recorded in the table 342. Next, the decoder 134 reads the floating gate transistor 202_2, assuming that the initial bit value in the soft information D_soft generated is "1" and the two soft bits are (1, 0), and the LDPC decoding circuit 320 outputs The final bit value D_hard is "1", therefore, since the initial bit value is the same as the final bit value (that is, the initial bit value is correct), the floating gate transistor 202_2 is judged not to correspond. To a bit with a high reliability error, and the physical address of the floating gate 202_2 is not recorded in the table 342. Next, the decoder 134 reads the floating gate transistor 202_3, assuming that the initial bit value in the soft information D_soft generated is "1" and the two soft bits are (0, 1), and the final bit value D_hard output by the LDPC decoding circuit 320 is "1", therefore, since the initial bit value is the same as the final bit value (ie, The initial bit value is correct, so the floating gate transistor 202_3 is judged not to correspond to a bit having a high reliability error, and the physical address of the floating gate transistor 202_3 is not recorded in the table 342. . Next, the decoder 134 reads the floating gate transistor 202_4, assuming that the initial bit value in the soft information D_soft generated is "1" and the two soft bits are (0, 0), and the LDPC decoding circuit 320 outputs The final bit value D_hard is "1", although the initial bit value is different from the final bit value (ie, the initial bit value is wrong), but since the two soft bits (0, 0) represent With low reliability, the floating gate transistor 202_4 is judged not to correspond to a bit having a high reliability error, and the physical address of the floating gate 202_4 is not recorded in the table 342. Next, the decoder 134 reads the floating gate transistor 202_5, assuming that the initial bit value in the soft information D_soft generated is "0" and the two soft bits are (0, 0), and the LDPC decoding circuit 320 outputs The final bit value D_hard is "0". Therefore, since the initial bit value is the same as the final bit value (that is, the initial bit value is correct), the floating gate 202_5 is judged not to correspond. To a bit with a high reliability error, and the physical address of the floating gate 202_5 is not recorded in the table 342. Next, the decoder 134 reads the floating gate transistor 202_6, assuming that the initial bit value in the soft information D_soft generated is "0" and the two soft bits are (0, 1), and the LDPC decoding circuit 320 outputs The final bit value D_hard is "0", therefore, since the initial bit value is the same as the final bit value (that is, the initial bit value is correct), the floating gate 202_6 is judged not to correspond. To a bit with a high reliability error, and the physical address of the floating gate 202_6 is not recorded in the table 342. Next, the decoder 134 reads the floating gate transistor 202_7, assuming that the initial bit value in the soft information D_soft generated is "0" and the two soft bits are (1, 0), and the LDPC decoding circuit 320 outputs The final bit value D_hard is "1", although the initial bit value is different from the final bit value (ie, the initial bit value is wrong), but since the two soft bits (1, 0) represent Moderate reliability, rather than high reliability, is such that the floating gate 202_7 is judged not to correspond to a bit with a high reliability error, and the physical address of the floating gate 202_7 is not recorded in the table 342. Finally, the decoder 134 reads the floating gate transistor 202_8, false Let the initial bit value in the soft information D_soft generated by it be "0" and the two soft bits be (1, 1), and the final bit value D_hard output by the LDPC decoding circuit 320 is "0", therefore Since the initial bit value is the same as the final bit value (that is, the initial bit value is correct), the floating gate transistor 202_8 is judged not to correspond to a bit having a high reliability error, and the floating gate The physical address of transistor 202_8 is not recorded in table 342.

Figure 5 is a schematic illustration of a table 342 in accordance with one embodiment of the present invention. As shown in FIG. 5, the block number, the material page number, the block number, and the address information of the floating gate transistor 202 in which the high reliability error has occurred is recorded in the table 342. In addition, table 342 also records the number of times the floating gate transistor 202 has experienced an excessively high degree of reliability error during decoding.

In an embodiment, the decoder 134 shown in FIG. 3 may further include a temporary register to temporarily store the floating gate transistor 202 of the bit with high reliability error generated by the high reliability error determining circuit 330. The address is, and waits for the number of temporarily stored addresses to reach a critical value (for example, 10 addresses), and then writes them to the table 342.

In addition, since the space of the storage unit 342 is limited, the table 342 can use a Least recently used (LRU) algorithm during the writing process, that is, the floating gate of the high reliability error bit does not occur for a certain period of time. The address of transistor 202 is removed from table 342.

FIG. 6 is a flowchart of a decoding method according to an embodiment of the present invention, and the process steps are as follows:

Step 600: The process begins.

Step 602: The flash memory controller 110 reads a capital from the flash memory module 120. material.

Step 604: The decoder 134 decodes the data, wherein when the decoding is successful (ie, the LDPC decoding circuit 320 can generate the final bit value), the flow proceeds to step 606; and if the decoding fails, the flow proceeds to step 608.

Step 606: The decoder 134 outputs the decoded data, and the high reliability error judging circuit judges which bits in the data have high reliability but the bit values are wrong, and these have high reliability but their bits The physical address corresponding to the bit with the wrong value is recorded in table 342.

Step 608: Determine whether a part of the address in the flash memory module 120 corresponding to the data is recorded in the table 342. If yes, the process proceeds to step 612; if not, the process proceeds to step 610.

Step 610: Using other decoding methods, such as a method of error correction using a Redundant Array of Independent Disks (RAID) or a disk rescue method to facilitate decoding.

Step 612: Modify at least a part of the bits of the data corresponding to the plurality of bits having the high reliability error address to generate a modified data.

Step 614: Decode the modified data.

In step 612, the decoder 134 may first modify a bit to be decoded, wherein the bit corresponds to the floating gate transistor with the highest number of occurrences of high reliability errors, and then if the decoding fails again, the other is modified. Bit. For example, suppose that the floating gate transistor 202 corresponding to the first, fifth, sixth, and eighth bits in the data is recorded in the table 342, and the floating gate transistor corresponding to the fifth bit is recorded. 202 has the highest number of occurrences of high reliability errors, so when the data decoding fails, the decoder 134 may first flip the initial bit value of the 5th bit (eg, "0" to "1", or " 1" is changed to "0") to generate modified data for decoding. If the decoding still fails, then the first, sixth, and eighth bits will be used. The initial bit value is flipped to produce the modified data and then decoded again.

It should be noted that the description in the previous paragraph is merely illustrative and not a limitation of the present invention. In other embodiments, the decoder 134 may also initially convert the initial bit values of the first, fifth, sixth, and eighth bits to generate modified data for decoding. As long as the selection of the bit flip is based on the address recorded in the table 342 where a high reliability error has occurred, changes in the design are subject to the scope of the present invention.

In an embodiment, the information recorded in the table 342 can also be used to determine whether the number of floating gate transistors 202 in the block frequently occurs with high reliability errors, and to determine whether or not to erase according to this. Use this block. Specifically, when the content of the table 342 indicates that the address corresponding to the high reliability error in a specific block is higher than a critical value, in order to avoid the subsequent address corresponding to the high reliability error in the specific block. The microprocessor 112 may first move the valid data in the specific block to other blocks (ie, garbage collection operation), and then add the specific data to the other block (ie, garbage collection operation). The block is marked as invalid and the flash memory controller 110 is set to no longer write data to the particular block.

Briefly summarized in the present invention, in the decoding method of the present invention, the physical address corresponding to the bit in which the high reliability error occurs is continuously recorded in a table during the decoding process, and the content of the table can be used for subsequent decoding failure. When used. Due to the high probability that the floating gate transistor with high reliability error will continue to have errors, the success of the decoding will be seriously affected. Therefore, the present invention can reduce the floating of these high reliability errors during the decoding process. The effect of the gate transistor to increase the probability of successful decoding.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

Claims (17)

A decoding method applied to a flash memory controller includes: reading a first data from a flash memory module; decoding the first data, and decoding the first data according to the first data Marking at least one specific address in the flash memory module, wherein the specific address corresponds to data having a High Reliability Error (HRE) in the first data; from the flash memory module Reading a second data; and decoding the second data by referring to the specific address; wherein decoding the first data is a soft decoding operation, and decoding the first data In the process, an initial bit value and a reliability are calculated for each bit of the first data, and the data with high reliability error in the first data refers to the high reliability but the initial bit The meta value is wrong. The decoding method of claim 1, wherein the step of decoding the first data and marking the at least one specific address in the flash memory module according to the decoding result of the first data includes: And recording the at least one specific address in the flash memory module in a table according to the decoding result of the first data. The decoding method of claim 1, wherein the step of marking the at least one specific address in the flash memory module according to the decoding result of the first data comprises: each bit for the first data Meta-reading: reading the flash memory module to obtain the initial bit value corresponding to the bit and at least two soft bits; Performing soft decoding on the initial bit value and the at least two soft bits to obtain a final bit value of the bit and a reliability; determining whether the final bit value and the initial bit value are the same; The final bit value is different from the initial bit value, and the bit has a high reliability, and the bit is determined to be a bit with a high reliability error, and the bit is in the flash memory. The address in the module is used as the specific address to be recorded in the table. The decoding method of claim 3, further comprising: recording the number of occurrences of the specific address corresponding to the bit having the high reliability error in the decoding process of the first data. The decoding method of claim 1, wherein the second data corresponds to the at least one specific address, and the decoding method further comprises: decoding the second data; if the second data is decoded If the failure occurs, the at least one element corresponding to the at least one specific address in the second data is modified to generate a modified second data; and the modified second data is decoded. The decoding method of claim 5, wherein the second data corresponds to a plurality of specific addresses, and the decoding method further comprises: recording the plurality of specific addresses in the decoding process of the first data Corresponding to the number of occurrences of a bit having a high reliability error; wherein the at least one bit is the specific address corresponding to the highest number of occurrences of the bit having the high reliability error. The decoding method of claim 1, further comprising: determining whether the number of at least one specific address marked in a block in the flash memory module is higher than a critical value; If the number is above the threshold, the block is marked as invalid. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes: a read only memory for storing one a code for executing the code to control access to the flash memory module; and a decoder; wherein the decoder reads a first from the flash memory module Decoding the first data after the data, and marking at least one specific address in the flash memory module according to the decoding result of the first data, wherein the specific address corresponds to high reliability in the first data The data of the High Reliability Error (HRE); the decoder reads a second data from the flash memory module, and decodes the second data by referring to the specific address; wherein the decoder pair Decoding the first data into a soft decode operation, and calculating an initial bit value and a reliability for each bit of the first data in the process of decoding the first data And the first material has a high A data with a bad reliability means that the reliability is high but the initial bit value is wrong. The flash memory controller of claim 8, wherein the microprocessor records at least one specific address in the flash memory module in a table. The flash memory controller of claim 8, wherein each bit of the first data is: the decoder reads the flash memory module to obtain the corresponding pixel An initial bit value and at least two soft bits, the bit value and the at least two soft bits are soft decoded to obtain a final bit value of the bit and a reliability, and the Whether the final bit value and the initial bit value are the same, and if the final bit value is different from the initial bit value, and the bit has a high reliability, determining that the bit has a high reliability error The bit and the address of the bit in the flash memory module is used as the specific address to be recorded in the table. The flash memory controller of claim 10, wherein the microprocessor further records that the specific address corresponds to the occurrence of a bit with a high reliability error in the decoding process of the first data. frequency. The flash memory controller of claim 8, wherein the decoder decodes the second data, and if the decoding of the second data fails, the second data corresponds to at least one At least one bit of the specific address is modified to generate a modified second data, and the modified second data is decoded. The flash memory controller of claim 12, wherein the second data corresponds to a plurality of specific addresses, and the microprocessor further records the decoding of the plurality of specific addresses in the first data. The number of occurrences of a bit corresponding to a bit having a high reliability error in the process, and the at least one bit is the specific address corresponding to the number of occurrences of the bit having the high reliability error. A flash memory controller as described in claim 8 wherein the microprocessor Determining whether the number of at least one specific address in a block in the flash memory module is higher than a threshold, and if the number is higher than the threshold, marking the block as invalid . An electronic device includes: a flash memory module; and a flash memory controller for accessing the flash memory module; wherein the flash memory controller is from the flash memory After reading a first data, the module decodes the first data, and marks at least one specific address in the flash memory module according to the decoding result of the first data, where the specific address corresponds to the first a data having a High Reliability Error (HRE); the flash memory controller reads a second data from the flash memory module, and refers to the specific address to The second data is decoded; wherein the decoder decodes the first data into a soft decode operation, and the first data is decoded for each bit of the first data. An initial bit value and a reliability are calculated, and a bit with a high reliability error in the first data means that the reliability is high but the initial bit value is erroneous. The electronic device of claim 15, wherein for each bit of the first data: the flash memory controller reads the flash memory module to obtain the corresponding to the bit An initial bit value and at least two soft bits, the bit value and the at least two soft bits are soft decoded to obtain a final bit value of the bit and a reliability, and the Whether the final bit value and the initial bit value are the same, and if the final bit value is different from the initial bit value, and the bit has a high reliability, determining that the bit has a high reliability error Bit, and the address of the bit in the flash memory module is taken as the specific address Recorded in the form. The electronic device of claim 15, wherein the flash memory controller determines whether the number of at least one specific address marked in a block in the flash memory module is higher than one A threshold, and if the number is above the threshold, the block is marked as invalid.