TWI906994B - Method for accessing flash memory module and associated flash memory controller and memory device - Google Patents

Abstract

The present invention provides a method for accessing a flash memory module, which includes the following steps: using a first set of threshold voltages, a positively adjusted first set of threshold voltages, and a negatively adjusted first set of threshold voltages to read a first logical page of a physical page in the flash memory module to obtain first readout information, second readout information and third readout information respectively. decoding the first readout information, the second readout information and the third readout information to generate decoded data of the first logical page; generating an LLR mapping table according to the decoded data of the first logical page, the first readout information, the second readout information and the third readout information.

Description

Methods for accessing flash memory modules and related flash memory controllers and memory devices

This invention relates to a flash memory controller.

Flash memory stores data electronically through erasure and writing/programming, and is widely used in memory cards, solid-state drives, and portable multimedia players. Because flash memory is non-volatile, it does not require additional power to maintain the information it stores. Furthermore, flash memory offers fast data retrieval and better shock resistance, which explains its widespread adoption.

Flash memory can be divided into NOR flash memory and NAND flash memory. NAND flash memory has shorter erase and write times and requires less chip area per memory cell, thus allowing for higher storage density and lower cost per memory bit compared to NOR flash memory. Generally, flash memory stores data in an array of memory cells, and each memory cell is a floating-gate transistor. The floating gate transistor is used to implement the memory, and each memory cell can be set to the required critical voltage for conducting the memory cell implemented by the floating gate transistor by appropriately controlling the number of charges on the floating gate of the floating gate transistor, thereby storing a single bit of information or more than one bit of information. In this way, when one or more predetermined gate control voltages are applied to the control gate of the floating gate transistor, the conduction state of the floating gate transistor will indicate the one or more binary digits stored in the floating gate transistor.

However, due to certain factors, the number of charges originally stored in a memory cell may be affected/disrupted. For example, interference in flash memory may come from write/program disturbance, read disturbance, and/or retention disturbance. Taking NAND flash memory with memory cells that each store more than one bit of information as an example, a physical memory page contains multiple logical pages, and each logical page is read using one or more gate control voltages. For example, a memory cell used to store 4 bits of information might have one of 16 states (i.e., charge levels) corresponding to different numbers of charges (i.e., different critical voltages). However, due to the program/erase count (P/E count) and/or data retention time, the critical voltage distribution of the memory cells within the memory cell varies. The distribution will change, so using the original gate control voltage setting (i.e., the critical voltage setting) to read the information stored in the memory cell may not be able to obtain the stored information correctly due to the changed critical transformer distribution.

Therefore, one of the objectives of this invention is to provide a flash memory controller and a related control method, which can efficiently establish/update a log-likelihood ratio (LLR) mapping table based on the read information of the flash memory for subsequent decoding, thereby solving the problems described in the prior art.

In one embodiment of the present invention, a method for accessing a flash memory module is disclosed, comprising the following steps: using a first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages respectively to read a first logical data page of a physical data page in the flash memory module, so as to obtain a first read information, a second read information, and a... The third read information; the first read information, the second read information, and the third read information are decoded to generate decoded data of the first logic data page; an LLR mapping table is generated based on the decoded data of the first logic data page, the first read information, the second read information, and the third read information, for use when subsequently reading and decoding other logic data pages.

In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes: a read-only memory for storing program code; a cache memory; and a microprocessor for executing the program code to control access to the flash memory module; wherein the microprocessor is used to perform the following operations: reading using a first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages respectively. The flash memory module has a first logical data page of a physical data page, which obtains a first read information, a second read information, and a third read information respectively; the first read information, the second read information, and the third read information are decoded to generate decoded data of the first logical data page; an LLR mapping table is generated based on the decoded data of the first logical data page, the first read information, the second read information, and the third read information, for use when reading and decoding other logical data pages.

In one embodiment of the present invention, a memory device is disclosed, comprising a flash memory module and a flash memory controller. The flash memory controller performs the following operations: reading a first logical data page of a physical data page in the flash memory module using a first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages, respectively, to obtain a first read information, a second read information, and a third read information; for the first read... The first logical data page is decoded by the output information, the second read information, and the third read information to generate decoded data of the first logical data page; an LLR mapping table is generated based on the decoded data of the first logical data page, the first read information, the second read information, and the third read information for subsequent use when reading and decoding other logical data pages.

Figure 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to the present embodiment, the flash memory controller 110 includes a microprocessor 112, a read-only memory (ROM) 112M, a control logic 114, a cached memory 116, and an interface logic 118. The read-only memory 112M is used to store code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the flash memory module 120. The control logic 114 includes an encoder 132, a decoder 134, a control unit 136, and an LLR mapping table generation/update unit 138. The encoder 132 is used to encode the data written to the flash memory module 120 to generate a corresponding check code (or error correction code, ECC), and the decoder 134 is used to decode the data read from the flash memory module 120. Furthermore, the control unit 136 and the LLR mapping table generation/update unit 138 are implemented by circuit elements, and their specific operation will be explained in subsequent embodiments.

In a typical configuration, the flash memory module 120 includes multiple flash memory chips, and each flash memory chip contains blocks. The flash memory controller 110 performs data copying, erasing, and merging operations on the flash memory module 120 on a block-by-block basis. Additionally, a block can record a specific number of data pages, and the flash memory controller 110 writes data to the flash memory module 120 on a page-by-page basis. In other words, a block is the smallest unit of erasure in the flash memory module 120, while a data page is the smallest unit of writing in the flash memory module 120.

In practice, the flash memory controller 110, which executes program code 112C through microprocessor 112, can perform a variety of control operations using its internal components, such as: using control logic 114 to control the access operation of flash memory module 120 (especially the access operation of at least one block or at least one data page), using cache memory 116 to perform the necessary buffering processing, and using interface logic 118 to communicate with a host device 130.

In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card conforming to SD/MMC, CF, MS, or XD standards), and the main device 130 may be an electronic device that can be connected to the memory device, such as a mobile phone, a laptop, a desktop computer, etc. In another embodiment, the memory device 100 may be a solid-state drive or an embedded storage device conforming to Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, to be installed in an electronic device, such as a mobile phone, watch, portable medical diagnostic device (e.g., medical bracelet), laptop computer, or desktop computer, and in this case, the main device 130 may be a processor of the electronic device.

In this embodiment, the flash memory module 120 is a 3D NAND-type flash memory module, wherein each block is composed of multiple word lines, multiple bit lines, and multiple memory cells. Since the 3D NAND-type flash memory architecture is well known to those skilled in the art, it will not be described in detail in this specification.

Figure 2 is a schematic diagram of a block 200 included in the flash memory module 120, wherein the block 200 includes multiple physical data pages P_0, P_1, P_2, ..., P_N, and each physical data page P_0 ~ P_N contains multiple memory units (e.g., floating gate transistors) 103. For example, for a target physical data page P_0 to be read, it contains memory units M_0 ~ M_K. In order to read the data stored in memory units M_0 ~ M_K of the target entity data page P_0, the gate control voltages VG_0 ~ VG_N should be appropriately set to read multiple bit values B0 ~ BK from memory units M_0 ~ M_K respectively. If each memory unit 103 is used to store N bits, that is, the target entity data page P_0 contains N logical data pages, then the flash memory 102 will set the gate control voltage VG_0 to ( ^2N -1) voltage levels in order to identify the N bits of each memory unit 103 in the target entity data page P_0.

Figure 3 is a schematic diagram of each memory unit 103 according to an embodiment of the present invention for storing 4 bits. As shown in Figure 3, each memory unit can have sixteen states, and each state represents a different combination of four bits (named top bit, upper bit, middle bit, and lower bit, respectively). In the embodiment shown in Figure 3, when the memory unit is programmed to have state S0, the top, upper, middle, and bottom bits of the memory unit are stored as (1, 1, 1, 1); when the memory unit is programmed to have state S1, the top, upper, middle, and bottom bits of the memory unit are stored as (1, 1, 1, 0); when the memory unit is programmed to have state S2, the top, upper, middle, and bottom bits of the memory unit are stored as (1, 0, 1, 1). 0); When the memory unit is programmed to have state S3, the top, top, middle, and bottom bits of the memory unit are (1, 0, 0, 0); When the memory unit is programmed to have state S4, the top, top, middle, and bottom bits of the memory unit are (1, 0, 0, 1); When the memory unit is programmed to have state S5, the top, top, middle, and bottom bits of the memory unit are (0, 0, 0, 1). 1) When the memory unit is programmed to have state S6, the top, top, middle, and bottom bits of the memory unit are stored as (0, 0, 0, 0); when the memory unit is programmed to have state S7, the top, top, middle, and bottom bits of the memory unit are stored as (0, 0, 1, 0); when the memory unit is programmed to have state S8, the top, top, middle, and bottom bits of the memory unit are stored as (0, 1, 1, 0). 0); When the memory unit is programmed to have state S9, the top, top, middle, and bottom bits of the memory unit are (0, 1, 0, 0); When the memory unit is programmed to have state S10, the top, top, middle, and bottom bits of the memory unit are (1, 1, 0, 0); When the memory unit is programmed to have state S11, the top, top, middle, and bottom bits of the memory unit are (1, 1, 0, 0). 1) When the memory unit is programmed to have state S12, the top, top, middle, and bottom bits of the memory unit are stored as (0, 1, 0, 1); when the memory unit is programmed to have state S13, the top, top, middle, and bottom bits of the memory unit are stored as (0, 1, 1, 1); when the memory unit is programmed to have state S14, the top, top, middle, and bottom bits of the memory unit are stored as (0, 0, 1, 1). 1); and when the memory unit is programmed to have state S15, the top, upper, middle and lower bits stored in the memory unit are (1, 0, 1, 1).

In the related technology, taking data page P_0 as an example, when the top bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply a gate control voltage VG_0 with four critical voltages VT5, VT10, VT12 and VT15 to read the memory cell. If the memory cell is conducting when a critical voltage VT5 is applied, the top bit is determined to be "1"; if the memory cell is not conducting when a critical voltage VT5 is applied and the memory cell is conducting when a critical voltage VT10 is applied, the top bit is determined to be "0"; if the memory cell is not conducting when a critical voltage VT10 is applied and the memory cell is conducting when a critical voltage VT10 is applied, the top bit is determined to be "0". When the memory cell is turned on by the critical voltage VT12, the top bit is determined to be "1"; if the memory cell is not turned on when the critical voltage VT12 is applied and the memory cell is turned on when the critical voltage VT15 is applied, the top bit is determined to be "0"; and if the memory cell is not turned on when the critical voltage VT15 is applied, the top bit is determined to be "1". When the top bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply a gate control voltage VG_0 with three critical voltages VT2, VT8 and VT14 to read the memory cell. If the memory cell is turned on when a critical voltage VT2 is applied, the upper bit is determined to be "1"; if the memory cell is not turned on when a critical voltage VT2 is applied and the memory cell is turned on when a critical voltage VT8 is applied, the upper bit is determined to be "0"; if the memory cell is not turned on when a critical voltage VT8 is applied and the memory cell is turned on when a critical voltage VT14 is applied, the upper bit is determined to be "1"; if the memory cell is not turned on when a critical voltage VT14 is applied, the upper bit is determined to be "0". When the intermediate bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply a gate control voltage VG_0 with four critical voltages VT3, VT7, VT9, and VT13 to read the memory cell. If the memory cell is conducting when the critical voltage VT3 is applied, the intermediate bit is determined to be "1"; if the memory cell is not conducting when the critical voltage VT3 is applied and the memory cell is conducting when the critical voltage VT7 is applied, the intermediate bit is determined to be "0"; if the memory cell is not conducting when the critical voltage VT7 is applied and the memory cell is not conducting when the critical voltage VT13 is applied, the intermediate bit is determined to be "0"; if the memory cell is not conducting when the critical voltage VT7 is applied and the memory cell is not conducting when the critical voltage VT13 is applied, the intermediate bit is determined to be "0". When the memory cell is turned on by the critical voltage VT9, the intermediate bit is determined to be "1"; if the memory cell is not turned on when the critical voltage VT9 is applied and the memory cell is turned on when the critical voltage VT13 is applied, the intermediate bit is determined to be "0"; and if the memory cell is not turned on when the critical voltage VT13 is applied, the intermediate bit is determined to be "1". When the lower bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply a gate control voltage VG_0 with four critical voltages VT1, VT4, VT6 and VT11 to read the memory cell. If the memory cell is conducting when a critical voltage VT1 is applied, the lower bit is determined to be "1"; if the memory cell is not conducting when a critical voltage VT1 is applied and the memory cell is conducting when a critical voltage VT4 is applied, the lower bit is determined to be "0"; if the memory cell is not conducting when a critical voltage VT4 is applied and the memory cell is conducting when a critical voltage VT4 is applied, the lower bit is determined to be "0". When the memory cell is turned on when the critical voltage VT6 is applied, the lower bit is determined to be "1"; if the memory cell is not turned on when the critical voltage VT6 is applied and the memory cell is turned on when the critical voltage VT11 is applied, the lower bit is determined to be "0"; and if the memory cell is not turned on when the critical voltage VT11 is applied, the lower bit is determined to be "1".

It should be noted that the Gray code shown in Figure 3 is for illustrative purposes only and is not intended to limit the invention. Any suitable Gray code can be used in the memory device 100, and the critical voltages used to determine the top, upper, middle, and lower bits can be changed accordingly.

However, due to certain factors, such as the increase in the number of write/read operations and/or data retention time, the distribution of each state shown in Figure 3 of the flash memory module 120 may shift or widen, thus causing the critical voltage used to read the memory unit to no longer be the most suitable critical voltage. Taking Figure 4 as an example, due to the influence of the number of write/read operations and/or data retention time of the flash memory module 120, states S0 and S1 become wider and shift to the left. At this time, the optimal critical voltage should correspond to the intersection of the distribution of states S0 and S1, i.e., VT1' in the figure. If the original critical voltage VT1 is used to read the memory cell, the read data will have a higher error rate, which may cause problems in the processing of the decoder 134. Similarly, due to the impact of the number of writes/reads and/or data retention time of the flash memory module 120, states S10 and S11 become wider and shift to the right. At this time, the optimal critical voltage should correspond to the intersection of the distribution of states S10 and S11, i.e., VT11' in the figure. If the original critical voltage VT11 is used to read the memory cell, the read data will have a higher error rate, which may cause problems in the processing of the decoder 134. Therefore, in order to solve the problem of state distribution offset and/or width variation of the above memory units, the present invention proposes a control method that can generate/update the LLR mapping table based on the data that has been successfully decoded, so as to increase the probability of subsequent data being successfully decoded.

Figure 5 is a flowchart of a method for accessing a flash memory module 120 according to an embodiment of the present invention. At step 500, the process begins. At step 502, the microprocessor 112 in the flash memory controller 110 receives a read instruction, such as a read instruction from the device 130, to begin reading a first logical data page from a physical data page. Specifically, the microprocessor 112 transmits a read request to the flash memory module 120 via control logic 114 to request reading the first logical data page. Upon receiving the read request, the flash memory module 120 uses a first set of critical voltages to read a segment of the first logical data page to obtain read information. For ease of explanation below, the physical data page is exemplified by the physical data page P_0 shown in Figure 2, and each memory unit in the physical data page P_0 can store 4 bits. That is, the physical data page P_0 contains four logical data pages, and the four logical data pages are respectively used to store the top bit, the upper bit, the middle bit, and the lower bit shown in Figure 3. Furthermore, in the following description, the first logical data page is the logical data page used to store the upper bit.

In step 504, the decoder 134 of the flash memory controller 110 decodes the read information of a segment of the first logic data page. In this embodiment, since the first logic data page is the logic data page used to store upper bits in Figure 3, the first set of critical voltages used to read the first logic data page includes the critical voltages VT2, VT8, and VT14 shown in Figure 3 or Figure 6. Furthermore, the segment in the first logical data page being read can be a codec unit, which can be 4 kilobytes (KB) in size or other suitable sizes. The decoding process of the decoder 134 for this segment can be a hardware decoding process, where hardware decoding can be a BCH code (Bose-Chaudhuri-Hocquenghem code) or a low-density parity-check code (LDPC) decoding method. Since the decoding operation of the decoder 134 is well known to those skilled in the art, the details of the decoding operation will not be described here.

In step 506, the decoder 134 determines whether the read information of the segment can be successfully decoded. If the decoding is successful, the process proceeds to step 518 to end the reading operation of that segment of the first logic data page; if the decoding fails, the process proceeds to step 508.

In step 508, the flash memory controller 110 obtains a first read information, a second read information, and a third read information of that segment of the first logic data page. The first read information, the second read information, and the third read information are obtained by the flash memory module 120 reading that segment of the first logic data page using a first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages, respectively. In one embodiment, the first read information can be the read information mentioned in step 502, while the read information temporarily stored in control logic 114 can be directly used as the first read information in step 508. Taking Figure 6 as an example, the control unit 136 of the flash memory controller 110 can send a read request to the flash memory module 120 to read the first logic data page using the first set of positively adjusted critical voltages, i.e., critical voltages (VT2+Δ), (VT8+Δ), and (VT14+Δ), to obtain the second read information. Here, "Δ" can be... The adjustment value (voltage value) is any suitable value; then, the control unit 136 of the flash memory controller 110 can send another read request to the flash memory module 120 to read the first logic data page using the negatively adjusted first set of critical voltages, namely the critical voltages (VT2-Δ), (VT8-Δ), and (VT14-Δ), to obtain the third read information. In this embodiment, the first read information, the second read information, and the third read information are temporarily stored in a buffer area in the control logic 114.

In this embodiment, assuming that the size of this segment of the first logic data page is 4KB (i.e., 32768 bits), then each of the first read information, the second read information, and the third read information will also contain 32768*3 bits.

In step 510, decoder 134 uses a default LLR mapping table to perform software decoding on that segment of the first logic data page. Specifically, each bit in the first read information can be considered as a hard bit or a sign bit, while each bit in the second and third read information is considered as a soft bit. For each memory unit, it will have three bits of information, namely a hard bit, a first soft bit, and a second soft bit, hereinafter represented as (BH, BS1, BS2). In addition, the information of the above three bits (BH, BS1, BS2) can have eight combinations, which are (1, 1, 1), (1, 1, 0), (1, 0, 1), (1, 0, 0), (0, 1, 1), (0, 1, 0), (0, 0, 1), (0, 0, 0). The default LLR mapping table contains (BH, BS1, BS2) and the corresponding LLR values, where the LLR values reflect the relative reliability. For example, if (BH, BS1, BS2) equals (1, 1, 1), it means that the uppermost bit of the memory unit has the highest reliability of "1" (e.g., 99% reliability is "1"); if (BH, BS1, BS2) equals (1, 1, 0), it means that the uppermost bit of the memory unit has the second highest reliability of "1"; if (BH, BS1, BS2) equals (0, 1, 1), it means that the uppermost bit of the memory unit has the highest reliability of "0", and so on. After determining the LLR value of each memory unit according to the default LLR mapping table, the LDPC decoding circuit in the decoder 134 can begin software decoding of that segment of the first logic data page based on these LLR values. Furthermore, since the operation of the LLR mapping table and LDPC software decoding is well known to those skilled in the art, these details will not be described here.

In step 512, the decoder 134 determines whether the segment can be successfully decoded. If the decoding fails, the process proceeds to step 514; if the decoding is successful, the process proceeds to step 516.

In step 514, if the control logic 114 contains other LLR mapping tables, the decoder 134 uses the other LLR mapping table to perform software decoding on that segment of the first logic data page. Furthermore, if all LLRs have been used and none have been able to successfully decode that segment of the first logic data page, the decoder 134 can use other suitable decoding methods, such as redundant array of independent disks (RAID) decoding.

In step 516, the LLR mapping table generation/update unit 138 generates a new LLR mapping table based on the decoded data, first read information, second read information, and third read information of that segment of the first logical data page, for use by the subsequent decoder 134 when decoding other segments. Specifically, the decoded data, first read information, second read information, and third read information have the same number of bits, for example, 32,768 bits, and for each memory unit, it will have four bits of information, namely the decoded bits, hard bits, first soft bits, and second soft bits, hereinafter represented as (DD, BH, BS1, BS2). Furthermore, the information of the above four bits (DD, BH, BS1, BS2) can have 16 combinations, which are (1, 1, 1, 1), (1, 1, 1, 0), (1, 1, 0, 1), (1, 1, 0, 0), (1, 0, 1, 1), (1, 0, 1, 0), (1, 0, 0, 1), (1, 0, 0, 0), (0, 1, 1, 1), (0, 1, 1, 0), (0, 1, 0, 1), (0, 1, 0, 0), (0, 0, 1, 1), (0, 0, 1, 0), (0, 0, 0, 1), (0, 0, 0, 0). The 16 possible combinations of the four-bit information (DD, BH, BS1, BS2) represent combinations with different levels of reliability and whether the decoded bits are the same as the hard bits. For example, (DD, BH, BS1, BS2) equals (1, 1, 1, 1), indicating that both the decoded bits and the hard bits are "1" and have the highest reliability. That is, the upper bits of the memory unit have the highest reliability of "1" in the information read before decoding, and the decoded bits are indeed "1". (DD, BH, BS1, BS2) equals (0, 1, 1, 1), indicating that the upper bits of the memory unit have the highest reliability of "1" in the information read before decoding, but the decoded bits are "0". (DD, BH, BS1, BS2) equals (0, 0, 1, ... 1) indicates that both the decoded bits and the hard bits are "0" and have the highest reliability. That is, the upper bits of the memory unit have the highest reliability of "0" in the information read before decoding, and the decoded bits are indeed "0"; (DD, BH, BS1, BS2) is equal to (1, 0, 1, 1), indicating that the upper bits of the memory unit have the highest reliability of "0" in the information read before decoding, but the decoded bits are "1". The LLR mapping table generation/update unit 138 counts 16 combinations of the above four-bit information (DD, BH, BS1, BS2) based on the decoded data of that segment of the first logical data page, the first read information, the second read information, and the third read information, to calculate the number of each combination, and calculates the LLR value corresponding to (BH, BS1, BS2) in a new LLR mapping table. For example, assuming that the number of (DD, BH, BS1, BS2) equal to (1, 1, 1, 1) is N1, and the number of (DD, BH, BS1, BS2) equal to (1, 0, 1, 1) is N2, then in one embodiment, the LLR value corresponding to (BH, BS1, BS2) equal to (1, 1, 1) in the new LLR mapping table can be calculated as follows: ln(N1/N2). In another example, assuming that the number of (DD, BH, BS1, BS2) equal to (0, 0, 1, 1) is N3, and the number of (DD, BH, BS1, BS2) equal to (1, 1, 1, 1) is N4, then in one embodiment, the LLR value corresponding to (BH, BS1, BS2) equal to (0, 1, 1) in the new LLR mapping table can be calculated as follows: ln(N3/N4). Similarly, any of the other combinations of (BH, BS1, BS2) in the new LLR mapping table can also be obtained by taking the count values of two combinations of (DD, BH, BS1, BS2) (that is, by dividing the count values of these two combinations and taking the logarithm). Since those skilled in the art should be able to understand how to calculate other LLR values after reading the above embodiments, the calculation methods for all LLR values are not listed here.

Next, the LLR mapping table generation/update unit 138 temporarily stores the new LLR mapping table in the storage unit of control logic 114. In one embodiment, if the LLR mapping table generation/update unit 138 has previously generated a certain number of LLR mapping tables, causing insufficient space in the storage unit, the LLR mapping table generation/update unit 138 can use the new LLR mapping table to replace the previously generated LLR mapping table for use by the subsequent decoder 134 in step 514 when decoding other segments of the first logic data page or blocks of other logic data pages.

As described above, since the new LLR mapping table is generated from the decoded data of that segment of the first logical data page, the first read information, the second read information, and the third read information, it can more accurately reflect the critical voltage offset of the memory unit inside block 200 or physical data page P_0. Therefore, by establishing the new LLR mapping table, the decoder 134 can have a higher success rate when decoding subsequent segments.

In the above embodiments, the new LLR mapping table is used for the critical voltages VT2, VT8, and VT14 used to read the first logical data page of the physical data page P_0. However, since the distribution offset of each state S0 to S15 of the memory unit is different, that is, the offset direction and offset amount of the critical voltages VT1 to VT15 are also different, the above-mentioned new LLR mapping table still has limitations in improving the decoding capability of the decoder 134. Therefore, in another embodiment of the present invention, the LLR mapping table generation/update unit 138 generates a new LLR mapping table for each of the critical voltages VT2, VT8, and VT14 for use by each of the critical voltages VT2, VT8, and VT14.

Specifically, in step 516, after obtaining the decoded data, first read information, second read information and third read information of the segment of the first logical data page of the physical data page P_0, the control unit 136 sends one or more read requests to obtain the decoded data of the segment of the second logical data page of the physical data page P_0 and the decoded data of the segment of the third logical data page of the physical data page P_0. In this embodiment, the purpose of reading the decoded data of that segment of the second logic data page and the decoded data of that segment of the third logic data page is to identify which of the critical voltages VT2, VT8, and VT14 the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information correspond to respectively. Therefore, the selection of the second logic data page and the third logic data page needs to meet the following conditions: (1) For each of the first set of critical voltages VT2, VT8, and VT14, the two adjacent states correspond to the same bit value on the second logic page and also on the third logic page. The bit value (b1) corresponding to the two adjacent states of each of the first set of critical voltages VT2, VT8, and VT14 on the second logic page and the bit value (b2) corresponding to the third logic page have different (b1, b2) combinations, and each critical voltage VT2, VT8, and VT14 corresponds to (b1, b2) equal to three of (1, 1), (1, 0), (0, 1), and (0, 0). Taking Figure 3 as an example, the second and third logic data pages can be used to store the top and bottom position logic data pages, respectively. The two adjacent states S1 and S2 of the critical voltage VT2 have a first combination (1, 0) in the second and third logic data pages, respectively. The two adjacent states S7 and S8 of the critical voltage VT8 have a second combination (0, 0) in the second and third logic data pages, respectively. The two states S13 and S14 adjacent to the critical voltage VT14 have a third combination (0, 1) in the second logic data page and the bit value corresponding to the third logic data page.

Next, when the bit value corresponding to the second logic data page and the bit value corresponding to the third logic data page have the first combination (1, 0), the LLR mapping table generation/update unit 138 generates a first LLR mapping table based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information, for use by the subsequent decoder 134 when decoding other segments. The first LLR mapping table is used by the decoder 134 when it subsequently reads the memory unit using the critical voltages VT2, (VT2-Δ), and (VT2+Δ). Furthermore, when the bit values corresponding to the second logic data page and the bit values corresponding to the third logic data page have a second combination (0, 0), the LLR mapping table generation/update unit 138 generates a second LLR mapping table based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information, for subsequent decoder 134 to use when decoding other segments. The second LLR mapping table is used by decoder 134 when subsequently using the critical voltage VT8, (VT8-Δ), and (VT8+Δ) to read memory units. Finally, when the bit values corresponding to the second logic data page and the bit values corresponding to the third logic data page have a third combination (0, 1), the LLR mapping table generation/update unit 138 generates a third LLR mapping table based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information, for use by the subsequent decoder 134 when decoding other segments. The third LLR mapping table is used by the decoder 134 when it subsequently reads the memory unit using the critical voltage VT14, (VT14-Δ), and (VT14+Δ). The above description is merely a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Memory Device 103: Memory Unit 110: Flash Memory Controller 112: Microprocessor 112M: Read-Only Memory 112C: Program Code 114: Control Logic 116: Cache Memory 118: Interface Logic 120: Flash Memory Module 130: Main Unit 132: Encoder 134: Decoder 136: Control Unit 138: LLR Mapping Table Generation/Update Unit 200: Blocks 500 ~ 516: Steps M_0 ~ M_K: Memory Units P_0 ~ P_N: Physical Data Pages VG_0 ~ VG_N: Gate Control Voltages B0 ~ BK: Bit Values S0 ~ S15: Status VT1 ~ VT15: Critical voltage; VT1’, VT11’: Adjusted critical voltage

Figure 1 is a schematic diagram of a memory device according to an embodiment of the present invention. Figure 2 is a schematic diagram of a block included in a flash memory module. Figure 3 is a schematic diagram of each memory unit storing 4 bits according to an embodiment of the present invention. Figure 4 is a schematic diagram showing the offset or widening of the distribution of each state of the memory unit. Figure 5 is a flowchart of a method for accessing a flash memory module according to an embodiment of the present invention. Figure 6 is a schematic diagram of reading a data page using different critical voltages according to an embodiment of the present invention.

500 ~ 516: Steps

Claims (12)

A method for accessing a flash memory module includes: using a first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages to read a first logical data page of a physical data page in the flash memory module, so as to obtain a first read information, a second read information, and a third read information, respectively. The first read information, the second read information, and the third read information are decoded to generate decoded data of the first logic data page; a log-likelihood ratio is generated based on the decoded data of the first logic data page, the first read information, the second read information, and the third read information. A ratio (LLR) mapping table is used for subsequent reading and decoding of other logical data pages; wherein the physical data page contains multiple memory units, each memory unit is used to store multiple bits, each memory unit has multiple states, and the multiple states are used to indicate different combinations of the multiple bits; and the first read information contains a hard bit of each memory unit, the second read information contains a first soft bit of each memory unit, and the third read information contains a second soft bit of each memory unit; and according to the The step of generating the LLR mapping table from the decoded data, the first read information, the second read information, and the third read information of the first logical data page includes: counting 16 combinations of the decoded data, the hard bits, the first soft bits, and the second soft bits based on the decoded data, the first read information, the second read information, and the third read information of the first logical data page, to calculate the number of each combination of the decoded data, the hard bits, the first soft bits, and the second soft bits, for calculating the LLR mapping table. The method as described in claim 1, wherein the first set of critical voltages includes at least a first critical voltage, a second critical voltage, and a third critical voltage; the positively adjusted first set of critical voltages includes the first critical voltage plus an adjustment value, the second critical voltage plus the adjustment value, and the third critical voltage plus the adjustment value; and the negatively adjusted first set of critical voltages includes the first critical voltage minus the adjustment value, the second critical voltage minus the adjustment value, and the third critical voltage minus the adjustment value. A method for accessing a flash memory module includes: using a first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages to read a first logical data page of a physical data page in the flash memory module, so as to obtain a first read information, a second read information, and a third read information, respectively. The first read information, the second read information, and the third read information are decoded to generate decoded data of the first logic data page; a log-likelihood ratio is generated based on the decoded data of the first logic data page, the first read information, the second read information, and the third read information. A ratio (LLR) mapping table is used for subsequent reading and decoding of other logical data pages; wherein the decoded data is a first decoded data, and the method further includes: using a second set of critical voltages to read a second logical data page of the physical data page in the flash memory module, and decoding the read information to obtain a second decoded data; using a third set of critical voltages to read a third logical data page of the physical data page in the flash memory module, and decoding the read information to obtain a third... The steps of generating the LLR mapping table based on the decoded data of the first logical data page, the first read information, the second read information, and the third read information include: generating at least one first LLR mapping table, one second LLR mapping table, and one third LLR mapping table based on the decoded data of the first logical data page, the first read information, the second read information, the third read information, the second decoded data of the second logical data page, and the third decoded data of the third logical data page. As described in claim 3, the physical data page includes multiple memory units, each memory unit storing multiple bits, each memory unit having multiple states, and the multiple states indicating different combinations of the multiple bits; for each of the first set of critical voltages, two adjacent states correspond to the same bit value in the second logical data page, and also correspond to the same bit value in the third logical data page; in the first set of critical voltages... Each critical voltage has two adjacent states whose corresponding bit values in the second logic data page and the third logic data page have different combinations; and based on the decoded data of the first logic data page, the first read information, the second read information, the third read information, the second decoded data of the second logic data page, and the third decoded data of the third logic data page, at least the first LLR mapping table and the second LLR are generated. The steps for creating the mapping table and the third LLR mapping table include: If the bit values corresponding to the second logic data page and the bit values corresponding to the third logic data page have a first combination, generating the first LLR mapping table based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information; if the bit values corresponding to the second logic data page and the bit values corresponding to the third logic data page have a second combination... In the case of a combination, the second LLR mapping table is generated based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information; and in the case where the bit value corresponding to the second logic data page and the bit value corresponding to the third logic data page have a third combination, the third LLR mapping table is generated based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information. A flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes: a read-only memory for storing program code; a cache memory; and a microprocessor for executing the program code to control access to the flash memory module; wherein the microprocessor is used to perform the following operations: reading the flash memory module using a first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages respectively. A first logical data page of a physical data page in the flash memory module is used to obtain a first read information, a second read information, and a third read information, respectively. The first read information, the second read information, and the third read information are decoded to generate decoded data of the first logical data page. A log-likelihood ratio is generated based on the decoded data of the first logical data page, the first read information, the second read information, and the third read information. A ratio (LLR) mapping table is used for subsequent reading and decoding of other logical data pages; wherein the physical data page contains multiple memory units, each memory unit is used to store multiple bits, each memory unit has multiple states, and the multiple states are used to indicate different combinations of the multiple bits; and the first read information contains a hard bit of each memory unit, the second read information contains a first soft bit of each memory unit, and the third read information contains a second soft bit of each memory unit; and according to the The step of generating the LLR mapping table from the decoded data, the first read information, the second read information, and the third read information of the first logical data page includes: counting 16 combinations of the decoded data, the hard bits, the first soft bits, and the second soft bits based on the decoded data, the first read information, the second read information, and the third read information of the first logical data page, to calculate the number of each combination of the decoded data, the hard bits, the first soft bits, and the second soft bits, for calculating the LLR mapping table. As described in claim 5 of the flash memory controller, the first set of critical voltages includes at least a first critical voltage, a second critical voltage, and a third critical voltage; the positively adjusted first set of critical voltages includes the first critical voltage plus an adjustment value, the second critical voltage plus the adjustment value, and the third critical voltage plus the adjustment value; and the negatively adjusted first set of critical voltages includes the first critical voltage minus the adjustment value, the second critical voltage minus the adjustment value, and the third critical voltage minus the adjustment value. A flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes: a read-only memory for storing program code; a cache memory; and a microprocessor for executing the program code to control access to the flash memory module; wherein the microprocessor is used to perform the following operations: reading the flash memory module using a first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages respectively. A first logical data page of a physical data page in the flash memory module is used to obtain a first read information, a second read information, and a third read information, respectively. The first read information, the second read information, and the third read information are decoded to generate decoded data of the first logical data page. A log-likelihood ratio is generated based on the decoded data of the first logical data page, the first read information, the second read information, and the third read information. A ratio (LLR) mapping table is used for subsequent reading and decoding of other logical data pages; wherein the decoded data is a first decoded data, and the microprocessor further performs the following operations: using a second set of critical voltages to read a second logical data page of the physical data page in the flash memory module, and decoding the read information to obtain a second decoded data; using a third set of critical voltages to read a third logical data page of the physical data page in the flash memory module, and decoding the read information to obtain... The step of generating the LLR mapping table based on the decoded data of the first logical data page, the first read information, the second read information, and the third read information includes: generating at least a first LLR mapping table, a second LLR mapping table, and a third LLR mapping table based on the decoded data of the first logical data page, the first read information, the second read information, the third read information, the second decoded data of the second logical data page, and the third decoded data of the third logical data page. As described in claim 7 of the flash memory controller, the physical data page includes multiple memory units, each memory unit storing multiple bits, each memory unit having multiple states, and the multiple states indicating different combinations of the multiple bits; for each of the first set of critical voltages, two adjacent states correspond to the same bit value in the second logic data page, and also correspond to the same bit value in the third logic data page; the first set of Each critical voltage has two adjacent states whose corresponding bit values in the second logic data page and the third logic data page have different combinations; and based on the decoded data of the first logic data page, the first read information, the second read information, the third read information, the second decoded data of the second logic data page, and the third decoded data of the third logic data page, at least the first LLR mapping table and the second... The steps for creating the LLR mapping table and the third LLR mapping table include: If the bit values corresponding to the second logic data page and the bit values corresponding to the third logic data page have a first combination, generating the first LLR mapping table based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information; If the bit values corresponding to the second logic data page and the bit values corresponding to the third logic data page have a second combination, generating the first LLR mapping table based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information; and if the bit values corresponding to the second logic data page and the bit values corresponding to the third logic data page have a second combination, generating the first LLR mapping table based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information. In the case of a certain combination, the second LLR mapping table is generated based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information; and in the case where the bit value corresponding to the second logic data page and the bit value corresponding to the third logic data page have a third combination, the third LLR mapping table is generated based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information. A memory device includes: a flash memory module; and a flash memory controller for accessing the flash memory module; wherein the flash memory controller performs the following operations: reading a first logical data page of a physical data page in the flash memory module using a first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages, respectively, to obtain a... First, a second, and a third readout; the first, second, and third readouts are decoded to generate decoded data for the first logic data page; a log-likelihood ratio is generated based on the decoded data of the first logic data page, the first, second, and third readouts. A ratio (LLR) mapping table is used for subsequent reading and decoding of other logical data pages; wherein the physical data page contains multiple memory units, each memory unit is used to store multiple bits, each memory unit has multiple states, and the multiple states are used to indicate different combinations of the multiple bits; and the first read information contains a hard bit of each memory unit, the second read information contains a first soft bit of each memory unit, and the third read information contains a second soft bit of each memory unit; and according to the The step of generating the LLR mapping table from the decoded data, the first read information, the second read information, and the third read information of the first logical data page includes: counting 16 combinations of the decoded data, the hard bits, the first soft bits, and the second soft bits based on the decoded data, the first read information, the second read information, and the third read information of the first logical data page, to calculate the number of each combination of the decoded data, the hard bits, the first soft bits, and the second soft bits, for calculating the LLR mapping table. The memory device as described in claim 9, wherein the first set of critical voltages includes at least a first critical voltage, a second critical voltage, and a third critical voltage; the positively adjusted first set of critical voltages includes the first critical voltage plus an adjustment value, the second critical voltage plus the adjustment value, and the third critical voltage plus the adjustment value; and the negatively adjusted first set of critical voltages includes the first critical voltage minus the adjustment value, the second critical voltage minus the adjustment value, and the third critical voltage minus the adjustment value. A memory device includes: a flash memory module; and a flash memory controller for accessing the flash memory module; wherein the flash memory controller performs the following operations: reading a first logical data page of a physical data page in the flash memory module using a first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages, respectively, to obtain a... First, a second, and a third readout; the first, second, and third readouts are decoded to generate decoded data for the first logic data page; a log-likelihood ratio is generated based on the decoded data of the first logic data page, the first, second, and third readouts. A ratio (LLR) mapping table is used for subsequent reading and decoding of other logical data pages; wherein the decoded data is a first decoded data, and the flash memory controller further performs the following operations: using a second set of critical voltages to read a second logical data page of the physical data page in the flash memory module, and decoding the read information to obtain a second decoded data; using a third set of critical voltages to read a third logical data page of the physical data page in the flash memory module, and decoding the read information to obtain a second decoded data. The step of obtaining a third decoded data; and generating the LLR mapping table based on the decoded data of the first logic data page, the first read information, the second read information, and the third read information includes: generating at least a first LLR mapping table, a second LLR mapping table, and a third LLR mapping table based on the decoded data of the first logic data page, the first read information, the second read information, the third read information, the second decoded data of the second logic data page, and the third decoded data of the third logic data page. As described in claim 11, the memory device, wherein the physical data page includes multiple memory units, each memory unit being used to store multiple bits, each memory unit having multiple states, and the multiple states being used to indicate different combinations of the multiple bits; for each of the first set of critical voltages, two adjacent states correspond to the same bit value in the second logical data page, and also correspond to the same bit value in the third logical data page; the first set of critical voltages... Each critical voltage in the voltage has two adjacent states whose corresponding bit values in the second logic data page and the third logic data page have different combinations; and based on the decoded data of the first logic data page, the first read information, the second read information, the third read information, the second decoded data of the second logic data page, and the third decoded data of the third logic data page, at least the first LLR mapping table and the second LLR mapping table are generated. The steps for creating the LR mapping table and the third LLR mapping table include: If the bit values corresponding to the second logic data page and the bit values corresponding to the third logic data page have a first combination, generating the first LLR mapping table based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information; if the bit values corresponding to the second logic data page and the bit values corresponding to the third logic data page have a second combination... In the case of a combination, the second LLR mapping table is generated based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information; and in the case where the bit value corresponding to the second logic data page and the bit value corresponding to the third logic data page have a third combination, the third LLR mapping table is generated based on the decoded data of that segment of the first logic data page, the first read information, the second read information, and the third read information.