TWI658595B - Semiconductor structure and method for forming the same - Google Patents

Abstract

An embodiment of the present invention relates to a semiconductor structure including a semiconductor substrate, a gate trench located in the semiconductor substrate, a gate dielectric layer disposed on a sidewall of the gate trench, and a gate trench below the gate trench. A gate trench extension, an insulation post disposed in the gate trench extension, a gate electrode disposed in and on the insulation post, and a semiconductor substrate buried on both sides of the gate trench A doped well region, and a source region in a semiconductor substrate disposed on the doped well region.

Description

Semiconductor structure and forming method thereof

Embodiments of the present invention relate to a semiconductor structure, and more particularly, to a semiconductor structure of a power MOSFET.

Semiconductor devices have been widely used in various electronic products, such as personal computers, mobile phones, and digital cameras ... Semiconductor devices are usually manufactured by sequentially depositing an insulating layer or a dielectric layer material, a conductive layer material, and a semiconductor substrate material on a semiconductor substrate, and then patterning various material layers formed by a lithography process, so that the semiconductor substrate is formed on the semiconductor substrate. Circuit parts and components are formed thereon.

Among them, the power metal-oxide half field effect transistor is a field effect transistor that can be widely used in analog circuits and digital circuits. It has the advantages of small power dissipation at the input end and fast switching speed, so it is highly anticipated in the development of power components. .

The breakdown voltage of a power metal-oxide half field effect transistor is one of its important parameters. However, according to the existing technology, increasing the breakdown voltage usually causes the on resistance and threshold voltage of the transistor to increase, which is not beneficial. Operation of semiconductor components. Therefore, today's power metal-oxygen half-time There are still many problems with efficiency transistors that need to be improved.

An embodiment of the present invention provides a semiconductor structure including a semiconductor substrate, a gate trench in the semiconductor substrate, a gate dielectric layer disposed on a sidewall of the gate trench, and a gate below the gate trench. The gate trench extension, an insulating post disposed in the gate trench extension, a gate electrode disposed in the gate trench and on the insulating post, and a semiconductor substrate buried in both sides of the gate trench. A well region is a source region in a semiconductor substrate disposed on a doped well region.

An embodiment of the present invention also provides a method for forming a semiconductor structure, which includes providing a semiconductor substrate, forming a gate trench in the semiconductor substrate, forming a gate dielectric layer on a sidewall of the gate trench, and etching back the gate. The trench is formed to form a gate trench extension below the gate trench, an insulating post is formed in the gate trench extension, a gate electrode is formed in the gate trench and above the insulating post, and a doped well is formed. The semiconductor substrate is located on both sides of the gate trench, and the source substrate is formed in the semiconductor substrate on the doped well region.

100‧‧‧ semiconductor substrate

102‧‧‧Epimorph Region

104‧‧‧Gate Trench

106‧‧‧ first conformal dielectric layer

108‧‧‧ second conformal dielectric layer

108A, 108B, 108C‧Parts of the second conformal dielectric layer

110‧‧‧ extension of gate trench

112‧‧‧Insulation post

114‧‧‧Gate electrode

116‧‧‧ doped well area

118‧‧‧Source area

120‧‧‧ Insulation

122‧‧‧Source contact

124‧‧‧ Drain contact

Part of 126‧‧‧ semiconductor substrate

128‧‧‧ first dielectric layer

130‧‧‧second dielectric layer

200‧‧‧ reverse doped region

300‧‧‧ Reduced surface electric field doped region

10, 20, 30‧‧‧ semiconductor structure

T‧‧‧thickness

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are for illustration only. In fact, the size of the components may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.

Figures 1A-1L are a series of cross-sectional views for explaining the manufacturing process of a semiconductor structure according to some embodiments of the present invention.

Figures 2-3 are cross-sectional views of semiconductor structures according to some other embodiments of the present invention.

Many different implementation methods or examples are disclosed below to implement the different features of the embodiments of the present invention. Specific elements and their arrangements are described below to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration, and the scope of the embodiments of the present invention should not be limited by this. For example, it is mentioned in the description that the first feature is formed on the second feature, which includes the embodiment in which the first feature and the second feature are in direct contact, and also includes the other between the first feature and the second feature. An embodiment of a feature, that is, the first feature and the second feature are not in direct contact. It should be understood that the additional operation steps may be implemented before, during or after the method, and in other embodiments of the method, part of the operation steps may be replaced or omitted.

In the semiconductor structure of the embodiment of the present invention, a gate trench extension is formed under the gate trench, and then an insulating pillar is formed in the gate trench extension. The above-mentioned insulating pillar enables the semiconductor structure to maintain a low on-resistance. Value and the threshold voltage while increasing its breakdown voltage.

FIG. 1A illustrates the initial steps of this embodiment. First, a semiconductor substrate 100 is provided, which may include an epitaxial region 102 and a portion 126 of the semiconductor substrate 100 below it. In some embodiments, the doping concentration of the semiconductor substrate 100 of the portion 126 (e.g.: 1E18-1E20cm ^-3) is greater than the doping concentration of the epitaxial region 102 (e.g.: 1E15-1E17cm ^-3). For example, the semiconductor substrate 100 may include silicon. In some other embodiments, the semiconductor substrate 100 may be other element semiconductors, such as germanium; compound semiconductors, such as: silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (indium arsenide (InAs) or indium phosphide (InP); alloy semiconductors, such as: silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP) ) Or gallium indium phosphide (GaInP). The semiconductor substrate 100 may include an epitaxial region 102. For example, vapor phase epitaxy (VPE), molecular-beam epitaxy (MBE), and organic metal vapor deposition may be used. The epitaxial region 102 is formed by metal organic chemical vapor deposition (MOCVD), a combination of the above, or other suitable methods. For example, the semiconductor substrate 100 may be an N-type substrate or a P-type substrate. For convenience, this embodiment is described by using an N-type field effect transistor formed in the N-type semiconductor substrate 100 as an example. It should be generally understood by those skilled in the art that in some other embodiments of the present invention, a P-type field effect transistor may be formed in a P-type semiconductor substrate.

Next, as shown in FIG. 1A, a first dielectric layer 128 and a second dielectric layer 130 are formed on the epitaxial region 102. For example, the first dielectric layer 128 may include silicon oxide, other suitable dielectric materials, or a combination thereof. The first dielectric layer 128 may be formed using a chemical vapor deposition (CVD) method, a thermal oxidation method, other suitable methods, or a combination thereof. For example, the second dielectric layer 130 may include silicon nitride, other suitable dielectric materials, or a combination thereof. In some embodiments, the second dielectric layer 130 may be formed by low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), other suitable methods, or a combination thereof.

In some embodiments, the first dielectric layer 128 may be a pad oxide layer formed of an oxide, and the second dielectric layer 130 may be a pad nitride layer formed of a nitride ( pad nitride layer).

Next, referring to FIG. 1B, a gate trench 104 is formed in the epitaxial region 102 of the semiconductor substrate 100. For example, a patterned photoresist and / or a patterned hard mask (not shown) having an opening pattern corresponding to the gate trench 104 may be formed on the first dielectric layer 128 and the second dielectric layer 130 first. And then use the patterned photoresist and / or patterned hard mask as the etching mask to perform one or more etching processes to form the second dielectric layer 130 and the first dielectric layer 128 corresponding to the above. An opening of the gate trench 104. Then, the patterned photoresist and / or patterned hard mask is removed, and then the second dielectric layer 130 and the first dielectric layer 128 are used as an etching mask to perform an etching process to form a gate in the epitaxial region 102.极 槽 104。 The pole trench 104. For example, the above-mentioned etching process may be dry etching (eg, anisotropic plasma etching), wet etching, or a combination thereof. In some embodiments using dry etching, it is beneficial to form a gate trench with a high aspect ratio. 104.

Next, referring to FIG. 1C, a first conformal dielectric layer 106 is formed in the gate trench 104 and covers a sidewall and a bottom of the gate trench 104. For example, the first conformal dielectric layer 106 may include silicon oxide, silicon oxynitride, lanthanum oxide (La ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), hafnium oxynitride. (HfON), zirconia (ZrO ₂ ), tantalum silicon oxide (TaSiO _x ), other suitable materials, or a combination thereof. Atomic-layer deposition (ALD), molecular beam deposition (MBD), chemical vapor deposition (CVD), thermal oxidation, other appropriate methods, or the above may be used The combination forms the first conformal dielectric layer 106. It should be noted that the first conformal dielectric layer 106 covering the sidewall of the gate trench 104 will serve as the gate dielectric layer of the semiconductor structure in the future. It can be selected according to the characteristics required by the field effect transistor. Thickness T (for example: 50-800Å).

Next, as shown in FIG. 1C, a second conformal dielectric layer 108 is formed on the first conformal dielectric layer 106, which may have a portion 108A on the second dielectric layer 130 and a gate trench. A portion 108B on the sidewall of the trench 104 and a portion 108C on the bottom of the gate trench 104. In some embodiments, the thickness T 'of the second conformal dielectric layer 108 may be 3 to 10 m. For example, the second conformal dielectric layer 108 may include silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the second conformal dielectric layer 108 may be formed by low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), other suitable methods, or a combination thereof.

Next, as shown in FIG. 1D, an etching process (for example, a dry etching process) is performed to remove portions 108A and 108C of the second conformal dielectric layer 108 and expose the first common layer covering the bottom of the gate trench 104. A portion of the dielectric layer 106 is shaped. As shown in FIG. 1D, the above-mentioned etching process does not substantially remove or only removes a portion 108B of the second conformal dielectric layer 108. Therefore, after the above-mentioned etching process, the sidewalls of the gate trench 104 still remain. Portion 108B of the second conformal dielectric layer 108. In some embodiments, the second conformal dielectric layer 108 may include a material different from the first conformal dielectric layer 106 (eg, the first conformal dielectric layer is an oxide and the second conformal dielectric layer is Nitride), so in the subsequent etching step, the portion 108B of the second conformal dielectric layer 108 may be used as an etching mask to etch the first conformal dielectric layer 106 and the semiconductor substrate 100 to form a gate trench. The extension portion 110 (shown in FIG. 1E) will be described in detail later.

Next, referring to FIG. 1E, the gate trench 104 is etched back to form a gate trench extension 110 below the gate trench 104. Following the foregoing, in some embodiments In the process, one or more etching processes may be performed by using the portion 108B of the remaining second conformal dielectric layer 108 as an etching mask to sequentially etch the first conformal dielectric layer 106 and the bottom of the gate trench 104. Since the gate trench extension 110 is formed in the epitaxial region 102 of the semiconductor substrate 100, an additional photomask is not needed and cost can be saved. For example, the above-mentioned etching process may be dry etching (for example, anisotropic plasma etching), wet etching, or a combination thereof. In some embodiments, as shown in FIG. 1E, the width of the gate trench extension 110 is smaller than the width of the gate trench 104.

Next, referring to FIG. 1F, an insulating pillar 112 is formed in the extending portion 110 of the gate trench. For example, the insulating pillar 112 may include an oxide, a nitride, an oxynitride, other suitable materials, or a combination thereof. In some embodiments, a local oxidation process is performed to form an oxide insulation pillar 112 in the gate trench extension 110. For example, when performing the above-mentioned local oxidation process, the portion 108B of the remaining second conformal dielectric layer 108 can be used as an oxidation mask to prevent the thickness of the first conformal dielectric layer 106 from being substantially oxidized. The change in thickness cannot maintain the proper thickness selected according to the required characteristics of the field effect transistor.

Next, referring to FIG. 1G, an etching process is performed to remove the second dielectric layer 130, the second conformal dielectric layer 108, the first dielectric layer 128, and the first conformal dielectric outside the gate trench 104. Layer 106. For example, the above-mentioned etching process may be dry etching (for example, anisotropic plasma etching), wet etching, or a combination thereof. In some embodiments, the second conformal dielectric layer 108 can be removed by a wet etching process, and the second dielectric layer 130, the first dielectric layer 128, and the gate trench 104 can be removed by a dry etching process. First conformal dielectric layer 106. In some other embodiments, a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP), and a removable material such as photoresist may be filled in the gate trench 104 to protect the first conformal dielectric layer 106 in the gate trench 104 and the extension 110 of the gate trench. Insulation post 112.

Next, referring to FIG. 1H, a gate electrode 114 is formed in the gate trench 104. For example, the gate electrode 114 may include polycrystalline silicon, a metal material and / or a silicide thereof, other suitable conductive materials, or a combination thereof. In some embodiments, it can be filled by chemical vapor deposition, sputtering, electroplating, resistance heating evaporation, electron beam evaporation (EB), or other suitable deposition methods. An appropriate conductive material is inserted into the gate trench 104 to form the gate electrode 114. In addition, after the conductive material is deposited, a chemical mechanical polishing process or an etch-back process may be performed as required to remove the excess conductive material outside the gate trench 104.

Next, as shown in FIG. 11, a doped well region 116 is formed in the semiconductor substrate 100 on both sides of the gate trench 104. In this embodiment, the semiconductor structure 10 formed subsequently is an N-type field effect transistor, so the doped well region 116 may be a P-type doped region. For example, boron ions, indium ions, or boron difluoride ions (BF ₂ ⁺ ) can be implanted in the semiconductor substrate 100 on both sides of the gate trench 104 to form a P-type doping concentration of 1E15-1E18cm ^-3 . Doped well region 116. In other embodiments, the subsequently formed semiconductor structure is a P-type field effect transistor, so the doped well region 116 may be an N-type doped region. For example, phosphorus ions or arsenic ions can be implanted in the semiconductor substrate 100 on both sides of the gate trench 104 to form an N-type doped well region 116 having a doping concentration of 1E15-1E18cm ^-3 .

Next, a source region 118 is formed in the semiconductor substrate 100 on the doped well region 116 to form a semiconductor structure 10. In this embodiment, the semiconductor structure 10 is an N-type field effect transistor, so the source region 118 may be an N-type doped region. For example, phosphorus ions or arsenic ions can be implanted in the semiconductor substrate 100 on the doped well region 116 to form an N-type source region 118 with a doping concentration of 1E19-1E21Ecm ^-3 . In other embodiments, the formed semiconductor structure is a P-type field effect transistor, so the source region 118 may be a P-type doped region. For example, boron ions, indium ions, or boron difluoride ions (BF ₂ ⁺ ) can be implanted in the semiconductor substrate 100 on the doped well region 116 to form a P-type source with a doping concentration of 1E19-1E21cm ^-3 . District 118.

As shown in FIG. 1I, the semiconductor structure 10 according to the embodiment of the present invention includes an insulating pillar 112 formed under the gate electrode 114, and the breakdown voltage thereof can be increased without affecting its on-resistance and threshold voltage.

Next, as shown in FIG. 1J, an insulating layer 120 and a source contact 122 may be formed on the semiconductor substrate 100 as appropriate. In some embodiments, the source contact 122 may be electrically connected to the source 118 and the doped well region 116 to prevent the parasitic bipolar transistor from causing conduction behavior that affects device performance. For example, the source contact 122 may include a metal material (eg, tungsten, aluminum, or copper) or other suitable conductive materials.

It should be noted that the semiconductor substrate 100 under the insulating pillar 112 may serve as a drain region of the semiconductor structure 10. In addition, as shown in FIG. 1J, a drain contact 124 may be formed under the semiconductor substrate 100 as appropriate. For example, the drain contact 124 may include a metallic material (eg, tungsten, aluminum, or copper) or other suitable conductive materials.

In addition, although in this embodiment, the insulating post 112 is formed in the extension 110 of the gate trench, in some other embodiments, as shown in FIG. 1K, the insulating post 112 may be further formed on the gate. The bottom of the trench 104 can further relieve the electric field and extend the area of the empty region, thereby increasing the breakdown voltage of the device.

In addition, although the gate trenches 104 and the gate trench extensions 110 each have substantially straight sidewalls in this embodiment, in some other embodiments, the etching parameters can be appropriately controlled such that the gate trenches Each of the slot 104 and the extension portion 110 of the gate trench may have a curved side wall that is tapered downward (as shown in FIG. 1L), so as to avoid the problem of uneven electric field distribution.

Various modifications of the embodiments of the present invention are described below. For convenience of explanation, similar component symbols will be used to indicate similar components. In addition, repeated reference numerals or signs may be used in different embodiments. These repetitions are merely for simply and clearly describing the embodiments of the present invention, and do not represent that there must be a specific relationship between the different embodiments and / or structures discussed.

Next, please refer to FIG. 2, which illustrates a semiconductor structure 20 according to another embodiment of the present invention. The difference between the semiconductor structure 20 and the semiconductor structure 10 is that it further includes a reversely doped region 200 surrounding the insulating pillar 112, which can further increase the breakdown voltage. The reversely doped region 200 may have the same conductivity type as the semiconductor substrate 100, and its doping concentration is lower than that of the epitaxial region 102 of the semiconductor substrate 100 (for example, the doping concentration of the epitaxial region 102 of the semiconductor substrate 100 and The ratio of the doping concentration of the reversely doped region 200 is 2-8, preferably 4-6). For example, after the extension portion 110 of the gate trench is formed (as shown in FIG. 1E) and before the insulating pillar 112 is formed, a portion 108B of the second conformal dielectric layer 108 and the second dielectric may be used. The layer 130 is used as a mask to perform the implantation process to form the reverse doped region 200. In some embodiments where the semiconductor structure 20 is an N-type field effect transistor, a P-type dopant (eg, boron ion, indium ion, or boron difluoride ion (BF ₂ ⁺ )) may be implanted around the insulating pillar 112. In a portion of the epitaxial region 102 of the N-type semiconductor substrate 100, the doping concentration of the portion of the epitaxial region 102 of the N-type semiconductor substrate 100 around the insulating pillar 112 is reduced to form a reverse doped region 200. In some embodiments where the semiconductor structure 20 is a P-type field effect transistor, an N-type dopant (eg, phosphorus ion or arsenic ion) may be implanted on the epitaxial region 102 of the P-type semiconductor substrate 100 around the insulating pillar 112. In one part, the doping concentration of a portion of the epitaxial region 102 of the P-type semiconductor substrate 100 around the insulating pillar 112 is reduced to form a reversely doped region 200.

Next, please refer to FIG. 3, which illustrates a semiconductor structure 30 according to another embodiment of the present invention. The difference between the semiconductor structure 30 and the semiconductor structure 10 is that it further includes a reduced surface field doped region 300 formed in the semiconductor substrate 100 on both sides of the insulating pillar 112, so that the breakdown voltage can be further increased. The aforementioned reduced surface electric field doped region 300 may have a conductivity type opposite to that of the semiconductor substrate 100. For example, before the step of forming the source contact 122, a dopant can be implanted in the semiconductor substrate 100 on both sides of the insulating pillar 112 to form a surface area doped region 300. In some embodiments where the semiconductor structure 30 is an N-type field-effect transistor, a P-type dopant (eg, boron ion, indium ion, or boron difluoride ion (BF ₂ ⁺ )) can be implanted on the insulating pillar 112. In the N-type semiconductor substrate 100 on the side, a P-type reduced surface electric field doped region 300 is formed. In some embodiments where the semiconductor structure 30 is a P-type field effect transistor, an N-type dopant (eg, phosphorus ion or arsenic ion) may be implanted in the P-type semiconductor substrate 100 on both sides of the insulating pillar 112 to form N The reduced surface electric field doped region 300.

To sum up, the semiconductor structure of the embodiment of the present invention forms an insulating pillar under the gate electrode, which can increase its breakdown voltage. In addition, the semiconductor structure according to the embodiment of the present invention may further include the aforementioned reversely doped region and / or lower the surface electric field doped region to further increase its breakdown voltage.

The foregoing text outlines the features of many embodiments, enabling Those having ordinary knowledge in the domain can better understand the embodiments of the present invention from various aspects. Those with ordinary knowledge in the technical field should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention, so as to achieve the same purpose and / or achieve the implementation described here. Examples have the same advantages. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Any person with ordinary knowledge in the technical field can make any changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention shall be defined by the scope of the attached patent application. Whichever comes first.

Claims (18)

A semiconductor structure includes: a semiconductor substrate; a gate trench in the semiconductor substrate; a gate dielectric layer disposed on a sidewall of the gate trench; and a gate trench extension in the gate trench. Under the gate trench; an insulating post disposed in the gate trench extension; a gate electrode disposed in the gate trench and above the insulating post, wherein one of the gate electrodes has a width Larger than one width of the insulating pillar; a doped well region buried in a semiconductor substrate on both sides of the gate trench; a source region placed in the semiconductor substrate on the doped well region; and A doping region is formed in the semiconductor substrate and surrounds the insulating pillar. The semiconductor structure described in item 1 of the scope of patent application, further includes: a drain region disposed in the semiconductor substrate under the insulating pillar. The semiconductor structure according to item 1 of the scope of patent application, wherein the width of the gate trench extension is smaller than the width of the gate trench. The semiconductor structure according to item 1 of the patent application scope, wherein the semiconductor substrate and the source region have a first conductivity type, and the doped well region has a second conductivity type opposite to the first conductivity type. state. The semiconductor structure according to item 4 of the scope of patent application, wherein the first conductivity type is n-type and the second conductivity type is p-type. The semiconductor structure described in item 4 of the scope of patent application, further includes: a reduced surface field (reduced surface field) doped region formed in the semiconductor substrate on both sides of the insulating pillar and having the second conductivity type. The semiconductor structure according to item 4 of the scope of patent application, wherein the reversely doped region has the same first conductivity type as the semiconductor substrate. The semiconductor structure according to item 7 of the application, wherein the doping concentration of the reversely doped region is lower than the doping concentration of the semiconductor substrate. The semiconductor structure according to item 1 of the patent application scope, wherein the insulating pillar comprises an oxide, a nitride, an oxynitride, or a combination thereof. The semiconductor structure according to item 1 of the scope of patent application, wherein the insulating post is further disposed at the bottom of the gate trench. A method for forming a semiconductor structure includes: providing a semiconductor substrate; forming a gate trench in the semiconductor substrate; forming a gate dielectric layer on a sidewall of the gate trench; and forming the gate dielectric After the step of layering, the gate trench is etched back to form a gate trench extension under the gate trench; an insulating post is formed in the gate trench extension; a gate electrode is formed in the gate trench; A gate trench and above the insulating pillar; forming a doped well region in a semiconductor substrate on both sides of the gate trench; and forming a source region in the semiconductor substrate on the doped well region. The method for forming a semiconductor structure according to item 11 of the scope of patent application, wherein the step of forming the gate trench extension includes forming a first conformal dielectric layer, wherein the first conformal dielectric layer covers the A sidewall and a bottom of the gate trench; forming a second conformal dielectric layer on the first conformal dielectric layer, wherein the second conformal dielectric layer exposes a first layer covering the bottom of the gate trench A portion of a conformal dielectric layer; and using the second conformal dielectric layer as an etching mask to etch the first conformal dielectric layer and the semiconductor substrate to form the gate trench extension at the gate Under the trench. The method for forming a semiconductor structure according to item 12 of the application, wherein the insulating pillar comprises an oxide, a nitride, an oxynitride, or a combination thereof. The method for forming a semiconductor structure according to item 13 of the scope of the patent application, wherein the step of forming the oxide includes: performing a local oxidation process using the second conformal dielectric layer as a mask. The method for forming a semiconductor structure according to item 12 of the patent application scope further comprises: removing the second conformal dielectric layer after forming the insulating pillar and before forming the gate electrode. The method for forming a semiconductor structure according to item 12 of the scope of patent application, further comprising: forming a reversely doped region in the semiconductor substrate and surrounding the insulating pillar, wherein the reversely doped region has the same structure as the semiconductor. One of the substrates has a first conductivity type, and a doping concentration of the reversely doped region is lower than a doping concentration of the semiconductor substrate. The method for forming a semiconductor structure according to item 16 of the scope of the patent application, wherein the step of forming the reversely doped region includes: using the second conformal dielectric layer as a mask to perform a implantation process to inject a doped The substrate is embedded in a portion of the semiconductor substrate surrounding the insulating pillar; wherein the dopant has a second conductivity type opposite to the first conductive type of the semiconductor substrate, so that the semiconductor substrate surrounds the portion of the insulating pillar The doping concentration is reduced to form the reversely doped region. The method for forming a semiconductor structure according to item 17 of the scope of patent application, wherein the implantation process is performed before forming the insulating pillar.