TWI658585B - Semiconductor structures and fabrication method thereof - Google Patents

Abstract

The present disclosure provides a semiconductor structure including: a substrate including a first region and a second region; a first trench formed in the substrate, located in the first region, and surrounded by a first protruding structure; A second trench is formed in the substrate, is located in the second region, and is surrounded by a second protruding structure, wherein the depth of the second trench is greater than the depth of the first trench; a first silicon oxide layer Formed on top of the first protruding structure; a second silicon oxide layer formed on top of the second protruding structure; a first dielectric layer formed on the first silicon oxide layer; and a second dielectric An electrical layer is formed on the second silicon oxide layer, wherein a thickness of the first dielectric layer is greater than a thickness of the second dielectric layer.

Description

Semiconductor structure and manufacturing method thereof

The disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure having a silicon nitride layer with different thicknesses in a low-voltage region and a high-voltage region, and a method for manufacturing the same.

For high voltage devices, it is necessary to make deeper trenches to effectively increase their breakdown voltage. However, for low-voltage (low-voltage) components, because the interface of the low-voltage components is shallow, if the groove depth is deep at this time, the subsequent implantation process will necessarily be implanted for the deeper position of the substrate. However, The process conditions for such deep implantation are not easy to control, and because the deep trench filling process is not easy to perform, the trench openings between low-voltage components must be further enlarged. It has been shown that the single-depth trench structure no longer meets the requirements of high and low voltage component integration processes. However, currently the industry often uses methods for making trenches with different depths, which can only be achieved with multiple process steps (multiple yellow light and multiple etchings), which is quite costly.

Therefore, it is desirable to develop a simple semiconductor structure and related manufacturing method that can simultaneously have trenches with different depths in the low-voltage region and the high-voltage region.

According to an embodiment of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes: a substrate including a first region and a second region; a first trench formed in the substrate, located in the first region, surrounded by a first protruding structure; a second trench A trench is formed in the substrate, is located in the second region, and is surrounded by a second protruding structure, wherein the depth of the second trench is greater than the depth of the first trench; a first silicon oxide layer is formed on the substrate; On top of the first protruding structure; a second silicon oxide layer formed on top of the second protruding structure; a first dielectric layer formed on the first silicon oxide layer; and a second dielectric layer formed On the second silicon oxide layer, a thickness of the first dielectric layer is greater than a thickness of the second dielectric layer.

According to some embodiments, the substrate is a silicon substrate.

According to some embodiments, the first region is a region where a low-voltage element is provided, and the second region is a region where a high-voltage element is provided.

According to some embodiments, the first trench is an electrical isolation between low-voltage components, and the second trench is an electrical isolation between high-voltage components.

According to some embodiments, the difference between the depth of the first trench and the depth of the second trench is generally between 500 angstroms and 5,000 angstroms.

According to some embodiments, the first dielectric layer and the second dielectric layer include silicon nitride or silicon oxide.

According to some embodiments, when the first dielectric layer and the second dielectric layer are silicon nitride, the first silicon oxide layer further includes a portion of a sidewall extending to cover the first protruding structure, and the second silicon oxide layer It further includes a portion of the side wall extending to cover the second protruding structure.

According to some embodiments, the radius of curvature of the connecting portion between the top of the second protruding structure and the side wall is greater than the top and side of the first protruding structure. The radius of curvature of the connecting part of the wall.

According to some embodiments, the difference between the thickness of the first dielectric layer and the thickness of the second dielectric layer is generally between 300 angstroms and 1,000 angstroms.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. The manufacturing method includes: providing a substrate, the substrate including a first region and a second region; forming a silicon oxide layer on the substrate; forming a dielectric layer on the silicon oxide layer, wherein the silicon layer is located on the substrate; The thickness of the dielectric layer in the first region is greater than the thickness of the dielectric layer in the second region of the substrate; and an etching process is performed to etch the dielectric layer and pass through the silicon oxide layer to the substrate A first trench is formed in the first region of the substrate, and is surrounded by a first protruding structure; a second trench is formed in the second region of the substrate, and a second protrusion is formed Surrounded by a structure, wherein the depth of the second trench is greater than the depth of the first trench, wherein the silicon oxide layer on top of the first protruding structure is defined as a first silicon oxide layer located on the second protruding structure The silicon oxide layer on top of it is defined as a second silicon oxide layer.

According to some embodiments, the etching gas in the above-mentioned etching process includes sulfur hexafluoride, a combination of methane and nitrogen, or a combination of sulfur hexafluoride, methane, nitrogen, and oxygen.

According to some embodiments, the etching selectivity ratio between the dielectric layer and the substrate is generally between 1: 4 and 1:10.

According to some embodiments, when the dielectric layer is silicon nitride, an oxidation process is further performed, so that the first silicon oxide layer extends to cover part of the sidewall of the first protruding structure, and the second silicon oxide layer extends. Covering part of the side wall of the second protruding structure.

The present disclosure produces silicon nitride layers with different thicknesses in the low-voltage region and the high-voltage region (that is, a thicker silicon nitride layer in the low-voltage region and a thinner silicon nitride layer in the high-voltage region), and then cooperates with A single etching step with specific etching conditions (such as the silicon nitride layer-to-silicon substrate etching selection ratio) can simultaneously obtain shallower trenches in the low-voltage region and deeper trenches in the high-voltage region.

In addition, during the subsequent oxidation process (can be performed before or after the chemical mechanical polishing (CMP) process), the silicon nitride layer in the low voltage region is thicker and the silicon nitride layer in the high voltage region is thinner, which makes the low voltage region trench The rounding effect is relatively insignificant, and the grooves in the high-voltage region show a more pronounced rounding effect. The different degrees of rounding effects have different contributions to the low-voltage and high-voltage components. For low-voltage components, the lower rounding effect can maintain the effective width of the element channel, and get a high saturation-region drain current (Idsat), while for high-voltage components, a higher roundness The effect can improve the uniformity of related structures in the whole wafer and increase the matching of components.

Therefore, the present disclosure can simultaneously improve the structural and electrical advantages of low-voltage components and high-voltage components while making trenches of different depths in the low-voltage area and the high-voltage area.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows.

10‧‧‧Semiconductor Structure

12‧‧‧ substrate

14‧‧‧first groove

16‧‧‧The first prominent structure

18‧‧‧Second Groove

20‧‧‧Second prominent structure

22‧‧‧ First silicon oxide layer

24‧‧‧Second silicon oxide layer

25‧‧‧Silicon oxide layer

26‧‧‧First dielectric layer

28‧‧‧Second dielectric layer

29‧‧‧ Dielectric layer

30‧‧‧ the first area of the substrate

32‧‧‧ the second area of the substrate

34‧‧‧ the top of the first protruding structure

36‧‧‧ the top of the second protruding structure

38‧‧‧patterned photoresist layer

40‧‧‧ sidewall of the first protruding structure

42‧‧‧ the side wall of the second protruding structure

44‧‧‧ the connection between the top of the first protruding structure and the side wall

46‧‧‧ the connection between the top of the second protruding structure and the side wall

H1‧‧‧ Depth of the first groove

H2‧‧‧ Depth of second trench

R1‧‧‧ the radius of curvature of the connecting portion between the top of the first protruding structure and the side wall

R2 ‧‧‧ the radius of curvature of the connecting portion between the top of the second protruding structure and the side wall

T1‧‧‧Thickness of the first dielectric layer

T2‧‧‧thickness of the second dielectric layer

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure; and FIGS. 2A-2E are cross-sectional schematic views of a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure.

FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure; and FIGS. 4A-4E are cross-sectional schematic views of a method of manufacturing a semiconductor structure according to an embodiment of the disclosure.

Referring to FIG. 1, a semiconductor structure 10 is provided according to an embodiment of the disclosure. FIG. 1 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 1, in this embodiment, the semiconductor structure 10 includes a substrate 12, a first trench 14, a first protruding structure 16, a second trench 18, a second protruding structure 20, and a first silicon oxide layer 22. , A second silicon oxide layer 24, a first dielectric layer 26, and a second dielectric layer 28. The substrate 12 includes a first region 30 and a second region 32. The first trench 14 is formed in the substrate 12, is located in the first region 30, and is surrounded by the first protruding structure 16. The second trench 18 is formed in the substrate 12, is located in the second region 32, and is surrounded by the second protruding structure 20. It is worth noting that the depth H2 of the second trench 18 is greater than the depth H1 of the first trench 14. The first silicon oxide layer 22 is formed on the top 34 of the first protruding structure 16. A second silicon oxide layer 24 is formed on the top 36 of the second protruding structure 20. A first dielectric layer 26 is formed on the first silicon oxide layer 22. A second dielectric layer 28 is formed on the second silicon oxide layer 24. It is worth noting that the thickness T1 of the first dielectric layer 26 is greater than the thickness T2 of the second dielectric layer 28.

In some embodiments, the substrate 12 may be a silicon substrate.

In some embodiments, the first region 30 may be a region provided with a low voltage element, and the second region 32 may be a region provided with a high voltage element.

In some embodiments, the first trench 14 may be electrical isolation between low-voltage components, and the second trench 18 may be electrical isolation between high-voltage components.

In some embodiments, the difference between the depth H1 of the first trench 14 and the depth H2 of the second trench 18 is generally between 500 angstroms and 5,000 angstroms.

In some embodiments, the first dielectric layer 26 and the second dielectric layer 28 may include silicon nitride or silicon oxide.

In this embodiment, the first dielectric layer 26 and the second dielectric layer 28 are silicon oxide.

In some embodiments, the difference between the thickness T1 of the first dielectric layer 26 and the thickness T2 of the second dielectric layer 28 is generally between 300 angstroms and 1,000 angstroms.

Please refer to FIGS. 2A-2E. According to an embodiment of the present disclosure, a method for manufacturing a semiconductor structure 10 is provided. 2A-2E are schematic cross-sectional views of a method for manufacturing the semiconductor structure 10.

As shown in FIG. 2A, a substrate 12 is provided. The substrate 12 includes a first region 30 and a second region 32.

In some embodiments, the substrate 12 may be a silicon substrate.

In some embodiments, the first region 30 may be a region where a low voltage element is provided, and the second region 32 may be a region where a high voltage element is provided.

After that, a silicon oxide layer 25 is formed on the substrate 12.

Thereafter, a dielectric layer 29 is formed on the silicon oxide layer 25.

In some embodiments, the dielectric layer 29 may include silicon nitride or silicon oxide.

In this embodiment, the dielectric layer 29 is silicon oxide.

Thereafter, the dielectric layer 29 is patterned to form a first dielectric layer 26 located in the first region 30 of the substrate 12 and a second dielectric layer 28 located in the second region 32 of the substrate 12. It is worth noting that the thickness T1 of the first dielectric layer 26 is greater than the thickness T2 of the second dielectric layer 28, as shown in FIG. 2B.

In some embodiments, the difference between the thickness T1 of the first dielectric layer 26 and the thickness T2 of the second dielectric layer 28 is generally between 300 angstroms and 1,000 angstroms.

Thereafter, a patterned photoresist layer 38 is formed on the first dielectric layer 26 and the second dielectric layer 28, as shown in FIG. 2C.

After that, using the patterned photoresist layer 38 as a mask, an etching process is performed to etch the first dielectric layer 26 and the second dielectric layer 28, pass through the silicon oxide layer 25 to the substrate 12, and In a region 30, a first trench 14 is formed, surrounded by a first protruding structure 16, and in a second region 32 of the substrate 12, a second trench 18 is formed, surrounded by a second protruding structure 20. It is worth noting that the depth H2 of the second trench 18 is greater than the depth H1 of the first trench 14. The silicon oxide layer on the top 34 of the first protruding structure 16 is defined as the first silicon oxide layer 22, and the silicon oxide layer on the top 36 of the second protruding structure 20 is defined as the second silicon oxide layer 24, as in the 2D As shown.

In some embodiments, the etching gas in the above-mentioned etching process may include sulfur hexafluoride, a combination of methane and nitrogen, or a combination of sulfur hexafluoride, methane, nitrogen, and oxygen.

In some embodiments, the first dielectric layer 26 and the second dielectric layer 28 The etching selection ratio of the substrate 12 is generally between 1: 4 and 1:10.

In some embodiments, the first trench 14 may be an electrical isolation between low-voltage components, and the second trench 18 may be an electrical isolation between high-voltage components.

In some embodiments, the difference between the depth H1 of the first trench 14 and the depth H2 of the second trench 18 is generally between 500 angstroms and 5,000 angstroms.

Thereafter, the patterned photoresist layer 38 is removed, as shown in FIG. 2E. So far, the fabrication of the semiconductor structure 10 of this embodiment is completed.

Referring to FIG. 3, a semiconductor structure 10 is provided according to an embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 3, in this embodiment, the semiconductor structure 10 includes a substrate 12, a first trench 14, a first protruding structure 16, a second trench 18, a second protruding structure 20, and a first silicon oxide layer 22. , A second silicon oxide layer 24, a first dielectric layer 26, and a second dielectric layer 28. The substrate 12 includes a first region 30 and a second region 32. The first trench 14 is formed in the substrate 12, is located in the first region 30, and is surrounded by the first protruding structure 16. The second trench 18 is formed in the substrate 12, is located in the second region 32, and is surrounded by the second protruding structure 20. It is worth noting that the depth H2 of the second trench 18 is greater than the depth H1 of the first trench 14. The first silicon oxide layer 22 is formed on the top 34 of the first protruding structure 16. A second silicon oxide layer 24 is formed on the top 36 of the second protruding structure 20. A first dielectric layer 26 is formed on the first silicon oxide layer 22. A second dielectric layer 28 is formed on the second silicon oxide layer 24. It is worth noting that the thickness T1 of the first dielectric layer 26 is greater than the thickness T2 of the second dielectric layer 28.

In some embodiments, the substrate 12 may be a silicon substrate.

In some embodiments, the first region 30 may be a region provided by a low voltage element, and the second region 32 may be a high voltage region. The area where the component is set.

In some embodiments, the first trench 14 may be electrical isolation between low-voltage components, and the second trench 18 may be electrical isolation between high-voltage components.

In some embodiments, the difference between the depth H1 of the first trench 14 and the depth H2 of the second trench 18 is generally between 500 angstroms and 5,000 angstroms.

In some embodiments, the first dielectric layer 26 and the second dielectric layer 28 may include silicon nitride or silicon oxide.

In this embodiment, the first dielectric layer 26 and the second dielectric layer 28 are silicon nitride.

In this embodiment, the first silicon oxide layer 22 further includes a sidewall 40 extending to cover a portion of the first protruding structure 16, and the second silicon oxide layer 24 further includes a sidewall 42 extending to cover a portion of the second protruding structure 20. It is worth noting that the radius of curvature R2 of the connecting portion 46 between the top 36 of the second protruding structure 20 and the side wall 42 is greater than the radius of curvature R1 of the connecting portion 44 between the top 34 of the first protruding structure 16 and the side wall 40.

In some embodiments, the difference between the thickness T1 of the first dielectric layer 26 and the thickness T2 of the second dielectric layer 28 is generally between 300 angstroms and 1,000 angstroms.

Please refer to FIGS. 4A-4E. According to an embodiment of the present disclosure, a method for manufacturing a semiconductor structure 10 is provided. 4A-4E are schematic cross-sectional views of a method for manufacturing the semiconductor structure 10.

As shown in FIG. 4A, a substrate 12 is provided. The substrate 12 includes a first region 30 and a second region 32.

In some embodiments, the substrate 12 may be a silicon substrate.

In some embodiments, the first region 30 may be a region where a low voltage element is provided, and the second region 32 may be a region where a high voltage element is provided.

After that, a silicon oxide layer 25 is formed on the substrate 12.

Thereafter, a dielectric layer 29 is formed on the silicon oxide layer 25.

In some embodiments, the dielectric layer 29 may include silicon nitride or silicon oxide.

In this embodiment, the dielectric layer 29 is silicon nitride.

Thereafter, the dielectric layer 29 is patterned to form a first dielectric layer 26 located in the first region 30 of the substrate 12 and a second dielectric layer 28 located in the second region 32 of the substrate 12. It is worth noting that the thickness T1 of the first dielectric layer 26 is greater than the thickness T2 of the second dielectric layer 28, as shown in FIG. 4B.

In some embodiments, the difference between the thickness T1 of the first dielectric layer 26 and the thickness T2 of the second dielectric layer 28 is generally between 300 angstroms and 1,000 angstroms.

Thereafter, a patterned photoresist layer 38 is formed on the first dielectric layer 26 and the second dielectric layer 28, as shown in FIG. 4C.

After that, using the patterned photoresist layer 38 as a mask, an etching process is performed to etch the first dielectric layer 26 and the second dielectric layer 28, pass through the silicon oxide layer 25 to the substrate 12, and In a region 30, a first trench 14 is formed, surrounded by a first protruding structure 16, and in a second region 32 of the substrate 12, a second trench 18 is formed, surrounded by a second protruding structure 20. It is worth noting that the depth H2 of the second trench 18 is greater than the depth H1 of the first trench 14. The silicon oxide layer on the top 34 of the first protruding structure 16 is defined as the first silicon oxide layer 22, and the silicon oxide layer on the top 36 of the second protruding structure 20 is defined as the second silicon oxide layer 24, as in the 4D As shown.

In some embodiments, the etching gas in the above-mentioned etching process may include sulfur hexafluoride, a combination of methane and nitrogen, or a combination of sulfur hexafluoride, methane, nitrogen, and oxygen.

In some embodiments, the etching selectivity ratio of the first dielectric layer 26 and the second dielectric layer 28 to the substrate 12 is generally between 1: 4 and 1:10.

In some embodiments, the first trench 14 may be an electrical isolation between low-voltage components, and the second trench 18 may be an electrical isolation between high-voltage components.

In some embodiments, the difference between the depth H1 of the first trench 14 and the depth H2 of the second trench 18 is generally between 500 angstroms and 5,000 angstroms.

After that, the patterned photoresist layer 38 is removed.

In this embodiment, an oxidation process is further performed, so that the first silicon oxide layer 22 extends to cover a side wall 40 of a portion of the first protruding structure 16, and the second silicon oxide layer 24 extends to cover a portion of the second protruding structure 20. Side wall 42. It is worth noting that the radius of curvature R2 of the connecting portion 46 between the top 36 of the second protruding structure 20 and the side wall 42 is greater than the radius of curvature R1 of the connecting portion 44 between the top 34 of the first protruding structure 16 and the side wall 40, as shown in FIG. 4E. Show. So far, the fabrication of the semiconductor structure 10 of this embodiment is completed.

The present disclosure produces silicon nitride layers with different thicknesses in the low-voltage region and the high-voltage region (that is, a thicker silicon nitride layer in the low-voltage region and a thinner silicon nitride layer in the high-voltage region), and then cooperates with A single etching step with specific etching conditions (such as the silicon nitride layer-to-silicon substrate etching selection ratio) can simultaneously obtain shallower trenches in the low-voltage region and deeper trenches in the high-voltage region.

In addition, during subsequent oxidation processes (can be ground in CMP) (CMP process is performed before or after the process), because the silicon nitride layer in the low voltage region is thicker, and the silicon nitride layer in the high voltage region is thinner, the rounding effect of the trench in the low voltage region is less obvious, and the high voltage region The trench presents a more obvious rounding effect, and this different degree of rounding effect has exactly different contributions to the low-voltage component and the high-voltage component, respectively. For low-voltage components, the lower rounding effect can maintain the effective width of the element channel, and get a high saturation-region drain current (Idsat), while for high-voltage components, a higher roundness The effect can improve the uniformity of related structures in the whole wafer and increase the matching of components.

Therefore, the present disclosure can simultaneously improve the structural and electrical advantages of low-voltage components and high-voltage components while making trenches of different depths in the low-voltage area and the high-voltage area.

Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make any changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.

Claims (18)

A semiconductor structure includes: a substrate including a first region and a second region; a first trench formed in the substrate, located in the first region, surrounded by a first protruding structure; and a first Two trenches are formed in the substrate, are located in the second region, and are surrounded by a second protruding structure, wherein the depth of the second trench is greater than the depth of the first trench, and the top of the second protruding structure The radius of curvature of the connecting portion with the side wall is larger than the radius of curvature of the connecting portion between the top of the first protruding structure and the side wall. The semiconductor structure according to item 1 of the patent application scope, wherein the substrate is a silicon substrate. The semiconductor structure according to item 1 of the scope of patent application, wherein the first region is a region where a low-voltage element is provided, and the second region is a region where a high-voltage element is provided. The semiconductor structure according to item 1 of the scope of the patent application, wherein the first trench is an electrical isolation between low-voltage components and the second trench is an electrical isolation between high-voltage components. According to the semiconductor structure described in item 1 of the patent application scope, a difference between a depth of the first trench and a depth of the second trench is generally between 500 angstroms and 5,000 angstroms. The semiconductor structure described in item 1 of the patent application scope further includes a first silicon oxide layer formed on the top of the first protruding structure, and a second silicon oxide layer formed on the second protruding structure. top. According to the sixth aspect of the patent application, the semiconductor structure further includes a first dielectric layer formed on the first silicon oxide layer, and a second dielectric layer formed on the second silicon oxide layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer. The semiconductor structure according to item 7 of the scope of patent application, wherein the first dielectric layer and the second dielectric layer include silicon nitride or silicon oxide. The semiconductor structure according to item 8 of the application, wherein when the first dielectric layer and the second dielectric layer are silicon nitride, the first silicon oxide layer further includes an extension covering the first protruding structure. Part of the sidewall, the second silicon oxide layer further includes a portion of the sidewall extending to cover the second protruding structure. The semiconductor structure according to item 7 of the scope of patent application, wherein the difference between the thickness of the first dielectric layer and the thickness of the second dielectric layer is generally between 300 angstroms and 1,000 angstroms. A method for manufacturing a semiconductor structure includes: providing a substrate including a first region and a second region; forming a silicon oxide layer on the substrate; and forming a dielectric layer on the silicon oxide layer, wherein The thickness of the dielectric layer in the first region of the substrate is greater than the thickness of the dielectric layer in the second region of the substrate; and an etching process is performed to etch the dielectric layer and pass through the silicon oxide Layer to the substrate so that a first trench is formed in the first region of the substrate, surrounded by a first protruding structure, and a second trench is formed in the second region of the substrate. Surrounded by a second protruding structure, wherein the depth of the second trench is greater than the depth of the first trench, wherein the silicon oxide layer on top of the first protruding structure is defined as a first silicon oxide layer, which is located in the The silicon oxide layer on top of the second protruding structure is defined as a second silicon oxide layer. The method for manufacturing a semiconductor structure according to item 11 of the scope of patent application, wherein the thickness of the dielectric layer located in the first region of the substrate and the thickness of the dielectric layer located in the second region of the substrate Roughly between 300 Angstroms and 1,000 Angstroms. The method for manufacturing a semiconductor structure according to item 11 of the scope of the patent application, wherein the etching gas of the etching process includes sulfur hexafluoride, a combination of methane and nitrogen or a combination of sulfur hexafluoride, methane, nitrogen and oxygen. The method for manufacturing a semiconductor structure according to item 11 of the scope of the patent application, wherein an etching selection ratio of the dielectric layer to the substrate is generally between 1: 4 and 1:10. The method for manufacturing a semiconductor structure according to item 11 of the scope of patent application, wherein the difference between the depth of the first trench and the depth of the second trench is generally between 500 angstroms and 5,000 angstroms. The method for manufacturing a semiconductor structure according to item 11 of the scope of patent application, wherein the dielectric layer includes silicon nitride or silicon oxide. The method for manufacturing a semiconductor structure according to item 16 of the scope of patent application, wherein when the dielectric layer is silicon nitride, it further includes implementing an oxidation process so that the first silicon oxide layer extends to cover the first protruding structure. Part of the side wall, so that the second silicon oxide layer extends to cover part of the side wall of the second protruding structure. The method for manufacturing a semiconductor structure according to item 17 of the scope of patent application, wherein a radius of curvature of a connecting portion between the top portion of the second protruding structure and the sidewall is greater than a radius of curvature of the connecting portion between the top portion of the first protruding structure and the sidewall The radius of curvature.