TWI653671B - Resistive memory, manufacturing method thereof and chemical mechanical polishing process - Google Patents

Abstract

A resistive memory, a manufacturing method thereof and a chemical mechanical polishing process. The resistive memory body includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is disposed on a substrate. The variable resistance layer is disposed on the first electrode. The second electrode is disposed on the variable resistance layer. The first electrode includes a first titanium layer, a titanium oxide layer, and a conductive layer sequentially disposed on the substrate.

Description

Resistive memory, manufacturing method thereof and chemical mechanical polishing process

The present invention relates to a memory, a method of fabricating the same, and a semiconductor process, and more particularly to a resistive memory, a method of fabricating the same, and a chemical mechanical polishing process.

In recent years, resistive memory (such as resistive random access memory (RRAM)) has developed extremely rapidly and is the structure of the most watched future memory. Current resistive memory typically includes opposing upper and lower electrodes and a variable resistance layer between the upper and lower electrodes, i.e., having a generally well known metal-insulator-metal (MIM) structure. In the fabrication of the resistive memory, the lower electrode layer, the variable resistance layer and the upper electrode layer are sequentially formed directly on the substrate in the deposition chamber.

However, when the flatness of the substrate is not good, the flatness of the lower electrode layer, the variable resistance layer, and the upper electrode layer formed on the substrate is affected. Further, when the lower electrode layer, the variable resistance layer, and the upper electrode layer cannot have good flatness, the formed resistive memory cannot have a good electrical performance.

The present invention provides a chemical mechanical polishing process suitable for grinding a layer of titanium on a substrate.

The present invention provides a method of manufacturing a resistive memory using the above-described chemical mechanical polishing process.

The present invention provides a resistive memory manufactured by the above-described method of manufacturing a resistive memory.

The resistive memory of the present invention includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is disposed on a substrate. The variable resistance layer is disposed on the first electrode. The second electrode is disposed on the variable resistance layer. The first electrode includes a first titanium layer, a titanium oxide layer, and a conductive layer sequentially disposed on the substrate.

In an embodiment of the resistive memory of the present invention, the conductive layer includes a second titanium layer and a titanium nitride layer sequentially disposed on the titanium oxide layer.

The CMP process of the present invention is suitable for planarizing a titanium layer. The chemical mechanical polishing process includes the following steps. The titanium layer is brought into contact with the polishing pad to be ground to remove a portion of the titanium layer, and a titanium oxide layer is formed on the titanium layer. The titanium oxide layer is washed with a neutral solution. The titanium oxide layer is washed with an acidic solution. In the acidic solution, the titanium oxide layer is separated from the polishing pad. The acidic solution on the titanium oxide layer is removed.

In an embodiment of the chemical mechanical polishing process of the present invention, for example, an acidic slurry and a hydrogen peroxide solution are used for the grinding.

In an embodiment of the chemical mechanical polishing process of the present invention, the pH of the acidic slurry is, for example, less than 5, and the concentration of the hydrogen peroxide solution is, for example, less than 5%.

In an embodiment of the chemical mechanical polishing process of the present invention, the neutral solution is, for example, deionized water.

In an embodiment of the CMP process of the present invention, the acidic solution comprises an organic compound and an interfacial active agent.

In an embodiment of the chemical mechanical polishing process of the present invention, the method of removing the acidic solution is, for example, a solution of isopropyl alcohol (IPA).

The method of manufacturing the resistive memory of the present invention includes the following steps. A first titanium layer is formed on the substrate. The first titanium layer is ground by the chemical mechanical polishing process described above, and the titanium oxide layer is formed on the first titanium layer. A conductive layer is formed on the titanium oxide layer. A variable resistance layer is formed on the conductive layer. An electrode layer is formed on the variable resistance layer.

In an embodiment of the method of fabricating a resistive memory of the present invention, forming the conductive layer includes the following steps. A second titanium layer is formed on the titanium oxide layer. A titanium nitride layer is formed on the second titanium layer.

Based on the above, the chemical mechanical polishing process of the present invention can effectively grind the titanium layer while avoiding excessive particle residue, so that the ground titanium layer can have a flatter surface. In this way, the film layers formed on the titanium layer can also have good flatness, and the resistive memory formed through the film layers can have good electrical performance.

The above described features and advantages of the invention will be apparent from the following description.

FIG. 1 is a schematic flow chart of a chemical mechanical polishing process according to an embodiment of the invention. Referring to FIG. 1, first, in step 100, a substrate having a titanium layer formed thereon is held on a polishing carrier, and then a titanium layer is brought into contact with the polishing pad to chemically grind the titanium layer to remove a portion of titanium. Layer (reducing the thickness of the titanium layer). During the grinding process, the acidic slurry and the hydrogen peroxide solution are used for the grinding. The pH of the acidic slurry is, for example, less than 5, and the concentration of the hydrogen peroxide solution is less than 5%, but the invention is not limited thereto. The acidic slurry is used to grind the titanium layer, and the hydrogen peroxide solution is used to improve the polishing stability. In the process of grinding the titanium layer, since a titanium layer in contact with the external environment is oxidized, a titanium oxide layer is formed on the surface of the titanium layer.

Then, in step 102, a neutral cleaning solution (eg, deionized water) is provided to the polishing pad to perform a first cleaning of the titanium oxide layer. In this step, the particles in the acidic slurry and the slurry can be removed, and the particles can be prevented from accumulating on the surface of the substrate (titanium oxide layer).

Next, in step 104, an acidic cleaning solution is provided to the polishing pad to perform a second cleaning of the titanium oxide layer. The acidic cleaning solution may include an organic compound and an interfacial surfactant. In this step, particles remaining on the surface of the substrate (titanium oxide layer) can be further removed. The pH of the above acidic cleaning liquid is, for example, less than 5, but the present invention is not limited thereto.

Then, in step 106, while the acidic solution is maintained, the substrate is removed from the polishing pad to separate the titanium oxide layer from the polishing pad. In the process of separating the titanium oxide layer from the polishing pad, since the above acidic solution is maintained, it is possible to prevent the remaining particles and impurities from adhering to the titanium oxide layer.

Thereafter, at step 108, a third cleaning is performed to remove the acidic solution remaining on the titanium oxide layer. The cleaning liquid used for the third cleaning is, for example, an isopropyl alcohol solution. In this step, since the isopropyl alcohol solution is used for the cleaning, in addition to the removal of the residual acidic solution and the particles, the substrate can be simultaneously dried.

According to the above chemical mechanical polishing process, the titanium layer on the substrate can be effectively ground while avoiding excessive particle residue. Therefore, the ground titanium layer can have a flatter surface to facilitate subsequent processes.

The CMP process of the present invention can be applied to the fabrication of the lower electrode of a resistive memory to form a lower electrode having a flat surface. This will be described in detail below.

2A-2D are schematic cross-sectional views showing a manufacturing process of a resistive memory according to an embodiment of the invention. First, referring to FIG. 2A, a titanium layer 204 is formed on the substrate 200. The substrate 200 is, for example, a dielectric substrate, and a conductive plug 202 has been formed therein. A titanium layer 204 is formed on the surface of the substrate 200 and is in contact with the conductive plug 202. The method of forming the titanium layer 204 is, for example, a chemical vapor deposition process.

Then, referring to FIG. 2B, a portion of the titanium layer 204 is removed by a chemical mechanical polishing process as described in FIG. 1 to reduce the thickness of the titanium layer 204 while planarizing the titanium layer 204. As previously described, by grinding the titanium layer 204 by the chemical mechanical polishing process as described in FIG. 1, the titanium layer 204 can be made to have a flat surface and excessive particle residue can be avoided. Further, after the above-described chemical mechanical polishing process, a titanium oxide layer 206 is formed on the titanium layer 204.

Next, referring to FIG. 2C, a conductive layer is formed on the titanium oxide layer 206. The formed conductive layer, titanium oxide layer 206, and titanium layer 204 can be used to form the lower electrode of the resistive memory in a subsequent step. In the present embodiment, the conductive layer is composed of the titanium layer 208 and the titanium nitride layer 210 which are sequentially formed on the titanium oxide layer 206, but the present invention is not limited thereto. Then, a variable resistance layer 212 is formed on the conductive layer, and an electrode layer is formed on the variable resistance layer 212. In the present embodiment, the electrode layer is composed of the titanium layer 214 and the titanium nitride layer 216 which are sequentially formed on the variable resistance layer 212, but the present invention is not limited thereto. The method of forming the titanium layer 208, the titanium nitride layer 210, the variable resistance layer 212, the titanium layer 214, and the titanium nitride layer 216 is, for example, a chemical vapor deposition process.

Thereafter, referring to FIG. 2D, a titanium layer 204, a titanium oxide layer 206, a titanium layer 208, a titanium nitride layer 210, a variable resistance layer 212, a titanium layer 214, and a titanium nitride layer 216 are patterned to define In the resistive memory of the present invention, the patterned titanium layer 204a, the patterned titanium oxide layer 206a, the patterned titanium layer 208a, and the patterned titanium nitride layer 210a constitute a lower electrode of the resistive memory, patterned The titanium layer 214a and the patterned titanium nitride layer 216a constitute the upper electrode of the resistive memory, and the patterned variable resistance layer 212a is located between the upper electrode and the lower electrode.

In the present embodiment, since the titanium layer 204 polished by the chemical mechanical polishing process as described in FIG. 1 has good flatness, the film layer subsequently formed thereon can also have good flatness. In this way, the formed resistive memory can have good electrical performance.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 102, 104, 106, 108 ‧ ‧ steps

200‧‧‧Base

202‧‧‧conductive plug

204, 208, 214‧‧ ‧ titanium layer

204a, 208a, 214a‧‧‧ patterned titanium layer

206‧‧‧Titanium oxide layer

206a‧‧‧ patterned titanium oxide layer

210, 216‧‧‧ titanium nitride layer

210a, 216a‧‧‧ patterned titanium nitride layer

212‧‧‧Variable Resistance Layer

212a‧‧‧ patterned variable resistance layer

FIG. 1 is a schematic flow chart of a chemical mechanical polishing process according to an embodiment of the invention. 2A-2D are schematic cross-sectional views showing a manufacturing process of a resistive memory according to an embodiment of the invention.

Claims (10)

A resistive memory comprising: a first electrode disposed on a substrate; a variable resistance layer disposed on the first electrode; and a second electrode disposed on the variable resistance layer, wherein the first An electrode includes a first titanium layer, a titanium oxide layer, and a conductive layer sequentially disposed on the substrate, wherein the first titanium layer has a flat surface formed by a chemical mechanical polishing process. The resistive memory of claim 1, wherein the conductive layer comprises a second titanium layer and a titanium nitride layer sequentially disposed on the titanium oxide layer. A chemical mechanical polishing process suitable for planarizing a titanium layer, the chemical mechanical polishing process comprising: contacting the titanium layer with a polishing pad to perform grinding to remove a portion of the titanium layer, and forming a titanium oxide layer On the titanium layer; cleaning the titanium oxide layer with a neutral solution; washing the titanium oxide layer with an acidic solution; separating the titanium oxide layer from the polishing pad in the acidic solution; and removing the titanium oxide layer Said acidic solution on the titanium oxide layer. The chemical mechanical polishing process of claim 3, wherein the grinding is performed using an acidic slurry and a hydrogen peroxide solution. The chemical mechanical polishing process as described in claim 4, wherein The acidic slurry has a pH of less than 5 and the hydrogen peroxide solution has a concentration of less than 5%. The CMP process of claim 3, wherein the neutral solution comprises deionized water. The chemical mechanical polishing process of claim 3, wherein the acidic solution comprises an organic compound and an interfacial active agent. The CMP process of claim 3, wherein the method of removing the acidic solution comprises using an isopropanol solution. A method of manufacturing a resistive memory, comprising: forming a first titanium layer on a substrate; grinding the first by a chemical mechanical polishing process according to any one of claims 3 to 8. a titanium layer, and forming the titanium oxide layer on the first titanium layer; forming a conductive layer on the titanium oxide layer; forming a variable resistance layer on the conductive layer; and the variable resistance layer An electrode layer is formed thereon. The method of manufacturing a resistive memory according to claim 9, wherein the forming the conductive layer comprises: forming a second titanium layer on the titanium oxide layer; and forming nitrogen on the second titanium layer Titanium layer.