TWI645639B - Redundant isolating switch control circuit - Google Patents
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Abstract
一種冗餘隔離開關控制電路,包含一工作電源、一電力輸入端、一電力輸出端、至少一場效應電晶體、一第一電晶體及一第二電晶體,該場效應電晶體具有一閘極,一連接該電力輸入端的源極及一連接該電力輸出端的汲極,該第一電晶體與該第二電晶體以及關聯迴路構成電流鏡電路,該冗餘隔離開關控制電路更包含一第一電子單元及一第二電子單元,該第一電子單元具有一連接該第一電晶體的一第一基極的第一連接端及一連接該第二電晶體的一第二射極的第二連接端,該第二電子單元具有一連接該第一電晶體的一第一集極的第三連接端及一連接該閘極的第四連接端。A redundant isolating switch control circuit comprising a working power supply, a power input end, a power output end, at least one field effect transistor, a first transistor and a second transistor, the field effect transistor having a gate a first source connected to the power input end and a drain connected to the power output end, the first transistor and the second transistor and the associated circuit form a current mirror circuit, the redundant isolating switch control circuit further comprising a first An electronic unit and a second electronic unit, the first electronic unit having a first connection end connecting a first base of the first transistor and a second connection connecting a second emitter of the second transistor The second electronic unit has a third connection end connected to a first collector of the first transistor and a fourth connection end connected to the gate.
Description
本發明涉及一種冗餘隔離開關控制電路。 The invention relates to a redundant isolating switch control circuit.
現有冗餘隔離開關控制電路就如WO 2008/013895A1以及CN105450008A所揭,於此基於CN105450008A所揭該冗餘隔離開關控制電路進行模擬,並於模擬過程中對兩處於不同工作狀態的冗餘隔離開關控制電路80、90進行電路模擬,電路即如圖1所示,模擬條件如下,該冗餘隔離開關控制電路80被設定為電力輸入端電源(VIN1)為12伏特(V),且啟動時間為20ms,關閉時間為20ms,另一該冗餘隔離開關控制電路90則被設定為電力輸入端電源(Vs2)為12伏特(V),且固定於啟動的狀態下。除此之外,一負載70為100安培、012歐姆,另一方面,圖1中所呈現的一第一電壓量測單元(VG1)是用來測量該場效應電晶體81的閘源極電壓(VGS),一第一電流量測單元(IO1)是用來測量該冗餘隔離開關控制電路80的輸出電流,一第二電流量測單元(IO2)是用來測量該冗餘隔離開關控制電路90的輸出電流,一第二電壓量測單元(VIN)是用來測量該冗餘隔離開關控制電路80的電力輸入端電壓,一第三電壓量測單元(VO)是用來測量該負載70的端電壓。 The existing redundant isolating switch control circuit is disclosed in WO 2008/013895 A1 and CN 105450008 A. The redundant isolating switch control circuit disclosed in CN105450008A is simulated, and two redundant isolating switches in different working states are simulated in the simulation process. The control circuit 80, 90 performs circuit simulation, and the circuit is as shown in FIG. 1. The simulation condition is as follows. The redundant isolation switch control circuit 80 is set to a power input terminal power supply (V IN1 ) of 12 volts (V), and the startup time. For 20 ms, the off time is 20 ms, and the other redundant isolating switch control circuit 90 is set to 12 volts (V) of the power input terminal (V s2 ) and is fixed in the activated state. In addition, a load 70 is 100 amps, 012 ohms. On the other hand, a first voltage measuring unit (V G1 ) presented in FIG. 1 is used to measure the gate source of the field effect transistor 81. Voltage (V GS ), a first current measuring unit (I O1 ) is used to measure the output current of the redundant isolating switch control circuit 80, and a second current measuring unit (I O2 ) is used to measure the redundancy The output voltage of the isolation switch control circuit 90, a second voltage measurement unit (V IN ) is used to measure the voltage of the power input terminal of the redundant isolation switch control circuit 80, and a third voltage measurement unit (V O ) It is used to measure the terminal voltage of the load 70.
承上,電路模擬結果如圖2,從圖2可知,該冗餘隔離開關控制電路80的電力輸入端電壓一旦瞬間下降,該冗餘隔離開關控制電路80所包含的一場效應電晶體81未能即時關閉時,將會產生極大的反向電流。 As a result, the circuit simulation result is shown in FIG. 2. As can be seen from FIG. 2, once the voltage of the power input terminal of the redundant isolation switch control circuit 80 drops instantaneously, the field effect transistor 81 included in the redundant isolation switch control circuit 80 fails. When turned off instantly, it will generate a huge reverse current.
假若,分別將該冗餘隔離開關控制電路80、90所包含電阻82、92的阻值降低(本測試是將阻值由6.8k歐姆調降至3k歐姆),其模擬結果就如圖 3所揭。然由圖3可知,如此修改雖可加快該場效應電晶體81、91的反應速度,避免極大反向電流的產生,但如此卻會增加該場效應電晶體81、91的導通損。 If the resistance values of the resistors 82 and 92 included in the redundant isolation switch control circuits 80 and 90 are respectively reduced (this test is to reduce the resistance from 6.8 k ohm to 3 k ohm), the simulation result is as shown in the figure. 3 revealed. As can be seen from Fig. 3, such a modification can speed up the reaction speed of the field effect transistors 81, 91 and avoid the generation of a large reverse current, but this increases the conduction loss of the field effect transistors 81, 91.
本發明的主要目的,在於解決習用電路於實施過程中所產生的問題。 The main object of the present invention is to solve the problems that occur in the implementation of conventional circuits.
為達上述目的,本發明提供一種冗餘隔離開關控制電路,包含一電力輸入端、一電力輸出端、一穩壓單元、至少一場效應電晶體、一第一電晶體、一第二電晶體。該穩壓單元連接該電力輸入端並具有一工作電源,該場效應電晶體具有一閘極,一連接該電力輸入端的源極以及一連接該電力輸出端的汲極,該第一電晶體具有一第一基極,一連接該電力輸入端的第一射極以及一連接該工作電源的第一集極,該第二電晶體具有一第二射極,一連接該工作電源的第二基極以及一連接該電力輸出端的第二集極,該第二基極與該第二射極連接。進一步地,該冗餘隔離開關控制電路更包含一第一電子單元以及一第二電子單元,該第一電子單元具有一連接該第一基極的第一連接端以及一連接該第二射極的第二連接端,該第二電子單元具有一連接該第一集極的第三連接端以及一連接該閘極的第四連接端,其中,該第一電子單元為一二極體、一電阻以及一電容器的其中之一者,該第二電子單元為一用於啟動或關閉該場效應電晶體的集成電路元件、一二極體以及一電阻的其中之一者。 To achieve the above objective, the present invention provides a redundant isolating switch control circuit including a power input terminal, a power output terminal, a voltage stabilizing unit, at least one field effect transistor, a first transistor, and a second transistor. The voltage stabilizing unit is connected to the power input end and has a working power source. The field effect transistor has a gate, a source connected to the power input end, and a drain connected to the power output end. The first transistor has a first transistor. a first base, a first emitter connected to the power input end, and a first collector connected to the working power source, the second transistor has a second emitter, a second base connected to the working power source, and A second collector connected to the power output, the second base being coupled to the second emitter. Further, the redundant isolating switch control circuit further includes a first electronic unit and a second electronic unit, the first electronic unit having a first connecting end connected to the first base and a connecting the second emitting end a second connecting end, the second electronic unit has a third connecting end connecting the first collector and a fourth connecting end connecting the gate, wherein the first electronic unit is a diode, a One of a resistor and a capacitor, the second electronic unit being one of an integrated circuit component, a diode, and a resistor for activating or deactivating the field effect transistor.
一實施例中,該冗餘隔離開關控制電路包含複數場效應電晶體,該些場效應電晶體並聯設置,該些場效應電晶體的每一該閘極分別連接該 第二電子單元的該第四連接端,每一該源極分別連接該電力輸入端,每一該汲極分別連接該電力輸出端。 In one embodiment, the redundant isolation switch control circuit includes a plurality of field effect transistors, and the field effect transistors are disposed in parallel, and each of the gates of the field effect transistors are respectively connected to the The fourth connection end of the second electronic unit, each of the sources is respectively connected to the power input end, and each of the drain electrodes is respectively connected to the power output end.
一實施例中,該冗餘隔離開關控制電路具有一設置於該工作電源與該第一集極之間的第一電阻,以及一設置於該工作電源與第二基極的第二電阻。 In one embodiment, the redundant isolating switch control circuit has a first resistor disposed between the operating power source and the first collector, and a second resistor disposed between the operating power source and the second base.
透過本發明前述實施方式,相較於習用具有以下特點:本發明該冗餘隔離開關控制電路改善了該場效應電晶體的反應速度,並有效降低該冗餘隔離開關控制電路的內電力輸入端電壓瞬間下降所產生的反向電流,並兼顧了該場效應電晶體的導通損。 Through the foregoing embodiments of the present invention, the redundant isolation switch control circuit of the present invention improves the reaction speed of the field effect transistor and effectively reduces the internal power input end of the redundant isolation switch control circuit. The reverse current generated by the instantaneous drop of the voltage, taking into account the conduction loss of the field effect transistor.
10‧‧‧冗餘隔離開關控制電路 10‧‧‧Redundant isolating switch control circuit
101‧‧‧工作電源 101‧‧‧Working power supply
102‧‧‧電力輸入端 102‧‧‧Power input
103‧‧‧電力輸出端 103‧‧‧Power output
11‧‧‧場效應電晶體 11‧‧‧ Field Effect Transistor
111‧‧‧閘極 111‧‧‧ gate
112‧‧‧源極 112‧‧‧ source
113‧‧‧汲極 113‧‧‧汲polar
12‧‧‧第一電晶體 12‧‧‧First transistor
121‧‧‧第一基極 121‧‧‧First base
122‧‧‧第一射極 122‧‧‧first emitter
123‧‧‧第一集極 123‧‧‧First episode
13‧‧‧第二電晶體 13‧‧‧Second transistor
131‧‧‧第二射極 131‧‧‧second emitter
132‧‧‧第二基極 132‧‧‧Second base
133‧‧‧第二集極 133‧‧‧Second episode
14‧‧‧第一電子單元 14‧‧‧First electronic unit
141‧‧‧第一連接端 141‧‧‧First connection
142‧‧‧第二連接端 142‧‧‧second connection
15‧‧‧第二電子單元 15‧‧‧Second electronic unit
151‧‧‧第三連接端 151‧‧‧ third connection
152‧‧‧第四連接端 152‧‧‧fourth connection
16‧‧‧穩壓單元 16‧‧‧Stabilizer
17‧‧‧第一電阻 17‧‧‧First resistance
18‧‧‧第二電阻 18‧‧‧second resistance
20‧‧‧負載 20‧‧‧ load
30‧‧‧冗餘隔離開關控制電路 30‧‧‧Redundant isolating switch control circuit
70‧‧‧負載 70‧‧‧ load
80‧‧‧冗餘隔離開關控制電路 80‧‧‧Redundant isolating switch control circuit
81‧‧‧場效應電晶體 81‧‧‧ Field Effect Transistor
82‧‧‧電阻 82‧‧‧resistance
90‧‧‧冗餘隔離開關控制電路 90‧‧‧Redundant isolating switch control circuit
91‧‧‧場效應電晶體 91‧‧‧ Field Effect Transistor
92‧‧‧電阻 92‧‧‧resistance
VIN1‧‧‧電力輸入端電源 V IN1 ‧‧‧Power input power supply
Vs2‧‧‧電力輸入端電源 V s2 ‧‧‧Power input power supply
VG1‧‧‧第一電壓量測單元 V G1 ‧‧‧First voltage measuring unit
IO1‧‧‧第一電流量測單元 I O1 ‧‧‧First current measuring unit
IO2‧‧‧第二電流量測單元 I O2 ‧‧‧Second current measuring unit
VIN‧‧‧第二電壓量測單元 V IN ‧‧‧second voltage measuring unit
VO‧‧‧第三電壓量測單元 V O ‧‧‧ third voltage measuring unit
圖1,習用冗餘隔離開關控制電路的電路示意圖。 Figure 1. Schematic diagram of a conventional redundant isolation switch control circuit.
圖2,習用冗餘隔離開關控制電路的模擬波形示意圖(一)。 Figure 2 is a schematic diagram of the analog waveform of the conventional redundant isolating switch control circuit (1).
圖3,習用冗餘隔離開關控制電路的模擬波形示意圖(二)。 Figure 3 is a schematic diagram of the analog waveform of the conventional redundant isolation switch control circuit (2).
圖4,本發明冗餘隔離開關控制電路的電路示意圖。 4 is a circuit diagram of a redundant isolation switch control circuit of the present invention.
圖5,本發明冗餘隔離開關控制電路第一實施例的電路示意圖。 Fig. 5 is a circuit diagram showing the first embodiment of the redundant isolation switch control circuit of the present invention.
圖6,本發明冗餘隔離開關控制電路第一實施例的模擬波形示意圖。 Figure 6 is a schematic diagram showing the analog waveform of the first embodiment of the redundant isolation switch control circuit of the present invention.
圖7,本發明冗餘隔離開關控制電路第二實施例的電路示意圖。 Figure 7 is a circuit diagram showing a second embodiment of the redundant isolation switch control circuit of the present invention.
圖8,本發明冗餘隔離開關控制電路第二實施例的模擬波形示意圖。 Figure 8 is a schematic diagram showing the analog waveform of the second embodiment of the redundant isolation switch control circuit of the present invention.
圖9,本發明冗餘隔離開關控制電路第三實施例的電路示意圖。 Figure 9 is a circuit diagram showing a third embodiment of the redundant isolation switch control circuit of the present invention.
圖10,本發明冗餘隔離開關控制電路第三實施例的模擬波形示意圖。 Figure 10 is a schematic diagram showing the analog waveform of the third embodiment of the redundant isolation switch control circuit of the present invention.
圖11,本發明冗餘隔離開關控制電路第四實施例的電路示意圖。 Figure 11 is a circuit diagram showing a fourth embodiment of the redundant isolation switch control circuit of the present invention.
圖12,本發明冗餘隔離開關控制電路第四實施例的模擬波形示意圖。 Figure 12 is a schematic diagram showing the analog waveform of the fourth embodiment of the redundant isolation switch control circuit of the present invention.
本發明詳細說明及技術內容,現就配合圖式說明如下:請參閱圖4至圖11,本發明提供一種冗餘隔離開關控制電路10,該冗餘隔離開關控制電路10可應用於一電源供應器(本圖未示)中,該冗餘隔離開關控制電路10包含一工作電源101、一電力輸入端102、一電力輸出端103、至少一場效應電晶體11、一第一電晶體12以及一第二電晶體13。該場效應電晶體11具有一閘極111,一連接該電力輸入端102的源極112以及一連接該電力輸出端103的汲極113。進一步地,該電力輸入端102實際上連接一電力轉換電路(本圖未示)的輸出端,以接受該電力轉換電路輸出的電力。另一方面,該電力輸出端103實際上則連接一負載20,以對該負載20供給電力。 The detailed description and technical contents of the present invention are now described as follows: Referring to FIG. 4 to FIG. 11, the present invention provides a redundant isolating switch control circuit 10, which can be applied to a power supply. The redundant isolation switch control circuit 10 includes a working power supply 101, a power input terminal 102, a power output terminal 103, at least one field effect transistor 11, a first transistor 12, and a controller (not shown). Second transistor 13. The field effect transistor 11 has a gate 111, a source 112 connected to the power input terminal 102, and a drain 113 connected to the power output terminal 103. Further, the power input terminal 102 is actually connected to an output of a power conversion circuit (not shown) to receive power output by the power conversion circuit. On the other hand, the power output terminal 103 is actually connected to a load 20 to supply power to the load 20.
再者,該場效應電晶體11即為本發明所稱冗餘隔離開關,該場效應電晶體11可根據該電源供應器的額定輸出電流進行佈設數量的調整,舉例來說,該電源供應器的額定輸出電流較大時,該冗餘隔離開關控制電路10即需增加該場效應電晶體11的數量,而當該場效應電晶體11以複數實施時,該些場效應電晶體11將並聯設置,該些場效應電晶體11的每一該閘極111將產生連結關係並受同一控制源所控制,每一該源極112分別連接該電力輸入端102,每一該汲極113分別連接該電力輸出端103。 Furthermore, the field effect transistor 11 is the redundant isolation switch of the present invention, and the field effect transistor 11 can adjust the number of layout according to the rated output current of the power supply. For example, the power supply When the rated output current is large, the redundant isolating switch control circuit 10 needs to increase the number of the field effect transistors 11, and when the field effect transistors 11 are implemented in plural, the field effect transistors 11 are connected in parallel. It is provided that each of the gates 111 of the field effect transistors 11 will be connected and controlled by the same control source, and each of the sources 112 is respectively connected to the power input terminal 102, and each of the drain electrodes 113 is respectively connected. The power output terminal 103.
承上,本發明令該第一電晶體12與該第二電晶體13構成一電流鏡電路,該第一電晶體12具有一第一基極121,一連接該電力輸入端102的第一射極122以及一連接該工作電源101的第一集極123,該第二電晶體13具有一第二射極131,一連接該工作電源101的第二基極132以及一連接該電力輸出端103的第二集極133,該第二基極132與該第二射極131連接。再者,該 第一電晶體12與該第二電晶體13可被設置於同一封裝件中,也就是說,該第一電晶體12與該第二電晶體13可以封裝晶片的方式實施。 The first transistor 12 and the second transistor 13 form a current mirror circuit. The first transistor 12 has a first base 121 and a first shot connected to the power input 102. The pole 122 and a first collector 123 connected to the working power source 101, the second transistor 13 has a second emitter 131, a second base 132 connected to the working power source 101, and a connection to the power output terminal 103. The second collector 133 is connected to the second emitter 131. Furthermore, the The first transistor 12 and the second transistor 13 can be disposed in the same package, that is, the first transistor 12 and the second transistor 13 can be implemented by encapsulating the wafer.
進一步地,本發明該冗餘隔離開關控制電路10更於該電流鏡電路中設有一第一電子單元14以及一第二電子單元15,該第一電子單元14具有一連接該第一基極121的第一連接端141以及一連接該第二射極131的第二連接端142,該第一電子單元14可為一二極體、一電阻以及一電容器的其中之一者。具體說明,本發明設置該第一電子單元14的用意,由前述記載可知,該第一電晶體12與該第二電晶體13將構成該電流鏡電路,而根據該電流鏡電路的工作原理可知,該第一電晶體12電流應相當於該第二電晶體13電流,亦即IB1=IB2。然,因該場效應電晶體11的負載電流導致該第一電晶體12電流不同於該第二電晶體13電流,而令該第一電晶體12與該第二電晶體13互為截止及導通狀態,進而控制該場效應電晶體11的啟閉。承此,本發明為避免習用電路會令該第二電晶體13與該電源供應器關閉或未啟動時燒毀,遂以前列方式實施。又,本發明透過該第一電子單元14的設置來進行參數補償,令該第一電晶體12的工作更為明確,並使該場效應電晶體11的反應速度加快。 Further, the redundant isolation switch control circuit 10 of the present invention further includes a first electronic unit 14 and a second electronic unit 15 in the current mirror circuit. The first electronic unit 14 has a connection to the first base 121. The first connecting end 141 and the second connecting end 142 are connected to the second emitter 131. The first electronic unit 14 can be one of a diode, a resistor and a capacitor. Specifically, the present invention is intended to provide the first electronic unit 14. As can be seen from the foregoing description, the first transistor 12 and the second transistor 13 will constitute the current mirror circuit, and according to the working principle of the current mirror circuit, The current of the first transistor 12 should correspond to the current of the second transistor 13, that is, I B1 =I B2 . However, the current of the first transistor 12 is different from the current of the second transistor 13 due to the load current of the field effect transistor 11, and the first transistor 12 and the second transistor 13 are turned off and on each other. The state, in turn, controls the opening and closing of the field effect transistor 11. Accordingly, the present invention is implemented in a prior art manner in order to prevent the conventional circuit from causing the second transistor 13 to be burned when the power supply is turned off or not turned on. Moreover, the present invention performs parameter compensation through the arrangement of the first electronic unit 14, so that the operation of the first transistor 12 is made clearer, and the reaction speed of the field effect transistor 11 is increased.
另一方面,該第二電子單元15具有一連接該第一集極123的第三連接端151以及一連接該閘極111的第四連接端152,該第二電子單元15為一用於啟閉控制的集成電路元件(又稱驅動IC)、一二極體以及一電阻的其中之一者。更具體說明,該第二電子單元15是作為驅動該場效應電晶體11的重要角色,因此該第二電子單元15的選用將依該場效應電晶體11的數量而定,舉例來說,當該場效應電晶體11數量較多而需較多的驅動電流時,該第二電子單元15即可以該驅動IC實施。 On the other hand, the second electronic unit 15 has a third connection end 151 connected to the first collector 123 and a fourth connection end 152 connected to the gate 111. The second electronic unit 15 is used for One of the closed-circuit integrated circuit components (also known as driver ICs), a diode, and a resistor. More specifically, the second electronic unit 15 plays an important role as the field effect transistor 11 , so the selection of the second electronic unit 15 will depend on the number of the field effect transistors 11 , for example, when When the number of field effect transistors 11 is large and a large amount of driving current is required, the second electronic unit 15 can be implemented by the driving IC.
進一步地,該冗餘隔離開關控制電路10更可包含一連接該電力輸入端102並具有該工作電源101的穩壓單元16,該穩壓單元16可以一穩壓電路實施或以一穩壓IC實施。另一方面,該冗餘隔離開關控制電路10具有一設置於該工作電源101與該第一集極123之間的第一電阻17,以及一設置於該工作電源101與第二基極132的第二電阻18。 Further, the redundant isolating switch control circuit 10 further includes a voltage stabilizing unit 16 connected to the power input terminal 102 and having the working power supply 101. The voltage stabilizing unit 16 can be implemented by a voltage stabilizing circuit or as a voltage stabilizing IC. Implementation. On the other hand, the redundant isolating switch control circuit 10 has a first resistor 17 disposed between the operating power source 101 and the first collector 123, and a first resistor 17 disposed between the operating power source 101 and the second base 132. The second resistor 18.
復請參閱圖5,於此本發明遂以兩處於不同工作狀態的該冗餘隔離開關控制電路10、30進行電路模擬,其中該第一電子單元14與該第二電子單元15分別為電阻,該冗餘隔離開關控制電路10被設定為電力輸入端電源(VIN1)為12伏特(V),且啟動時間為20ms,關閉時間為20ms,另一該冗餘隔離開關控制電路30則被設定為電力輸入端電源(Vs2)為12伏特(V),且固定於啟動的狀態下。除此之外,該負載20為100安培、0.12歐姆,另一方面,圖5中所呈現的該第一電壓量測單元(VG1)是用來測量該場效應電晶體11的閘源極電壓(VGS),該第一電流量測單元(IO1)是用來測量該冗餘隔離開關控制電路10的輸出電流,該第二電流量測單元(IO2)是用來測量該冗餘隔離開關控制電路30的輸出電流,該第二電壓量測單元(VIN)是用來測量該冗餘隔離開關控制電路10的電力輸入端電壓,該第三電壓量測單元(VO)是用來測量該負載20的端電壓。承此,電路模擬後的結果如圖6所示。再者,併參閱圖7,一實施例中,該第一電子單元14與該第二電子單元15分別為二極體與電阻的並聯組合,其餘模擬條件則如前一模擬實施例,於此不予贅述,電路模擬後的結果如圖8所示。又,併請參閱圖9,一實施例中,該第一電子單元14為電容與電阻的並聯組合,該第二電子單元15則為二極體與電阻的並聯組合,其餘模擬條件則如前一模擬實施例,於此不予贅述,電路模擬後的結果如圖10所示。又,併請參閱圖11,一實施例中,該第一電子單元14 為電容與電阻的並聯組合,該第二電子單元15則為驅動IC,其餘模擬條件則如前一模擬實施例,於此不予贅述,電路模擬後的結果如圖12所示。 Referring to FIG. 5, the present invention performs circuit simulation by using the redundant isolation switch control circuits 10 and 30 in different working states, wherein the first electronic unit 14 and the second electronic unit 15 are respectively resistors. The redundant isolation switch control circuit 10 is set to have a power input terminal power supply (V IN1 ) of 12 volts (V), a startup time of 20 ms, a turn-off time of 20 ms, and the other redundant isolation switch control circuit 30 is set. The power input terminal (V s2 ) is 12 volts (V) and is fixed in the activated state. In addition, the load 20 is 100 amps and 0.12 ohms. On the other hand, the first voltage measuring unit (V G1 ) presented in FIG. 5 is used to measure the gate source of the field effect transistor 11 . Voltage (V GS ), the first current measuring unit (I O1 ) is used to measure the output current of the redundant isolating switch control circuit 10, and the second current measuring unit (I O2 ) is used to measure the redundancy The output voltage of the switch is controlled by the second voltage measuring unit (V IN ) for measuring the voltage of the power input terminal of the redundant isolating switch control circuit 10, the third voltage measuring unit (V O ) It is used to measure the terminal voltage of the load 20. As a result, the results of the circuit simulation are shown in Figure 6. Furthermore, referring to FIG. 7, in an embodiment, the first electronic unit 14 and the second electronic unit 15 are respectively a parallel combination of a diode and a resistor, and the remaining simulation conditions are as in the previous simulation embodiment. Without further elaboration, the results after circuit simulation are shown in Fig. 8. In addition, referring to FIG. 9, in an embodiment, the first electronic unit 14 is a parallel combination of a capacitor and a resistor, and the second electronic unit 15 is a parallel combination of a diode and a resistor, and the remaining simulation conditions are as before. A simulation embodiment will not be described here, and the result after the circuit simulation is shown in FIG. Moreover, referring to FIG. 11, in an embodiment, the first electronic unit 14 is a parallel combination of a capacitor and a resistor, and the second electronic unit 15 is a driving IC, and the remaining simulation conditions are as in the previous simulation embodiment. This will not be repeated, and the results after the circuit simulation are shown in FIG.
然而,從圖6、圖8、圖10以及圖12可知,本發明該冗餘隔離開關控制電路10改善了該場效應電晶體11的反應速度,並有效降低該冗餘隔離開關控制電路10的電力輸入端電壓瞬間下降所產生的反向電流,且該場效應電晶體11的閘源極電壓(VGS)可在電力輸入端電壓建立後提高到5伏特以上,而兼顧了該場效應電晶體11的導通損。 However, as can be seen from FIG. 6, FIG. 8, FIG. 10 and FIG. 12, the redundant isolating switch control circuit 10 of the present invention improves the reaction speed of the field effect transistor 11, and effectively reduces the redundant isolating switch control circuit 10. The reverse current generated by the voltage drop of the power input terminal instantaneously, and the gate-source voltage (V GS ) of the field effect transistor 11 can be increased to more than 5 volts after the voltage of the power input terminal is established, and the field effect electricity is taken into consideration The conduction loss of the crystal 11.
以上已將本發明做一詳細說明,惟以上所述者,僅為本發明的一較佳實施例而已,當不能以此限定本發明實施的範圍,即凡依本發明申請專利範圍所作的均等變化與修飾,皆應仍屬本發明的專利涵蓋範圍內。 The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. Variations and modifications are still within the scope of the patents of the present invention.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1841874A (en) * | 2005-03-18 | 2006-10-04 | 株式会社理光 | Power switching circuit |
| TW201126328A (en) * | 2009-10-30 | 2011-08-01 | Intersil Inc | Power supply with low power consumption hiccup standby operation |
| TW201407653A (en) * | 2012-08-03 | 2014-02-16 | Memchip Technology Co Ltd | Current control type electronic switch circuit |
| TW201517469A (en) * | 2013-05-29 | 2015-05-01 | Panasonic Corp | Load control device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1841874A (en) * | 2005-03-18 | 2006-10-04 | 株式会社理光 | Power switching circuit |
| TW201126328A (en) * | 2009-10-30 | 2011-08-01 | Intersil Inc | Power supply with low power consumption hiccup standby operation |
| TW201407653A (en) * | 2012-08-03 | 2014-02-16 | Memchip Technology Co Ltd | Current control type electronic switch circuit |
| TW201517469A (en) * | 2013-05-29 | 2015-05-01 | Panasonic Corp | Load control device |
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