TWI643204B - Memory Layout Fabricated for Preventing Reference Layer from Breaking - Google Patents

Abstract

A memory arrangement structure includes a plurality of substrates; a plurality of perforated regions respectively disposed at a center of each of the substrates; and a plurality of first contact regions respectively disposed on each of the substrates and located at one side of each of the perforated regions, each of the first connections The dot area is connected to the signal pads of each of the memory pads; and the plurality of second contact areas respectively disposed on the other substrate and located on the other side of each of the perforated areas, and the second contact area is used for each of the second contact areas. Connected to each of the pads of the memory with a signal line, and at least includes a PAR pin of the memory, and one of the substrates passes through the perforated area with another first contact area or second contact area The first contact region or the second contact region of the substrate is electrically connected to each other. Thereby, after the pins of the memory are electrically connected to the first contact region and the second contact region, the substrates are perforated through the corresponding signal lines corresponding to the first contact region or the second contact region. The guiding of the area is electrically connected across the layers, so that the memory can be effectively prevented from being broken when the memory is produced, and the power distribution and the layout space are sufficient to maintain better signal integrity. .

Description

Memory configuration structure

The invention relates to a memory arrangement structure, in particular to a situation in which the memory can be effectively prevented from being broken when the memory is produced, and has a better power distribution and sufficient line layout space, thereby maintaining a better signal. Integrity.

According to the conventional memory, the pins are usually electrically connected to the contacts according to the configuration requirements, and the contacts are electrically connected to each other by signal lines respectively; thereby completing the setting of the memory. However, in terms of the wiring method of the conventional memory, the perforations are provided on the substrate, and the pins and the contacts of the memory are directly electrically connected to each other by the signal lines through the perforation, except for the line layout. In addition to the space is more cramped, there is a situation in which the power supply is poorly distributed, and the reference layer is broken when wiring, so that the reference layer of the memory is less capable of signal integrity. Therefore, in order to improve the above-mentioned deficiency, the inventors of the present invention have devoted themselves to research and development of a "memory configuration structure" to effectively improve the disadvantages of the conventional use.

The main purpose of the present invention is to enable each substrate to be electrically connected to the first contact region and the second contact region, so that the substrates correspond to the first contact region or the second contact region. The signal lines are electrically connected to each other across the layers through the guidance of the perforated area, so that the memory can be effectively prevented from being broken when the memory is produced, and the power distribution and the layout space are sufficient to maintain Better signal integrity. In order to achieve the above object, the present invention is a memory arrangement structure comprising: a plurality of substrates; a plurality of perforated regions respectively disposed at the center of each substrate; a plurality of interconnected regions respectively disposed on the respective substrates and located in each of the perforated regions a first contact area on the side, each of the first contact areas is connected to a signal line of each of the memory pads; and a plurality of second respectively connected to the substrate and located on the other side of each of the perforated areas In the contact area, each of the second contact areas is connected to each of the pads of the memory by a signal line, and at least includes a PAR pin of the memory, and one of the substrates is a first contact area thereof Or the second contact region is electrically connected to the first contact region or the second contact region of the other substrate through the through-hole region. In one embodiment of the present invention, each of the perforated regions includes a first row of perforations, a second row of perforations disposed on one side of the first row of perforations, and a third row disposed on one side of the second row of perforations. perforation. In an embodiment of the invention, each of the first rows of perforations has at least eight perforations, and each of the second rows of perforations has at least nine perforations, and each of the third perforations has at least eight perforations. In an embodiment of the invention, each of the first row of perforations, the second row of perforations and the three rows of perforations respectively have a compartment. In an embodiment of the present invention, each of the outer edges of the perforations has an insulating portion, and each of the through holes has a power connection portion. In an embodiment of the present invention, each of the first contact regions includes a first row of contacts, a second row of contacts disposed on a side of the first row of contacts, and a second row of contacts. At the third row of contacts on one side, each of the first row of contacts, each of the second row of contacts and each of the third row of contacts has at least nine contacts. In an embodiment of the present invention, each of the second contact regions includes a first row of contacts, a second row of contacts disposed on a side of the first row of contacts, and a second row of contacts. At the third row of contacts on one side, each of the first row of contacts, each of the second row of contacts and each of the third row of contacts has at least nine contacts. In an embodiment of the present invention, each of the first contact regions and each of the second contact regions respectively passes through the through-hole region of the one of the substrates and the contact region of the other substrate by the signal line. The two contact areas are electrically connected. In one embodiment of the invention, each of the signal lines is of the same length.

Please refer to FIG. 1 and FIG. 2 for a basic schematic view of the present invention and a schematic view of the state of use of the present invention. As shown in the figure, the present invention is a memory arrangement structure including at least a plurality of substrates 1, a plurality of perforated regions 2, a plurality of first contact regions 3, and a plurality of second contact regions 4. Each of the substrates 1 is a circuit board, and each of the substrates 1 is provided in a corresponding or stacked manner. Each of the perforated areas 2 is connected to the center of each of the substrates 1 . Each of the first contact regions 3 is connected to each of the substrates 1 and located on one side of each of the perforated regions 2, and each of the first contact regions 3 is connected to a signal line of each of the pads of the memory (Fig. Not shown). Each of the second contact regions 4 is connected to each of the substrates 1 and located on the other side of each of the perforated regions 2, and each of the second contacts 4 is connected to the respective pads of the memory by signal lines. And including at least a PAR pin (not shown) of the memory, and causing one of the substrates to pass through the perforated area 2 and the first substrate 1 with the first contact area 3 or the second contact area 4 The contact area 3 or the second contact area 4 are electrically connected to each other. When the pins of the memory are electrically connected to the first contact region 3 and the second contact region 4 of one of the substrates 1, the first contact region 3 and the second contact region 4 are allowed to be connected. The corresponding signal line 5 is electrically connected to the desired contact area 3 or the second contact area 4 of the other substrate 1 through the guiding of the perforated area 2 (not shown) to make a memory. In the production process, the reference layer can be effectively prevented from being broken, and the power distribution and the layout space are sufficient, so as to maintain better signal integrity. In one embodiment of the present invention, each of the perforated areas 2 includes a first row of perforations 21, a second row of perforations 22 disposed on one side of the first row of perforations 21, and a perforation 22 disposed in the second row of perforations 22 The third row of perforations 23 on the side, each of the first row of perforations 21 has at least eight perforations 211, and each of the second rows of perforations 22 has at least nine perforations 221, and each of the third rows of perforations 23 has at least eight perforations 231, respectively. Each of the first row of perforations 21, each of the second rows of perforations 22 and each of the third row of perforations 23 respectively have a partition portion 24, and each of the outer perforations has 211, 221, 231 an insulating portion 212, 222, 232, and each of the through holes 211, 221, 231 has a power connection portion 25. In an embodiment of the present invention, each of the first contact regions 3 includes a first row of contacts 31, a second row of contacts 32 disposed on a side of the first row of contacts 31, and a first The third row of contacts 33 on the side of the second row of contacts 32, each of the first row of contacts 31, each of the second row of contacts 32 and each of the third row of contacts 33 has at least nine contacts 311, 321 331. In an embodiment of the present invention, each of the second contact regions 4 includes a first row of contacts 41, a second row of contacts 42 disposed on a side of the first row of contacts 41, and a second The third row of contacts 43 on the side of the second row of contacts 42, each of the first row of contacts 41, each of the second row of contacts 42 and each of the third row of contacts 43 respectively have at least nine contacts 411, 421 431. When the memory is electrically connected to the first contact region 3 and the second contact region 4 of one of the substrates 1, the following is exemplified: when the memory is connected, at least the VDD pin of the memory is connected to The first contact point 311 of the first row of contacts 31 is disposed in the first contact region 3; the A13 pin of the memory is connected to the second row of contacts 32 disposed in the first contact region 3 a first contact 321; the A17 pin of the memory is connected to the first contact 331 of the third row of contacts 33 provided in the first contact region 3; the PAR pin of the memory is connected to the The first contact 411 of the first row of contacts 41 is disposed in the second contact region 4; the A11 pin of the memory is connected to the second row of contacts 42 of the second contact region 4 A contact 421; the VSS pin of the memory is connected to the first contact 431 of the third row of contacts 43 provided in the second contact region 4. Since the perforated area 2 is disposed between the first contact area 3 and the second contact area 4, the first contact area 3 and the second contact area 4 of the substrate 1 and another When the substrate 1 (not shown) is electrically connected, the signal lines 5 are respectively disposed through the perforated area 2 through the two surfaces of the substrate 1 to the first row of through holes 21, the second row of holes 22 and the third row. Each of the through holes 211, 221, and 231 of the through hole 23 performs routing and guiding of each signal line 5, so that the contacts 311, 321, 331 of the first contact area 3 and the second contact area 4 are connected. The points 411, 421, and 431 pass through the respective through holes 211, 221, and 231 as needed, and the electrical connection between the signal lines 5 and the first contact area 3 and the second contact area 4 of the other substrate 1 is performed. The power cable or the grounding wire is connected to each power connection portion 25 as needed. In this embodiment, the signal lines 5 are the same length, so that the lines of the signal lines 5 can be cleaned and fallen. Causes the breaking of the reference layer, and can achieve each signal line 5 are equal in length, with better power distribution and enough line layout space. The first row of perforations 21, the second rows of perforations 22, and the third row of perforations 23 are separated by the partitions 24 to prevent the signal lines 5 from interfering with each other. When the signal lines 5 are worn to When the perforations 211, 221, and 231 are formed, the respective insulating portions 212, 222, and 232 can prevent the respective signal lines 5 from coming into contact with the respective power supply connecting portions 25 to cause a short circuit. In summary, the memory configuration structure of the present invention can electrically connect the pins of the memory to the first contact region and the second contact region, and let the substrates have their first contact regions or second connections. The signal lines corresponding to the dot areas are electrically connected to each other through the guiding of the perforated area, so that the memory can be effectively prevented from being broken when the memory is produced, and the power distribution and the layout space are sufficient. In turn, the better signal integrity can be maintained; thus, the invention can be made more progressive, more practical, and more in line with the needs of the consumer, and indeed meets the requirements of the invention patent application, and the patent application is filed according to law. However, the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto; therefore, the simple equivalent changes and modifications made in accordance with the scope of the present invention and the contents of the invention are modified. All should remain within the scope of the invention patent.

1‧‧‧Substrate

2‧‧‧Perforated area

21‧‧‧First row of perforations

211, 221, 231‧‧ ‧ piercing

212, 222, 232‧‧‧Insulation

22‧‧‧Second row of perforations

23‧‧‧ Third row of perforations

24‧‧‧section

25‧‧‧Power connection

3‧‧‧First junction area

31‧‧‧first row of contacts

311, 321, 331‧‧‧ contacts

32‧‧‧second row of contacts

33‧‧‧ third row of contacts

4‧‧‧Second junction area

41‧‧‧first row of contacts

411, 421, 431‧‧‧ contacts

42‧‧‧second row of contacts

43‧‧‧ third row of contacts

5‧‧‧Signal line

Figure 1 is a basic schematic view of the present invention. Fig. 2 is a schematic view showing the state of use of the present invention.

Claims (9)

A memory arrangement structure comprising: a plurality of substrates; a plurality of perforated regions respectively connected at a center of each substrate; and a plurality of first contact regions respectively connected to each of the substrates and located at one side of each of the perforated regions Each of the first contact regions is connected to the signal pads of each of the memory pads; and the plurality of second contact regions are respectively connected to the respective substrates and located on the other side of each of the perforated regions, each of The second contact area is connected to the signal pads of the memory, and includes at least the PAR pin of the memory, and one of the substrates is the first contact area or the second contact The region is electrically connected to the first contact region or the second contact region of the other substrate through the perforated area. The memory arrangement according to claim 1, wherein each of the perforated areas comprises a first row of perforations, a second row of perforations disposed on one side of the first row of perforations, and one of the second perforations. The third row of perforations on one side of the perforation. The memory arrangement according to claim 2, wherein each of the first rows of perforations has at least eight perforations, and each of the second rows of perforations has at least nine perforations, and each of the third rows of perforations has at least eight Perforation. The memory arrangement according to claim 3, wherein each of the first row of perforations, the second row of perforations and the third row of perforations respectively have a compartment. The memory arrangement according to claim 3, wherein each of the outer edges of the perforations has an insulating portion, and each of the through holes has a power connection portion. According to the memory configuration of claim 1, wherein each of the first contact regions includes a first row of contacts and a second row of contacts disposed on a side of the first row of contacts, And a third row of contacts disposed on one side of the second row of contacts, each of the first row of contacts, each of the second row of contacts and each of the third row of contacts respectively have at least nine contacts. According to the memory arrangement structure of claim 1, wherein each of the second contact points includes a first row of contacts and a second row of contacts disposed on a side of the first row of contacts, And a third row of contacts disposed on one side of the second row of contacts, each of the first row of contacts, each of the second row of contacts and each of the third row of contacts respectively have at least nine contacts. According to the memory configuration of claim 1, wherein each of the first contact regions and each of the second contact regions respectively pass through the perforated region and the other substrate via the two surfaces of one of the substrates by signal lines. A contact area or a second contact area is electrically connected. The memory arrangement according to item 8 of the patent application scope, wherein each of the signal lines has the same length.