TWI527196B - semiconductor structure and method for manufacturing the same - Google Patents

Description

Semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure having a conductive plug and a method of fabricating the same.

Semiconductor structures, including memory devices, are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. In response to this demand, it is required to manufacture a memory device having a high component density.

Since device critical dimensions have been reduced to the limits of technology, designers have developed a way to increase the density of memory devices by using a three-dimensional stacked memory device to achieve higher memory capacity while reducing the cost per bit. However, the complicated structure of such a memory device also complicates the manufacturing method.

According to an embodiment, a method of fabricating a semiconductor structure is disclosed. The method includes the following steps. Forming a first conductive structure on a substrate. A second conductive structure is formed on the substrate. The second conductive structure has an upper conductive portion that is different in material from the first conductive structure. Forming a lower dielectric portion of a dielectric structure on the first conductive junction Constructed on the second conductive structure. A dielectric layer is formed on the lower dielectric portion. An upper dielectric portion of the dielectric structure is formed over the dielectric layer. The material of the dielectric layer is different from the upper dielectric portion and the lower dielectric portion. A first conductive plug is formed to pass through the upper dielectric portion, the dielectric layer and the lower dielectric portion to physically and electrically contact the first conductive structure. Forming a second conductive plug, passing through the upper dielectric portion, the dielectric layer and the lower dielectric portion to physically and electrically contact the second conductive structure.

In accordance with another embodiment, a semiconductor structure is disclosed, including a substrate, a first conductive structure, a second conductive structure, a dielectric structure, a dielectric layer, a first conductive plug, and a second conductive plug. The first conductive structure is on the substrate. The second conductive structure is on the substrate and has an upper conductive portion different in material from the first conductive structure. The dielectric structure includes an upper dielectric portion and a lower dielectric portion. The dielectric layer is between the upper dielectric portion and the lower dielectric portion, and the material is different from the upper dielectric portion and the lower dielectric portion. The first conductive plug only passes through the upper dielectric portion, the dielectric layer and the lower dielectric portion to physically and electrically contact the first conductive structure. The second conductive plug passes through the upper dielectric portion, the dielectric layer and the lower dielectric portion to physically and electrically contact the second conductive structure.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

102‧‧‧Substrate

104‧‧‧First conductive structure

106‧‧‧First Circuit Area

108, 208‧‧‧ lower dielectric part

110‧‧‧矽 structure

112‧‧‧Second circuit area

114‧‧‧ Conductive stripes

116‧‧‧Dielectric stripes

118‧‧‧Insulation materials

120‧‧‧First etch stop layer

122, 122A, 122B, 122C, 222C‧‧‧ upper dielectric part

124, 224‧‧‧ dielectric layer

126‧‧‧ Upper conductive part

128‧‧‧Second conductive structure

130‧‧‧Electrical part

132‧‧‧ Lower dielectric part

134‧‧‧second etch stop layer

136‧‧‧ patterned mask

138, 238‧‧‧ dielectric layer

140‧‧‧Upper dielectric section

142, 242‧‧‧ dielectric structure

144‧‧‧ dielectric structure

146, 246‧‧‧ first conductive plug

148‧‧‧Second conductive plug

150‧‧‧Perforation

152‧‧‧Perforation

254‧‧‧Intermediary section

FIGS. 1A to 1H illustrate a method of fabricating a semiconductor structure according to an embodiment.

FIG. 2 illustrates a semiconductor structure according to a comparative example.

FIGS. 1A to 1H illustrate a method of fabricating a semiconductor structure according to an embodiment.

Referring to FIG. 1A, a substrate 102 is provided. Substrate 102 can include a germanium substrate, such as a polysilicon, or other suitable semiconductor substrate. The first conductive structure 104 is formed on the substrate 102 of the first circuit region 106. The lower dielectric portion 108 is formed on the first conductive structure 104. In one embodiment, the first conductive structure 104 includes a plurality of different levels of conductive steps separated from each other by the lower dielectric portion 108. In one embodiment, the conductive ladder of the first conductive structure 104 comprises a (not metallized) polysilicon material.

The germanium containing structure 110 is formed on the substrate 102 of the second circuit region 112. In one embodiment, the germanium containing structure 110 comprises a polycrystalline germanium. The germanium-containing structure 110 may be formed over the staggered stacked conductive strips 114 and dielectric strips 116 of the three-dimensional stacked memory and separated from the conductive strips 114 and the dielectric strips 116 by an insulating material 118. In one embodiment, the conductive steps of the first conductive structure 104 and the conductive stripes 114 of the second circuit region 112 may be disposed at the same level, and the germanium-containing structure 110 may be disposed higher than the first conductive structure 104.

A first etch stop layer 120 is formed to cover the lower dielectric portion 108 in the first circuit region 106 and the insulating material 118 on the germanium containing structure 110 in the second circuit region 112. A dielectric material is formed over the first etch stop layer 120 to form an upper dielectric portion 122 in the first circuit region 106. In one embodiment, the dielectric material may be planarized, such as chemical mechanical polishing, which stops at the first etch. Stop layer 120.

Referring to FIG. 1B, an etching step may be performed to remove portions of the upper dielectric portion 122 (FIG. 1A), the first etch stop layer 120 (FIG. 1A), and the insulating material 118 to expose the germanium-containing structure 110. Portion, and leaving the first etch stop layer 120 in the first circuit region 106 to form the dielectric layer 124 underlying the upper dielectric portion 122A.

Referring to FIG. 1C, the upper portion exposed by the germanium containing structure 110 (FIG. 1B) may be metallized to form an upper conductive portion 126 comprising a metal halide. The formed second conductive structure 128 includes an upper conductive portion 126 and a lower conductive portion 130, wherein the lower conductive portion 130 maintains a polycrystalline germanium material that is not metallized as the germanium containing structure 110. The second conductive structure 128 is not limited to a gate structure of a metal oxide semiconductor (MOS), but may be applied to a source and a drain, or other contact structures.

Referring to FIG. 1D, a dielectric material may be formed in the first circuit region 106 and the second circuit region 112 to form a lower dielectric portion 132 covering the second conductive structure 128 and forming an upper dielectric portion 122B. A second etch stop layer 134 is formed overlying the upper dielectric portion 122B in the first circuit region 106 and the lower dielectric portion 132 in the second circuit region 112.

Referring to FIG. 1E, a patterned mask 136 is formed overlying the second etch stop layer 134 (FIG. 1D) in the second circuit region 112. An etch process is performed to remove portions of the second etch stop layer 134 that are not masked in the first circuit region 106, wherein the remaining etch stop layer 134 forms the dielectric layer 138. Remove pattern The mask 136 is formed to form a structure as shown in FIG. 1F.

Referring to FIG. 1G, a dielectric material is formed on the upper dielectric portion 122B (FIG. 1F) of the first circuit region 106 and the dielectric layer 138 of the second circuit region 112 to form an upper dielectric layer in the first circuit region 106. The electrical portion 122C and the upper dielectric portion 140 are formed in the second circuit region 112. The material of the dielectric layer 124 is different from the upper dielectric portion 122C and the lower dielectric portion 108 of the dielectric structure 142. The material of the dielectric layer 138 is different from the upper dielectric portion 140 and the lower dielectric portion 132 of the dielectric structure 144. In one embodiment, for example, upper dielectric portions 122C, 140 and lower dielectric portions 108, 132 include an oxide, such as hafnium oxide. Dielectric layers 124, 138 include a nitride such as tantalum nitride.

Referring to FIG. 1H, a first conductive plug 146 is formed to pass through the upper dielectric portion 122C, the dielectric layer 124 and the lower dielectric portion 108 to physically and electrically contact the first conductive structure 104. The second conductive plug 148 is formed to pass through the upper dielectric portion 140, the dielectric layer 138 and the lower dielectric portion 132 to physically and electrically contact the upper conductive portion 126 of the second conductive structure 128. In one embodiment, for example, the aspect ratio or height of the first conductive plug 146 is greater than the second conductive plug 148. The first conductive plug 146 can have a high aspect ratio.

The first conductive plug 146 and the second conductive plug 148 may be formed by using an etching process to form the through holes 150, 152 and filling the through holes 150, 152 with a conductive material.

For example, the same mask (not shown) can be used to perform the first etching step while etching down from the upper surface of the upper dielectric portion 122C and the upper dielectric portion 140 to form a stop at the dielectric layer 124, 138 perforations. Compared to dielectric The layers 124, 138, the first etch step has a higher etch selectivity for the upper dielectric portions 122C, 140 (ie, the etch rate of the upper dielectric portions 122C, 140 in the first etch step is higher than the dielectric layers 124, 138 Or substantially not etching the dielectric layers 124, 138, the same concept will not be repeated hereafter, therefore, although the upper dielectric portion 122C is thicker than the upper dielectric portion 140, the first etching step and the resulting The perforations can be stopped at the dielectric layer 124 and the dielectric layer 138 as desired, and the perforations can have different desired aspect ratios, heights.

Then, in an embodiment, the dielectric layers 124, 138 exposed by the through holes may be removed by a second etching step different from the first etching step, so that the through holes extend downward to form a lower dielectric portion. Piercing of 108, 132. For example, the second etch step can have a higher etch selectivity for the dielectric layers 124, 138 than the upper dielectric portions 122C, 140 and the lower dielectric portions 108, 132, thus, the second etch step and The perforations formed thereby can be stopped at the lower dielectric portions 108, 132 as desired.

Then, in an embodiment, the lower dielectric portions 108, 132 exposed by the through holes may be removed by a third etching step different from the second etching step, so that the through holes are extended downward to form the first exposed first The conductive structure 104 and the through holes 150 and the through holes 152 of the second conductive structure 128. Compared with the dielectric layers 124, 138, the first conductive structure 104 and the second conductive structure 128, the third etching step has a higher etching selectivity for the lower dielectric portions 108, 132, and therefore, the third etching step and borrowing The perforations 150, 152 formed thereby can be stopped at the first conductive structure 104 and the second conductive structure 128 as desired.

For example, when the upper dielectric portions 122C, 140 are the same material as the lower dielectric portions 108, 132, the first etching step to remove the upper dielectric portions 122C, 140 and the lower dielectric portion 108 are removed. The third etching step of 132 can use the same etching environment, such as the same etching solution.

In other embodiments, since the thickness of the dielectric layer 124 and the lower dielectric portion 108 is approximately or substantially equal to the thickness of the dielectric layer 138 and the lower dielectric portion 132, the above-described method for removing the dielectric layers 124, 138 The second etching step may be continued after removal of the dielectric layers 124, 138 to continuously remove the lower dielectric portions 108, 132, such as controlling the etching time or the relationship of material etching selection such that the second etching step stops at the first The conductive structure 104 and the second conductive structure 128.

The semiconductor structure and its manufacturing method can be arbitrarily changed according to the above concept. The following examples illustrate several variations. For example, upper dielectric portions 122C, 140 and lower dielectric portions 108, 132 are not limited to oxides, and dielectric layers 124, 138 are not limited to nitride. In other embodiments, upper dielectric portions 122C, 140 The lower dielectric portions 108, 132 and the dielectric layers 124, 138 can arbitrarily change the material according to the etch process characteristics of the etch process parameters used to form the vias 150, 152. In some embodiments, the conductive strips 114 may be omitted, or the number of stacks of conductive strips 114 may be changed to be less than the conductive steps of the first conductive structures 104 such that the second conductive structures 128 are substantially similar to the first conductive structures 104 or The same class. In other embodiments, the first conductive plug 146 can be equal or shorter than the second conductive plug 148. The concept of the embodiments can also be applied to other types of devices that require the formation of a plurality of conductive plugs that electrically and physically contact different structural features and/or different levels (heights) of conductive structures.

2 is a semiconductor structure according to a comparative example, which differs from the semiconductor structure of the embodiment in that the first conductive plug 246 sequentially passes through the upper dielectric portion 222C, the dielectric layer 238, the dielectric portion 254, The dielectric layer 224 and the lower dielectric portion 208 physically and electrically contact the first conductive structure 104. By way of example, the upper dielectric portion 222C, the dielectric portion 254, and the lower dielectric portion 208 of the dielectric structure 242 include an oxide such as hafnium oxide, and the dielectric layers 224, 238 include a nitride such as tantalum nitride. Two photomasks must be used as compared to the semiconductor structure of the comparative example (one of the masks is used to remove the upper dielectric portion 222C and the dielectric layer 238, and the other photomask is used to remove the dielectric portion 254, dielectric The layer 224 and the lower dielectric portion 208), such as the semiconductor structures of the embodiments shown in FIGS. 1A through 1H, need only be etched using a single mask to form the first conductive plug 146 and the second conductive plug 148. The perforations 150, 152, and the etching process steps are small and the time is short. Moreover, embodiments may use a reticle having a feature size (eg, a non-critical dimension) that is greater than a comparative example (eg, a critical dimension). Therefore, the semiconductor structure of the embodiment has a low manufacturing cost and a high yield (WPH; wafer per hour).

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

104‧‧‧First conductive structure

106‧‧‧First Circuit Area

108‧‧‧ Lower dielectric part

112‧‧‧Second circuit area

114‧‧‧ Conductive stripes

122C‧‧‧Upper dielectric part

124‧‧‧ dielectric layer

126‧‧‧ Upper conductive part

128‧‧‧Second conductive structure

130‧‧‧Electrical part

132‧‧‧ Lower dielectric part

138‧‧‧ dielectric layer

140‧‧‧Upper dielectric section

142‧‧‧ dielectric structure

144‧‧‧ dielectric structure

146‧‧‧First conductive plug

148‧‧‧Second conductive plug

150‧‧‧Perforation

152‧‧‧Perforation

Claims (10)

A method of fabricating a semiconductor structure, comprising: forming a first conductive structure on a substrate; forming a second conductive structure on the substrate, the second conductive structure having an upper conductive portion different from the first conductive structure The upper conductive portion includes a metal halide; a lower dielectric portion forming a dielectric structure is on the first conductive structure and the second conductive structure; a dielectric layer is formed on the lower dielectric portion; forming the dielectric An upper dielectric portion of the structure is on the dielectric layer, the dielectric layer is different in material from the upper dielectric portion and the lower dielectric portion; forming a first conductive plug that passes only through the upper dielectric portion The dielectric layer and the lower dielectric portion are in physical and electrical contact with the first conductive structure; and a second conductive plug is formed through the upper dielectric portion, the dielectric layer and the lower dielectric layer In part, the second conductive structure is in physical and electrical contact. The method of fabricating a semiconductor structure according to claim 1, comprising: forming a germanium-containing structure; forming a first etch stop layer covering the lower dielectric portion and a second circuit in a first circuit region Removing the first etch stop layer in the second circuit region to expose the germanium-containing structure and leaving the first etch stop layer in the first circuit region to form The media An electrical layer; and a metallization process of the exposed portion of the germanium containing structure to form the upper conductive portion. The method of fabricating a semiconductor structure according to claim 1, comprising: forming a second etch stop layer covering the upper dielectric portion; and removing the second etch stop layer in a first circuit region, and The second etch stop layer in a second circuit region is left to form the dielectric layer. The method for fabricating a semiconductor structure according to claim 1, wherein the method of forming the first conductive plug and the second conductive plug comprises: removing a portion of the upper dielectric by a first etching step Part to form a plurality of perforations, the first etching step is stopped at the dielectric layer; and the dielectric layer exposed by the perforations is removed by a second etching step different from the first etching step, so that The through holes extend downward to expose the lower dielectric portion, the second etching step stops at the lower dielectric portion; and the plurality of etching steps are removed by a third etching step different from the second etching step The lower dielectric portion such that the through holes extend downward to expose the first conductive structure and the second conductive structure, respectively; and filling the through holes with a conductive material to form the first conductive plug and the second Conductive plug. The method of manufacturing a semiconductor structure according to claim 4, wherein The first etching step has a higher etching selectivity for the upper dielectric portion than the dielectric layer, and the second etching step is opposite to the upper dielectric portion and the lower dielectric portion. The electrical layer has a higher etch selectivity, and the third etch step has a higher etch selectivity for the lower dielectric portion than the dielectric layer. The method of fabricating a semiconductor structure according to claim 4, wherein the perforations for the first conductive plug and the second conductive plug are defined using the same mask. The method for fabricating a semiconductor structure according to claim 1, wherein the method of forming the first conductive plug and the second conductive plug comprises: removing a portion of the upper dielectric by a first etching step Part to form a plurality of perforations, the first etching step is stopped at the dielectric layer; and the dielectric layer exposed by the perforations is removed by a second etching step different from the first etching step, so that The through holes extend downward to expose the first conductive structure and the second conductive structure, the second etching step stops at the first conductive structure and the second conductive structure; and filling the through holes with a conductive material to form the a first conductive plug and the second conductive plug. A semiconductor structure includes: a substrate; a first conductive structure on the substrate; a second conductive structure is disposed on the substrate and has an upper conductive portion different from the first conductive structure, the upper conductive portion includes a metal halide; the dielectric structure includes an upper dielectric portion and a lower dielectric a dielectric layer between the upper dielectric portion and the lower dielectric portion, and having a material different from the upper dielectric portion and the lower dielectric portion; a first conductive plug that passes only through the upper portion The dielectric portion, the dielectric layer and the lower dielectric portion are in physical and electrical contact with the first conductive structure; and a second conductive plug passes through the upper dielectric portion, the dielectric layer and the lower portion The dielectric portion is in physical and electrical contact with the second conductive structure. The semiconductor structure of claim 8, wherein the first conductive plug has an aspect ratio greater than an aspect ratio of the second conductive plug. The semiconductor structure of claim 8, wherein the first conductive structure comprises a polysilicon, the upper dielectric portion and the lower dielectric portion of the dielectric structure comprise an oxide, the dielectric layer comprising a nitride.