TWI538410B - Pulse calibration circuit - Google Patents

Description

Pulse correction circuit

The present invention relates to a correction circuit, and more particularly to a pulse wave correction circuit.

In view of the clock jitter problem existing in the conventional phase lock loop (PLL), it has been pointed out that the sub-harmonically injection technique can be used to obtain an improvement. However, the influence of the width of the injected pulse wave injected into the phase-locked loop (VCO) on the clock jitter performance is not discussed in the literature. In fact, when the environment changes (for example, the power supply voltage or the change in the ambient temperature), the conventional injection pulse generation circuit will mutate, which will have a negative impact on the generated injection pulse. Moreover, the conventional injection pulse generation circuit does not design an appropriate injection pulse width for the clock jitter performance.

The invention provides a pulse wave correction circuit, including a pulse wave injection time point Positive circuit and pulse width correction circuit. The pulse injection time point correction circuit corrects the reference clock signal according to the mode signal and the first clock signal from the voltage controlled oscillator in the phase locked loop to generate the corrected clock signal, wherein the reference clock signal is also input to the phase lock signal. Loop. The pulse width correction circuit receives the proportional control signal and the corrected clock signal, and generates an injection pulse wave, wherein the proportional control signal is used to control the pulse width of the injected pulse wave and the clock period of the corrected clock signal The specific ratio value. The pulse injection time point correction circuit generates a start signal according to the mode signal, and the pulse width correction circuit injects the injection pulse into the voltage controlled oscillator in the phase locked loop according to the start signal.

In an embodiment of the invention, the proportional control signal is a digital signal, and the pulse width correction circuit includes a voltage control delay line, a first AND gate, a first current source, a capacitor, a plurality of second current sources, a decoder, The first switch, the plurality of second switches, and the second AND gate. The voltage control delay line receives the corrected clock signal and delays the corrected clock signal according to the feedback voltage delay to generate a delayed clock signal. The first gate generates an injection pulse wave according to the delayed clock signal and the corrected clock signal. The first current source outputs the first current to the node. The capacitor is coupled between the node and the ground point for generating a feedback voltage according to the first current. A plurality of second current sources output a plurality of second currents. The decoder converts the digital signal into a plurality of pilot numbers. The plurality of first switches are individually coupled between the plurality of second current sources and the ground point. A portion of the plurality of first switches are turned on in response to the plurality of pilot signals to transmit a portion of the plurality of second currents to a ground point. The second switch is coupled between the node and the plurality of second current sources, and is turned on in response to the injection of the pulse wave.

In an embodiment of the invention, the pulse wave correcting circuit further includes a second sum gate for injecting a pulse wave into the voltage controlled oscillator in the phase locked loop according to the injected pulse wave and the start signal output.

In an embodiment of the invention, when the current value of the first current is equal to the current value of the plurality of second currents, the pulse width of the injected pulse wave is equal to the clock period of the corrected clock signal multiplied by a specific ratio. value.

In one embodiment of the invention, the pulse width of the injected pulse wave is 1/4 of the period of the output signal of the phase locked loop.

Based on the above, the pulse width correction circuit in the pulse wave correction circuit according to the embodiment of the present invention can generate an injection pulse wave having an appropriate pulse width according to the proportional control signal and the corrected clock signal, and inject according to the start signal. The pulse wave is injected into the voltage controlled oscillator in the phase locked loop.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧ Pulse Correction Circuit

110‧‧‧ phase-locked loop

111‧‧‧Frequency Detector

112‧‧‧Charging pump

113‧‧‧ Loop Filter

114‧‧‧Automatic frequency controller

115‧‧‧Voltage Controlled Oscillator

116‧‧‧Delephone

120‧‧‧ Pulse injection time point correction circuit

121‧‧‧ finite state machine

122‧‧‧ and gate

123‧‧‧Resettable digital control delay line

124‧‧‧Digital Control Delay Line

125‧‧‧Digital loop filter

126‧‧‧砰砰 phase detector

130‧‧‧ Pulse width correction circuit

202‧‧‧Voltage control delay line

204‧‧‧First Gate

206‧‧‧First current source

C1‧‧‧ capacitor

208_1~208_M‧‧‧second current source

210‧‧‧Decoder

212_1~212_M‧‧‧First switch

214‧‧‧second switch

216‧‧‧second gate

310~330, 310'~330', 410~330, 410'~330', 510~530, 510'~530'‧‧‧ curves

CK _REF ‧‧‧Reference clock signal

CK _VCO+ ‧‧‧ first clock signal

CK _RDCL ‧‧‧corrected clock signal

CK’‧‧‧Delayed clock signal

CD_1~CD_M‧‧‧Direction number

CK _DLF ‧‧‧ clock signal

CK _DCL ‧‧‧ clock signal

C _DL , C _RDL ‧‧‧ control signals

EN _INJ ‧‧‧Start signal

EN _DLF ‧‧‧Enable signal

GND‧‧‧ Grounding point

INJ‧‧‧Injected pulse wave

I1‧‧‧First current

I2‧‧‧second current

MODE‧‧‧ mode signal

N1‧‧‧ node

RC‧‧‧ proportional control signal

R1‧‧‧ first reference signal

V _CTRL ‧‧‧ voltage control signal

Feedback voltage V _C ‧‧‧

1 is a schematic diagram of a pulse wave injection time point correction circuit, a pulse width correction circuit, and a phase locked loop according to an embodiment of the invention.

2 is a schematic diagram of a pulse width correction circuit according to an embodiment of the invention.

FIG. 3A is a diagram showing changes in the bandwidth of a phase-locked loop when the frequency of the output signal CK _OUT is 400 MHz according to an embodiment of the invention.

FIG. 3B is a diagram showing the bandwidth variation of the phase-locked loop when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention.

4A is a graph showing a trend of clock jitter of a phase-locked loop with respect to a power supply voltage when the frequency of the output signal CK _OUT is 400 MHz, according to an embodiment of the invention.

FIG. 4B is a graph showing the trend of the clock jitter of the phase locked loop with respect to the power supply voltage when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention.

FIG. 5A is a graph showing a trend of clock jitter of a phase-locked loop with respect to ambient temperature when the frequency of the output signal CK _OUT is 400 MHz according to an embodiment of the invention.

FIG. 5B is a graph showing the trend of the clock jitter of the phase-locked loop with respect to the ambient temperature when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention.

1 is a schematic diagram of a pulse wave injection time point correction circuit, a pulse width correction circuit, and a phase locked loop according to an embodiment of the invention. In the present embodiment, the phase locked loop 110 includes a phase frequency detector 111, a charge pump 112, a loop filter 113, an automatic frequency controller 114, a voltage controlled oscillator 115, and a frequency divider 116. Phase frequency detector 111, charge pump 112, loop filter 113, and voltage The control oscillator 115 is coupled in sequence. The phase frequency detector 111 is coupled to the phase frequency detector 111 through the frequency divider 116, and the loop filter 113 is coupled to the voltage controlled oscillator 115 through the automatic frequency controller 114.

In the phase-locked loop 110, the phase frequency detector 111 detects whether the phase of the reference clock signal CK _REF is leading or falling behind the phase of the first reference signal R1, and outputs a corresponding high-level signal according to the detection result. It is a low level signal to the charge pump 112. Then, the charge pump 112 can perform charging or discharging operation according to the high/low level signal output by the phase frequency detector 111, and output a signal to the loop filter 113. The loop filter 113 filters the signal output by the charge pump 112 to generate a voltage control signal V _CTRL . Automatic frequency controller 114 may be locked for operation of the voltage control signal V _CTRL, and the voltage control signal V _CTRL-locked output to the voltage controlled oscillator 115.

Next, the voltage controlled oscillator 115 may correspond to varying the frequency output signal CK _OUT according to the INJ injection pulse, the voltage control signal V _CTRL and the voltage control signal V _CTRL-locked, and generates a first clock signal CK _{VCO +.} Thereafter, the frequency divider 116 divides the frequency of the output signal CK _OUT by N times (N is a positive integer) to generate a first reference signal R1, and returns the first reference signal R1 to the phase frequency detector 111.

It is to be noted that the injection time point and the pulse width of the injection pulse wave INJ of the injection voltage control oscillator 115 in this embodiment are the pulse injection time point corrections in the pulse wave correction circuit 100 proposed by the embodiment of the present invention, respectively. The circuit 120 and the pulse width correction circuit 130 are corrected. In this way, when the environment changes, the characteristics of the injected pulse wave INJ (for example, the pulse width) do not change accordingly, and thus The clock jitter condition of the phase locked loop 110 is optimized. The details will be described below.

In this embodiment, the pulse injection time point correction circuit 120 includes a finite state machine 121, a gate 122, a resettable digital control delay line 123, a digital control delay line 124, a digital loop filter 125, and a phase detection. 126. In summary, the pulse injection time point correction circuit 120 can correct the reference clock signal CK _REF according to the mode signal MODE and the first clock signal CK _VCO+ from the voltage control oscillator 115 in the phase locked loop 110 to generate the corrected image. Clock signal CK _RDCL . The mode signal MODE is, for example, a signal composed of two bits, which allows the pulse injection time point correction circuit 120 to operate in one of four modes via user adjustment. The four modes are, for example, a general phase locked loop mode, a coarse tuning mode, a fine tuning mode, and an injection mode. In the general phase-locked loop mode, the pulse injection time point correction circuit 120 may perform no operation, so that the pulse width correction circuit 130 does not perform any operation. As a result, the phase-locked loop 110 will operate in a general manner and will not be described herein. In the coarse adjustment mode and the fine adjustment mode, the pulse injection time point correction circuit 120 roughly corrects and finely corrects the time point at which the injection pulse wave INJ is injected into the voltage control oscillator 115, respectively. In response to the mode signal MODE corresponding to the coarse mode and the fine mode, the finite state machine 121 can respectively generate the enable signal EN _DLF having the first width and the second width, wherein the first width is greater than the second width.

Then, the gate 122 generates a clock signal CK _DLF according to the enable signal EN _DLF having a specific width and the inverted reference clock signal CK _REF , and outputs the signal to the digital loop filter 125. The digital loop filter 125 generates the control signals C _DL and C _RDL according to the phase comparison result of the clock signal CK _DLF and the phase detector 126 for the clock signal CK _DCL and the first clock signal CK _VCO+ , wherein The clock signal CK _DCL is generated by the digitally controlled delay line 124 based on the reference clock signal CK _REF and the control signal C _DL . Then, the resettable digital control delay line 123 can generate the corrected clock signal CK _RDCL based on the reference clock signal CK _REF and the control signal C _RDL , and output the clock signal CK _RDCL to the pulse width correction circuit 130. It should be understood that the operation mode and principle of each component in the pulse injection time point correction circuit 120 can be referred to related documents, and details are not described herein again.

In other embodiments, the pulse width correction circuit 130 receives the proportional control signal RC and the corrected clock signal CK _RDCL and generates an injection pulse INJ according to the proportional control signal RC. The proportional control signal RC is used to control a specific ratio between the pulse width (indicated by D) of the injected pulse wave INJ and the clock period T _{REF of the} corrected pulse signal CK _RDCL .

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a pulse width correction circuit according to an embodiment of the invention. In this embodiment, the pulse width correction circuit 130 includes a voltage control delay line 202, a first AND gate 204, a first current source 206, a capacitor C1, a second current source 208_1~208_M (M is a positive integer), and a decoder. 210, first switches 212_1~212_M, second switch 214, and second AND gate 216.

The voltage control delay line 202 receives the corrected clock signal CK _RDCL and delays the corrected clock signal CK _RDCL according to the feedback voltage V _C to generate a delayed clock signal CK ′. The first gate 204 generates an injection pulse INJ according to the delayed clock signal CK' and the corrected clock signal CK _RDCL . It should be understood that the smaller the feedback voltage V _C is, the larger the amplitude of the pulse signal CK _RDCL after the voltage control delay line 202 is delayed, so that the pulse width (ie, D) of the injected pulse wave INJ is smaller, and vice versa. Also counter.

The first current source 206 outputs the first current I1 to the node N1. The capacitor C1 is coupled between the node N1 and the ground point GND for generating the feedback voltage V _C according to the first current I1. The second current sources 208_1~208_M individually output the second current I2. The first switches 212_1 212 212_M are individually coupled between the second current sources 208_1 208 208_M and the ground point GND. The second switch 214 is coupled between the node N1 and the second current sources 208_1 208 208_M, and is turned on according to the injection pulse INJ.

In one embodiment, the proportional control signal RC can be implemented, for example, as a 3-bit digital signal, and the decoder 210 can be used to convert the digital signal into a plurality of pilot numbers CD_1~CD_M. Assuming that the specific proportional value corresponding to the proportional control signal RC is set to 1/K (K is a positive integer), the decoder 210 can correspondingly control the first switches 212_1~212_M through the K signals of the communication numbers CD_1~CD_M. The K switches are turned on, and the K current sources among the second current sources 208_1~208_M can output K second currents I2 to the ground point GND.

Assume that, after the clock period of the corrected clock signal CK _RDCL is T _REF , and the current values of the first current I1 and the second current I2 are both I, the charge flowing into the node N1 in T _REF can be characterized as I × T _REF . In this case, when the specific proportional value corresponding to the proportional control signal RC is set to 1/K, and the pulse width of the injection pulse INJ is D, the charge flowing out of the node N1 in T _REF can be derived as K × I × D. According to the principle of conservation of charge, it can be known that the charge flowing into node N1 will be equal to the charge flowing out of node N1, so that the relationship of "I × T _REF = K × I × D" can be derived, and "D = " The relationship of T _REF /K". In other words, under the architecture shown in FIG. 2, when the current values of the first current I1 and the second current I2 are equal, the pulse width (ie, D) of the injected pulse wave INJ is equal to the time of the corrected clock signal CK _RDCL . The pulse period (ie, T _REF ) is multiplied by a specific scale value (ie, 1/K).

In an embodiment, when the mode signal MODE is switched to the signal corresponding to the injection mode, the finite state machine 121 can generate the start signal EN _INJ according to the mode signal MODE, and the pulse width correction circuit 130 can respond to the start signal EN _INJ. The injection pulse INJ is injected into the voltage controlled oscillator 115 in the phase locked loop 110. Specifically, the pulse width correction circuit 130 can receive the start signal EN _INJ and the injection pulse INJ from the first AND gate 204 by the second AND gate 216, and output the pulse wave according to the injection pulse INJ and the start signal EN _INJ. The voltage in INJ to phase-locked loop 110 controls oscillator 115.

From another point of view, after the user adjusts the proportional control signal RC according to the specific proportional value, the pulse width correction circuit 130 can accurately generate the pulse width according to the environment: "D=T _REF /K The relational injection pulse INJ. Therefore, after the user derives the optimum specific ratio value of the clock jitter that can optimize the phase-locked loop 110, the pulse width correction circuit 130 can generate an appropriate injection pulse INJ accordingly, and respond to the start signal. The EN _INJ injects the injection pulse INJ into the voltage controlled oscillator 115. As such, the clock jitter of the phase locked loop 110 can be optimized in response to the optimum specific ratio value.

It is deduced that when the pulse width of the injection pulse INJ is 1/4 of the period of the output signal CK _OUT (indicated by T _VCO ) (ie, D=T _VCO /4, hereinafter referred to as the optimum pulse width) The clock jitter of the phase-locked loop 110 is verified by different experimental waveforms.

FIG. 3A is a phase noise diagram of a phase locked loop when the frequency of the output signal CK _OUT is 400 MHz according to an embodiment of the invention. In this embodiment, the horizontal axis is the frequency offset and the vertical axis is the bandwidth of the phase locked loop. The curves 310 to 330 correspond to the cases of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (that is, the optimum pulse width). As shown in FIG. 3A, the root mean square value of the clock jitter corresponding to the curve 330 (about 10.65 ps) is significantly smaller than the root mean square value of the clock jitter corresponding to the curve 310 or 320 (about 16.73 ps and 12.01 ps, respectively). . That is to say, the pulse width of the injection pulse wave INJ corresponding to the curve 330 can surely achieve a better clock jitter suppression effect of the phase locked loop.

FIG. 3B is a phase noise diagram of a phase locked loop when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention. In this embodiment, the horizontal axis is the frequency offset and the vertical axis is the bandwidth of the phase locked loop. Curves 310'-330' correspond to the case of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (ie, optimal pulse width). As shown in Figure 3B, the area covered by curve 330' (approximately 2.29 ps) is significantly smaller than the area covered by curve 310' or 320' (approximately 3.42 ps and 2.52 ps, respectively). That is, even if the frequency of the output signal CK _OUT change, curve 330 'corresponding to the injection pulse width of the pulse INJ is still possible to achieve better phase-locked loop clock jitter suppressing effect.

4A is a graph showing a trend of clock jitter of a phase-locked loop with respect to a power supply voltage when the frequency of the output signal CK _OUT is 400 MHz, according to an embodiment of the invention. In this embodiment, the horizontal axis is the power supply voltage applied to the phase locked loop, and the vertical axis is the clock rms value of the phase locked loop. Curves 410 to 430 correspond to the case of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (ie, optimum pulse width). As shown in FIG. 4A, the clock rms value of curve 430 is lower than curves 410 and 420 regardless of the change in supply voltage. That is to say, even if the power supply voltage changes, the pulse width of the injection pulse wave INJ corresponding to the curve 430 can still achieve a better clock jitter suppression effect of the phase locked loop.

FIG. 4B is a graph showing the trend of the clock jitter of the phase locked loop with respect to the power supply voltage when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention. In this embodiment, the horizontal axis is the power supply voltage applied to the phase locked loop, and the vertical axis is the clock jitter rms value of the phase locked loop. The curves 410' to 430' correspond to the cases of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (ie, the optimum pulse width). As shown in FIG. 4B, the clock rms value of curve 430' is lower than curves 410' and 420' regardless of the change in supply voltage. That is to say, even if the frequency of the output signal CK _OUT is changed, the pulse width of the injection pulse INJ corresponding to the curve 430' can achieve a better clock jitter suppression effect of the phase locked loop under different power supply voltages.

FIG. 5A is a graph showing a trend of clock jitter of a phase-locked loop with respect to ambient temperature when the frequency of the output signal CK _OUT is 400 MHz according to an embodiment of the invention. In this embodiment, the horizontal axis is the ambient temperature of the phase locked loop, and the vertical axis is the clock root mean square value of the phase locked loop. The curves 510 to 530 correspond to the cases of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (ie, the optimum pulse width). As shown in FIG. 5A, the clock rms value of curve 530 is lower than curves 510 and 520 regardless of changes in ambient temperature. That is to say, even if the ambient temperature changes, the pulse width of the injection pulse INJ corresponding to the curve 530 can still achieve a better clock jitter suppression effect of the phase locked loop.

FIG. 5B is a graph showing the trend of the clock jitter of the phase-locked loop with respect to the ambient temperature when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention. In this embodiment, the horizontal axis is the ambient temperature applied to the phase locked loop, and the vertical axis is the clock rms value of the phase locked loop. Curves 510'-530' correspond to the case of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (ie, optimal pulse width). As shown in FIG. 5B, the clock rms value of curve 530' is lower than curves 510' and 520' regardless of changes in ambient temperature. That is to say, even if the frequency of the output signal CK _OUT is changed, the pulse width of the injection pulse INJ corresponding to the curve 530' can achieve a better clock jitter suppression effect at different ambient temperatures.

In summary, the pulse width correction circuit in the pulse wave correction circuit according to the embodiment of the present invention can generate an injection pulse wave having an appropriate pulse width according to the proportional control signal and the corrected clock signal, and respond to the start signal. The injection pulse is injected into the voltage controlled oscillator in the phase locked loop. In this way, after the user derives a specific pulse width (for example, D=T _VCO /4) that can optimize the clock jitter of the phase-locked loop, the pulse width correction circuit can generate the specific The pulse width is injected into the pulse wave, which in turn allows the clock jitter of the phase-locked loop to be optimized. Moreover, it has been experimentally verified that the specific pulse width can indeed achieve lower clock jitter than other pulse widths.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

130‧‧‧ Pulse width correction circuit

202‧‧‧Voltage control delay line

204‧‧‧First Gate

206‧‧‧First current source

C1‧‧‧ capacitor

208_1~208_M‧‧‧second current source

210‧‧‧Decoder

212_1~212_M‧‧‧First switch

214‧‧‧second switch

216‧‧‧second gate

CK _RDCL ‧‧‧corrected clock signal

CK’‧‧‧Delayed clock signal

CD_1~CD_M‧‧‧Direction number

EN _INJ ‧‧‧Start signal

GND‧‧‧ Grounding point

INJ‧‧‧Injected pulse wave

I1‧‧‧First current

I2‧‧‧second current

N1‧‧‧ node

RC‧‧‧ proportional control signal

Feedback voltage V _C ‧‧‧

Claims (5)

A pulse wave correction circuit includes: a pulse injection time point correction circuit for correcting a reference clock signal according to a mode signal and a first clock signal from a voltage controlled oscillator in the phase locked loop to generate a The corrected clock signal, wherein the reference clock signal is also input to a phase locked loop; and a pulse width correction circuit receives a proportional control signal and the corrected clock signal, and generates an injection pulse wave, The proportional control signal is used to control a specific ratio between a pulse width of the injected pulse wave and a clock period of the corrected pulse signal, wherein the pulse injection time point correction circuit is based on the mode signal An activation signal is generated, and the pulse width correction circuit injects the injection pulse into the voltage controlled oscillator in the phase locked loop according to the startup signal. The pulse wave correction circuit of claim 1, wherein the proportional control signal is a digital signal, and the pulse width correction circuit comprises: a voltage control delay line, receiving the corrected clock signal, and a feedback voltage delays the corrected clock signal to generate a delayed clock signal; a first gate, the injection pulse wave is generated according to the delayed clock signal and the corrected clock signal; a first current source, And outputting a first current to a node; a capacitor coupled between the node and a ground point for generating the feedback voltage according to the first current; a plurality of second current sources outputting a plurality of second currents; a decoder converting the digital signals into a plurality of conductive communication numbers; and a plurality of first switches individually coupled to the second current sources and the grounding point a portion of the first switches is turned on in response to the conductive signals to transmit a portion of the second currents to the ground point; a second switch coupled to the node and the plurality of The two current sources are turned on in response to the injection pulse. The pulse wave correcting circuit of claim 2, further comprising: a second gate, the output pulse wave is output to the voltage controlled oscillator in the phase locked loop according to the injection pulse wave and the start signal . The pulse wave correcting circuit of claim 2, wherein when the current value of the first current is equal to the current value of the second currents, the pulse width of the injected pulse wave is equal to the corrected clock pulse. The clock cycle of the signal is multiplied by the particular ratio value. The pulse wave correcting circuit of claim 4, wherein the pulse width of the injected pulse wave is 1/4 of a period of an output signal of the phase locked loop.