JP2013016995A - Pll circuit - Google Patents

Abstract

There is a problem in that a reference spurious that leads to deterioration of characteristics of a PLL occurs due to an output current mismatch from a charge pump circuit of the PLL.
A phase comparator that outputs first and second pulse signals according to a phase difference between a reference signal and a feedback signal, and the first and second pulse signals according to a first control signal. A pulse width adjusting circuit for generating third and fourth pulse signals, each of which is adjusted, a charge pump for generating an output current in accordance with the third and fourth pulse signals, and an output of the charge pump A loop filter that converts current into voltage, a detection circuit that outputs a detection result obtained by integrating the voltage converted by the loop filter, and a control that generates the first control signal according to the detection result A PLL circuit.
[Selection] Figure 1

Description

  The present invention relates to a PLL circuit.

  PLL (Phase Locked Loop) is a technique that is also required in the field of wireless communication, and is required to suppress unnecessary frequencies other than the desired frequency. Reference spurious affects radio transmission and reception, and the reference spurious appears to be a disturbing wave in the reception system, causing a deterioration in the minimum input reception sensitivity. In the transmission system, the reference spurious becomes unnecessary radiation, and the wireless communication standard cannot be satisfied. There is.

  FIG. 19 shows a PLL circuit 501 as an example of the PLL system. The loop constituted by the PLL is a feedback circuit for adjusting the oscillation frequency Fvco of the voltage controlled oscillator (VCO) 505 in the PLL circuit 501 to a desired frequency. The phase frequency comparator (PFD) 502 detects the phase difference between the reference frequency Fref and the comparison frequency Fsig and outputs it to the charge pump (CP) 503 as an UP or DN signal. The charge pump (CP) 503 discharges or draws current according to the UP or DN signal, converts the current into a voltage by the loop filter (LPF) 504, applies the voltage to the VCO 505, and converges Fvco to a desired frequency. The discharge current here refers to the current flowing from the CP 503 to the LPF 504, and the drawing current refers to the current flowing from the LPF 504 to the CP 503.

  After the Fvco convergence, the UP and DN signals are output from the PFD 502 at the same timing (reset pulse output) with no phase difference between Fref and Fsig. At this time, as an ideal operation of the CP 503, current is discharged or drawn in accordance with the UP or DN signal, and the current sum becomes zero. In reality, however, the timing difference occurs between the source current and the source current due to the parasitic capacitance of the circuit, the difference in the driving capability of the PMOS and NMOS transistors used for the source and the source, and the process variation of the transistor. Will occur. Here, the current mismatch is a state where the current sum of one cycle does not become zero. As a result, the input voltage (Vtune) depending on the frequency of the VCO 505 varies. As a result, the voltage depending on the frequency of the VCO 505 fluctuates, and FM modulation is applied to the VCO 505, thereby causing reference spurious and degrading the characteristics of the PLL.

  The conventional technique is a technique for suppressing the overshoot generated in the output waveform and operating stably, and is the conventional technique.

  FIG. 20 is a block diagram showing a basic configuration of a conventional PLL. As shown in FIG. 20, the PLL 1 includes a phase frequency comparator (hereinafter referred to as PFD) 2, an inverter 3, a charge pump circuit 4, a low-pass filter (hereinafter referred to as LPF) 5, and a voltage controlled oscillator (hereinafter referred to as VCO) 6. And a frequency divider 6a.

  The PFD 2 compares the phase of the reference clock with the phase of the output of the frequency divider 6a, and outputs a pulse for increasing the frequency (hereinafter referred to as the UP signal) when the phase of the frequency divider output is delayed compared to the reference clock. Conversely, when the phase of the frequency divider output is advanced compared to the reference clock, a pulse for lowering the frequency (hereinafter referred to as a DN signal) is output. The UP signal inverted by the inverter 3 is used.

  The charge pump circuit 4 is connected to the LPF 5 including a resistor 5a and a capacitor 5b in the subsequent stage. When the DN signal is supplied, the charge pump circuit 4 extracts the charge from the LPF 5, and conversely, when the inverted UP signal is supplied. Is a device for supplying electric charge to the LPF 5. The pulse output from the charge pump circuit 4 is converted into a DC analog signal by the LPF 5.

  The VCO 6 is supplied with the analog signal output from the LPF 5 and outputs a signal having a constant frequency. The frequency divider 6a is composed of a counter, divides the output of the VCO 6 into 1 / N (N: an arbitrary natural number), and then supplies it to the PFD 2 as a frequency divider output.

  In this way, in the PLL1, one loop is formed by the PFD2, the charge pump circuit 4, the VCO 6, and the frequency divider 6a, and the two input signals of the PFD2 are made to have the same phase by this loop, that is, two The input signals are controlled to have the same frequency. Therefore, the output of the VCO 6 is N times the input frequency, and an arbitrary natural number times the input frequency can be obtained by arbitrarily setting the value of N.

  FIG. 21 shows the configuration of the charge pump circuit 4 of the prior art. In the figure, the conventional charge pump circuit is roughly composed of the following parts. That is, a first current mirror circuit composed of PMOS transistors 7 and 9, a second current mirror circuit composed of NMOS transistors 12 and 13, constant current sources 10 and 11, and an analog switch circuit unit 8.

  The analog switch circuit unit 8 includes transfer gates 8a and 8c made of CMOS transistors, a PMOS transistor 8b, and an NMOS transistor 8d.

  The PMOS transistor 7 has a source connected to the power supply VDD and a drain and gate connected to the constant current source 10. The PMOS transistor 9 has a source connected to the power supply VDD and a drain connected to the output of the charge pump circuit. The PMOS transistors 7 and 9 constitute a first current mirror circuit, and the transfer gate 8a and the drain of the PMOS transistor 8b are connected in series between the gates of the PMOS transistors 7 and 9.

  The source of the PMOS transistor 8b is connected to the power supply VDD, and the UP signal is input to the gate. The UPB signal (inverted UP signal) is input to the gate of the PMOS transistor of the transfer gate 8a, and the UP signal is input to the gate of the NMOS transistor of the transfer gate 8a.

  The NMOS transistor 12 has a source connected to the ground GND, a drain and a gate connected to the constant current source 11. The NMOS transistor 13 has a source connected to the ground GND and a drain connected to the output of the charge pump circuit. The NMOS transistors 12 and 13 constitute a second current mirror circuit, and the transfer gate 8c and the drain of the NMOS transistor 8d are connected in series between the gates of the NMOS transistors 12 and 13.

  The source of the NMOS transistor 8d is connected to the ground GND, and the DNB signal (inverted DN signal) is input to the gate. The DNB signal (inverted DN signal) is input to the gate of the PMOS transistor of the transfer gate 8c, and the DN signal is input to the gate of the NMOS transistor of the transfer gate 8c.

  Here, the operation of the charge pump circuit 4 will be described. When the UP and DN signals are both at the low level (L), both the transfer gates 8a and 8c are turned off, the PMOS transistor 8b and the NMOS transistor 8d are both turned on, and both the PMOS transistor 9 and the NMOS transistor 13 are turned off. It becomes. For this reason, nothing is output to the LPF 5.

  Next, when the UP signal is at a high level (H), the transfer gate 8a is turned on and the PMOS transistor 8b is turned off. Then, since the gates of the PMOS transistors 7 and 9 constituting the first current mirror circuit are electrically connected, a current corresponding to the mirror ratio of the PMOS transistors 7 and 9 flows to the PMOS transistor 9. The current is supplied to the LPF 5.

  Next, when the DN signal is at a high level (H), the transfer gate 8c is turned on and the NMOS transistor 8d is turned off. Then, since the gates of the NMOS transistors 12 and 13 constituting the second current mirror circuit are connected, a current corresponding to the mirror ratio of the NMOS transistor 12 and the NMOS transistor 13 flows to the NMOS transistor 13, Current is drawn from the LPF 5.

  As described above, in this prior art, even if the PMOS transistor 9 and the NMOS transistor 13 are turned on, the potentials on the source side of the PMOS transistor 9 and the NMOS transistor 13 do not change. Therefore, as shown in FIG. 22, an overshoot does not occur unlike the output current of the charge pump circuit of FIG.

  In addition, there exist some like patent documents 2-5 as a prior art relevant to PLL.

JP-A-11-274920 JP-A-1-202916 JP-A 61-107812 JP 62-234415 A Japanese Patent Laid-Open No. 2000-224034

  The prior art has a problem that a transient current mismatch occurs due to a difference in driving ability due to an imbalance of parasitic elements and element variations, and a reference spurious generated due to the current mismatch leads to deterioration of the characteristics of the PLL. An example is described below. For example, it is assumed that UP and DN signals having no phase difference are output from the PFD 2 as shown in FIG.

  Here, when the overshoot current is improved only by the analog switch, as shown in FIG. 26B, when the reset pulse is input, the driving capability of the PMOS transistor 9 and the NMOS transistor 13, and the PMOS transistor 8b and the NMOS transistor 8d is improved. Due to the difference, the parasitic capacitance between the transfer gate 8a and the PMOS transistor 9, the difference between the parasitic capacitance between the transfer gate 8c and the NMOS transistor 13, and the variation between the PMOS transistor 9 and the NMOS transistor 13, a transient is caused when the UP or DN signal is switched. A current mismatch occurs.

  As a result, a state occurs in which the sum of the discharge current and the pull-in current does not transiently converge to 0 as shown in FIG. This becomes a current mismatch of the charge pump circuit 4 and a reference spurious that leads to deterioration of the characteristics of the PLL.

  Specifically, since this reference spurious appears as an interference wave in the reception system, the minimum input reception sensitivity is deteriorated, and in the transmission system, the reference spurious becomes unnecessary radiation and may not satisfy the standard of wireless communication.

  The present invention provides a phase frequency comparator that outputs first and second pulse signals according to a phase difference between a reference signal and a feedback signal, and the first and second pulses according to a first control signal. A pulse width adjusting circuit for generating third and fourth pulse signals, each of which adjusts a pulse width of the signal, a charge pump for generating an output current in accordance with the third and fourth pulse signals, and A loop filter connected to the output for converting a current into a voltage, a detection circuit for outputting a detection result obtained by integrating the voltage converted by the loop filter, and generating the first control signal according to the detection result And a control circuit.

  According to the present invention, when a mismatch occurs in the output current of the charge pump, the detection circuit detects it, and a first control signal is output from the control circuit to the pulse width adjustment circuit according to the detection result. In response to the first control signal, the pulse width adjustment circuit generates third and fourth pulse signals in which the pulse widths of the first and second pulse signals are adjusted, and the charge pump generates the third and fourth pulse signals. The output current corresponding to the pulse signal is output. As a result, the occurrence of mismatch in the output current of the charge pump can be suppressed.

  According to the present invention, output current mismatch of the PLL charge pump is suppressed, and reference spurious can be reduced.

1 is a configuration of a PLL circuit according to an embodiment. 1 is a configuration of a detection circuit according to an embodiment. It is a graph for demonstrating operation | movement of the detection circuit concerning Embodiment. 3 is a configuration of a pulse width adjustment circuit according to the embodiment. 6 is a timing chart for explaining the operation of the pulse width adjustment circuit according to the exemplary embodiment. It is a table | surface which shows the operation result of the pulse width adjustment circuit concerning embodiment. 4 is an operation flowchart of the PLL circuit according to the embodiment. 4 is an operation flowchart of the PLL circuit according to the embodiment. 4 is an operation flowchart of the PLL circuit according to the embodiment. It is the schematic of CP output current spurious concerning an embodiment. It is a graph which shows the rise timing of the discharge current before the pulse adjustment concerning embodiment, and drawing-in current. It is a graph which shows the fall timing of the discharge current before the pulse adjustment concerning embodiment, and drawing-in current. It is a graph which shows the rise timing of the discharge current after the pulse adjustment concerning embodiment, and drawing-in current. It is a graph which shows the timing of the fall of the discharge current after the pulse adjustment concerning embodiment, and drawing-in current. It is a graph which shows the current sum (rise) of the discharge current before the pulse adjustment concerning embodiment, and drawing-in current. It is a graph which shows the current sum (rise) of the discharge current after the pulse adjustment concerning embodiment, and drawing-in current. It is a graph which shows the result of having performed the Fourier analysis with respect to the electric current sum of the discharge electric current before the pulse adjustment concerning embodiment, and drawing-in electric current. It is a graph which shows the result of having performed the Fourier analysis with respect to the electric current sum of the discharge current after the pulse adjustment concerning embodiment, and drawing-in current. It is a block configuration of a conventional PLL circuit. It is a block configuration of a conventional PLL circuit. The circuit configuration of the CP. It is a schematic diagram for demonstrating operation | movement of CP. It is a schematic diagram for demonstrating the problem of the conventional PLL circuit.

  BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 shows a configuration of a PLL circuit 100 according to the present embodiment. However, only a part of the PLL system of the PLL circuit 100 is shown.

  The PLL circuit 100 includes a phase frequency comparator (hereinafter referred to as PFD) 102, a pulse width adjustment circuit 103, a charge pump circuit (hereinafter referred to as CP) 101, a bias circuit 104, a loop filter (hereinafter referred to as LPF). 105, a detection circuit 106, a control circuit 107, and inverters IV108 and IV109.

  Although not shown in FIG. 1, the output CPout of the charge pump circuit 101 output via the LPF 105 is input to the VCO as in FIG. 20, and the VCO output is input to the frequency divider. Then, the output from the frequency divider (frequency is assumed to be Fsig) is input again to the PFD 102 to constitute a PLL system.

  The PFD 102 detects the phase difference between the reference frequency Fref of the input signal and the comparison frequency Fsig of the frequency divider output from the frequency divider described above, and outputs a UP1 or DN1 signal corresponding to the phase difference. When this phase difference is 0, the UP1 signal and DN1 signal having the same phase are output from the PFD 102. The pulse at this time is referred to as a reset pulse.

  The pulse width adjustment circuit 103 receives the UP1 signal and the DN1 signal from the PFD 102, performs pulse adjustment described later, and outputs the UP2 signal and the DN2 signal.

  The inverters IV108 and IV109 receive the UP2 signal and the DN2 signal, respectively, and output them as inverted UPB2 and DNB2 signals.

  The CP 101 receives the UP2 signal and the DN2 signal, and the UPB2 signal and the DNB2 signal, controls the discharge current and the drawing current in accordance with them, and outputs it as CPout. Hereinafter, for convenience, this output terminal is also referred to as CPout.

  The CP 101 includes a first current mirror circuit composed of PMOS transistors 7 and 9, a second current mirror circuit composed of NMOS transistors 12 and 13, constant current sources 10 and 11, and an analog switch circuit. Part 8. The analog switch circuit unit 8 includes transfer gates 8a and 8c made of CMOS transistors, a PMOS transistor 8b, and an NMOS transistor 8d.

  The CP 101 performs the same configuration and the same operation as the CP 4 in FIG. However, although CP4 inputs UP, DN, UPB, and DNB signals, CP101 inputs UP2, DN2, UPB2, and DNB2 signals instead of UP, DN, UPB, and DNB signals. A common node of the PMOS transistor 9 and the NMOS transistor 13 is the CPout.

  The bias circuit 104 includes a switch 104a and a constant voltage source 104b. The switch 104a is connected between CPout and the constant voltage source 104b. The constant voltage source 104b supplies a predetermined voltage, for example, 1/2 of a power supply voltage (hereinafter referred to as VDD) to CPout when the switch 104a is in an on state. The on / off state of the switch 104a is controlled in accordance with a control signal 174 from the control circuit 107.

  The LPF 105 is connected to CPout. Since the LPF 105 performs the same configuration and the same operation as the LPF 5 of FIG. 21, description thereof is omitted here.

  The detection circuit 106 outputs a detection output signal 171 according to the input CPout. FIG. 2 shows the configuration of the detection circuit 106. As shown in FIG. 2, a buffer (hereinafter referred to as BUF) 201, an integration circuit 202, an analog-digital converter (hereinafter referred to as ADC) 203, a bias circuit 204, and a reset switch 205 are included.

  The BUF 201 inputs the output CPout of the CP 101 as the input signal 211. The BUF 201 buffers the input signal 211 and outputs an output signal 212 to the integration circuit 202. The integration circuit 202 integrates the output signal 212 of the BUF 201 and outputs the calculated result to the ADC 203 as an integration result signal 213. The ADC 203 converts the integration result signal 213 into a digital signal (code) and outputs it as a detection output signal 171. Since the ADC 203 needs to set a common code (comparison code) for the analog-digital conversion operation, the bias signal 215 is input to the ADC 203 for determining the common code. When the reset signal 172 is input from the control circuit 107, the reset switch 205 is turned on, the input signal (BUF201 output signal 212) of the integration circuit 202 is set to the same potential as the bias signal 215, and the detection circuit 106 is reset. Perform the action.

  An example of the operation of the detection circuit 106 is shown in FIG. First, CPout is input to the detection circuit 106, and voltage fluctuation caused by the current mismatch of CP 101 and the current-voltage conversion of the LPF 105 is input to the integration circuit 202 via the BUF 201. Since the output of the integration circuit 202 is a value corresponding to the current mismatch of CP101, the larger the current mismatch of CP101, the greater the difference from CPout of the initial node. Since the output of the integration circuit 202 increases with time, a certain detection time, for example, the time t1 in FIG. 3 is set, and the output of the integration circuit 202 at that time is converted into a digital signal (code) by the ADC 203. To do.

  The control circuit 107 outputs a control signal 173 to the pulse width adjustment circuit 103 in response to the detection output signal 171. With this control signal 173, the pulse width adjustment circuit 103 sets the delay amount of the UP2 signal and the DN2 signal and the adjustment of the rise and fall. Further, when the reset operation of the detection circuit 106 is performed, a reset signal 172 is output to the detection circuit 106. Further, a control signal 174 is output to the switch 104a of the bias circuit 104 to control on / off of the switch 104a.

  FIG. 4 shows the configuration of the pulse width adjustment circuit 103. As shown in FIG. 4, the pulse width adjustment circuit 103 includes delay circuits 301 and 302, AND circuits 303 and 304, OR circuits 305 and 306, and selectors 307 and 308. Note that the pulse width adjustment circuit 103 has two circuits, an UP1 signal input side 103a and a DN1 signal input side 103b. FIG. 4 shows a circuit on the UP1 signal input side. Since the configuration of the DN1 signal input side 103b is the same as that of the UP1 signal input side 103a, description thereof is omitted here. The delay circuit 301, the AND circuit 303, the OR circuit 305, and the selector 307 constitute the first stage, and the delay circuit 302, the AND circuit 304, the OR circuit 306, and the selector 308 are the second stage. Configure.

  The delay circuit 301 gives a delay amount Td1 to the signal 321 that is the UP1 signal input at the first stage, and outputs it as a signal 322. The AND circuit 303 inputs the signal 321 having no delay to one terminal and the signal 322 having the delay to the other terminal. The OR circuit 305 also inputs the signal 321 to one terminal and the signal 322 to the other terminal. The selector 307 selects the output of the AND circuit 303 or the OR circuit 305 according to the selection control signal 341. The signal selected by the selector 307 is output from the selector 307 as the first stage output signal 323.

  The delay circuit 302 gives a delay amount Td 2 to the signal 323 output from the selector 307 and outputs it as a signal 324. The AND circuit 304 inputs the signal 323 having no delay to one terminal and the signal 324 having the delay to the other terminal. The OR circuit 305 also inputs the signal 323 to one terminal and the signal 324 to the other terminal. The selector 308 selects the output of the AND circuit 304 or the OR circuit 306 according to the selection control signal 342. The signal selected by the selector 308 is output from the selector 308 as an output signal from the second stage (an output signal UP2 signal of the pulse width adjustment circuit 103).

  The delay circuits 301 and 302 can adjust the amount of delay added to the signal according to the delay adjustment signals 343 and 344, respectively. For example, when the timing of the discharge current of CP 101 matches the timing of the pull-in current, the delay circuits 301 and 302 are set to the through mode according to the delay adjustment signals 343 and 344 in the control signal 173 output from the control circuit 107, that is, The delay amounts Td1 and Td2 are set to 0.

  On the other hand, when the timing of the discharge current of CP 101 does not match the timing of the drawing current, the delay times Td1 and Td2 are varied in accordance with the delay adjustment signals 343 and 344 and input to the AND circuit or OR circuit of each stage. As a result, the rise and fall timings and pulse widths of the UP2 signal and DN2 signal output from the pulse width adjustment circuit 103 are adjusted.

  Note that the pulse width adjustment circuit 103 is not limited to the circuit configuration in FIG. 4, and may have other circuit configurations as long as the timing of the rise and fall of the pulse can be adjusted.

  FIG. 5 shows an example of an operation timing chart of the pulse width adjustment circuit 103 in FIG. The delay time set by the delay circuit 301 by the delay adjustment signal 343 is Td1, and the delay time set by the delay circuit 302 by the delay adjustment signal 344 is Td2. Further, in the following example, it is assumed that the UP1 signal is input, but the same adjustment is possible even with the DN1 signal.

  First, consider the case where the selector 307 selects the output of the OR circuit 305 in the first stage. In this case, the OR circuit 305 receives the UP1 signal (signal 321) and the signal 322 obtained by delaying the UP1 signal by the period Td1. The OR circuit 305 outputs a high level when either the UP1 signal or the signal 322 is at a high level. Therefore, the OR circuit 305 outputs a signal whose trailing edge is delayed by Td1 compared to the UP1 signal. The output of the OR circuit 305 is input to the second stage as a signal 323.

  In the second stage, a signal 323 and a signal 324 obtained by delaying the signal 323 by a period Td2 are input to the OR circuit 306. The OR circuit 306 outputs a high level when either the signal 323 or the signal 324 is at a high level. Therefore, the OR circuit 306 outputs a signal whose trailing edge is delayed by Td1 + Td2 compared to the UP1 signal. When the selector 308 selects the output of the OR circuit 306, this signal is output from the pulse width adjustment circuit 103 as the UP2 signal.

  In the second stage, the AND circuit 304 also receives the signal 323 and the signal 324 obtained by delaying the signal 323 by the period Td2. The AND circuit 304 outputs a high level when both the signal 323 and the signal 324 are at a high level. For this reason, the AND circuit 304 outputs a signal whose rising edge is delayed by Td2 and falling edge is delayed by Td1 compared to the UP1 signal. When the selector 308 selects the output of the AND circuit 304, this signal is output from the pulse width adjustment circuit 103 as the UP2 signal.

  On the other hand, consider the case where the selector 307 selects the output of the AND circuit 303 in the first stage. In this case, the AND circuit 303 receives the UP1 signal (signal 321) and the signal 322 obtained by delaying the UP1 signal by the period Td1. The AND circuit 303 outputs a high level when both the UP1 signal and the signal 322 are at a high level. Therefore, the AND circuit 303 outputs a signal whose rising edge is delayed by Td1 compared to the UP1 signal. The output of the AND circuit 303 is input to the second stage as a signal 323.

  In the second stage, a signal 323 and a signal 324 obtained by delaying the signal 323 by a period Td2 are input to the OR circuit 306. The OR circuit 306 outputs a high level when either the signal 323 or the signal 324 is at a high level. Therefore, the OR circuit 306 outputs a signal whose rising edge is delayed by Td1 and falling edge is delayed by Td2 compared to the UP1 signal. When the selector 308 selects the output of the OR circuit 306, this signal is output from the pulse width adjustment circuit 103 as the UP2 signal.

  In the second stage, the AND circuit 304 also receives the signal 323 and the signal 324 obtained by delaying the signal 323 by the period Td2. The AND circuit 304 outputs a high level when both the signal 323 and the signal 324 are at a high level. Therefore, the AND circuit 304 outputs a signal whose rising edge is delayed by Td1 + Td2 compared to the UP1 signal. When the selector 308 selects the output of the AND circuit 304, this signal is output from the pulse width adjustment circuit 103 as the UP2 signal.

  FIG. 6 summarizes the relationship between the rising delay and falling delay of the UP2 signal output from the pulse width adjustment circuit 103 with respect to Up1, by combining the above-described first and second stage logic circuits (OR, AND). A table is shown.

  As shown in FIG. 6, when the OR circuit 305 is selected in the first stage and the OR circuit 306 is selected in the second stage, the rising delay is 0 and the falling delay is Td1 + Td2 compared to the UP1 signal. When the OR circuit 305 is selected in the first stage and the AND circuit 304 is selected in the second stage, the UP2 signal has a rising delay Td2 and a falling delay Td1 compared to the UP1 signal. When the AND circuit 303 is selected in the first stage and the OR circuit 306 is selected in the second stage, the UP2 signal has a rising delay Td1 and a falling delay Td2 compared to the UP1 signal. When the AND circuit 303 is selected in the first stage and the AND circuit 304 is selected in the second stage, the UP2 signal has a rising delay of Td1 + Td2 and a falling delay of 0 compared to the UP1 signal.

  The UP2 signal and DN2 signal adjusted as described above are output from the pulse width adjustment circuit 103, and the CP 101 receives the UP2 signal, DN2 signal and the UPB2 signal and DNB2 signal which are inverted signals, and the subsequent stages according to them. A pull-in current or a discharge current is generated from the LPF 105 connected to the.

  The detection circuit 106 detects these current mismatches, and outputs the detection result to the control circuit 107 as a detection output signal 171, and the control circuit 107 outputs the control signal 173 to the pulse width adjustment circuit 103 accordingly. . For example, when the timing of the discharge current of CP 101 matches the timing of the pull-in current (no mismatch), the delay times Td1 and Td2 are 0, so the UP2 signal and DN2 signal are the same as the UP1 signal and DN1 signal. Become.

  Hereinafter, the pulse width adjustment operation performed by the PLL circuit 100 will be described. FIG. 7 shows an operation flowchart of this pulse width adjustment. As shown in FIG. 7, as the calibration of the pulse width adjustment, two-stage operations including preparation for pulse width adjustment and execution of pulse width adjustment are performed. As a pulse width adjustment preparation stage, first, the bias circuit 104 connected to CPout is turned on by the control signal 174, and CPout is set to VDD / 2 (step S1).

  Next, the ADC 203 of the detection circuit 106 sets the common code to a code corresponding to VDD / 2 and sets it as a reference code (step S2). Further, in order to output the UP1 and DN1 signals in the same phase (reset pulse output), signals are input to the PFD 102 so that Fref and Fsig substantially coincide (step S3). Specifically, an external circuit of the PLL circuit 100 may be configured so that signals having the same frequency and the same phase are input to Fref and Fsig.

  Next, as a pulse width adjustment execution stage, first, the control circuit 107 varies the delay time set by the pulse width adjustment circuit 103. The delay time adjustment of the delay circuits 301 and 302 of the pulse width adjustment circuit 103 is performed by varying the delay time in each circuit. At this time, the detection circuit 106 takes in the reset signal 172 from the control circuit 107 in order to reset the detection circuit 106 every time the delay time is varied (step S4).

  Next, the current mismatch amount output from CPout is converted into a voltage by the LPF 104, and code conversion is performed by the ADC 203 of the detection circuit 106 (step S5). Then, the detected code is compared with the common code (step S6). A more detailed flow of steps S4 and S5 is shown in FIG.

  As shown in FIG. 8, when pulse adjustment is started in step S4 (step S41), first, the logic of the first stage of the pulse width adjustment circuit 103 is set to one of the AND circuit 303 and the OR circuit 305, and 2 The logic of the stage is determined as either the AND circuit 304 or the OR circuit 306 (step S42). In the circuit configuration example of FIG. 4, there are four combinations of logic in the first and second stages. Next, the delay amount (delay time) of the first-stage delay circuit 301 of the pulse width adjustment circuit 103 and the delay amount (delay time) of the second-stage delay circuit 302 are set. The delay time of Td1 and Td2 is varied to adjust the rise and fall times of the pulse.

  Next, in step S <b> 5, the current output of the CP 101 is voltage-converted by the LPF 105. The detection circuit 106 integrates the input voltage for a certain period of time, converts it into a code by the ADC 203, and outputs it to the control circuit 107 (step S51). The control circuit 107 stores the code (step S52). After storing the code, the control circuit 107 resets the detection circuit 106 (step S53).

  When the combination of the first-stage logic and the second-stage logic (four patterns in this example) of the pulse width adjustment circuit 103 is completed (YES in step S54), the process proceeds to step S6 described above. On the other hand, if all combinations of the first-stage logic and the second-stage logic of the pulse width adjustment circuit 103 have not been completed (NO in step S54), the process returns to step S42 to set another logic combination.

  Finally, after detecting the code for each set delay condition (combination of logic and delay time), the code closest to the common code is selected as the optimum value (step S7). As a result, by selecting the ADC 203 code closest to the common code as the optimum value and setting the pulse width adjustment circuit 103 under the selected code condition, the current mismatch output by the CP 101 is minimized.

  Here, with reference to FIG. 9, the flow of determining the logic combination of the first and second stages of the pulse width adjusting circuit 103 performed in steps S42 and S43 and determining the delay time will be described. As shown in FIG. 9, first, in step S42, the first and second logic combinations of the pulse width adjustment circuit 103 are both set as OR circuits (OR circuits 305 and 306).

  Next, in step S43, the delay time of the first and second stages of the pulse width adjustment circuit 103 is set. Here, in this example, the delay time of the second stage is fixed at Td2-1, and the delay time of the first stage is changed in steps from Td1-1 to Td1-M. However, “M” is the total number that can be varied from Td1. Then, the delay time of the first stage is fixed at Td1-1, and the delay time of the second stage is changed in steps from Td2-1 to Td2-N. However, “N” is the total number that can be changed from Td2. In the above example, the Td1-1 and Td2-1 are changed to decrease toward Td1-M and Td2-N, respectively. However, the increase may be reversed.

  When all the above-described delay time settings are completed when the first and second stage logic combinations are OR circuits 305 and 306, the first stage logic is replaced with the AND circuit 303 and the second stage logic. The OR circuit 306 is used. After that, as described above, the delay time of the first and second stages of the pulse width adjustment circuit 103 is set, and when that is finished, a different combination of the first and second stages of logic is selected. This operation is performed for all combinations of the first and second stage logics of the pulse width adjustment circuit 103.

  With the operation as described above, the PLL circuit 100 according to the present embodiment uses the pulse width adjustment circuit to supply the UP2 and DN2 signals adjusted in the rise and fall timings and the pulse width of the UP1 and DN1 signals output from the PFD 102. 103 generates. With these UP2 and DN2 signals, the CP 101 can match the discharge current and the pull-in current, and can reduce the current mismatch. As a result, the PLL circuit 100 of the present embodiment can have an effect of reducing the reference spurious generated due to the CP101 current mismatch generated in the PLL.

  The reason for the above effect will be described below. First, FIG. 10 shows a schematic diagram of CP output current spurious. 10 indicates that the CP output current Ip (n) depends on the spurious frequency characteristics of the CP output current. The relational expression showing the influence on the reference spurious is shown below.

First, the output voltage fluctuation Vp (n) due to the CP output current spurious is obtained. Note that s = 2πfr (n).

より、Ｖｐ（ｎ）は以下のような式となる。

here,

Accordingly, Vp (n) is expressed as follows.

  From this result, it can be seen that Ip (n) depends on Vp (n).

  Next, the relationship between Ip (n) and reference spurious Spurious (n) is shown below.

リファレンススプリアスは、

The modulation coefficient β is

The reference spur is

となる。ここで、Ｖｐ（ｎ）：Ｖｔｕｎｅ電圧振幅［Ｖｐ］、Ｉｐ（ｎ）：ＣＰ出力電流［Ａ］、Ｚ（ｓ）：ＬＰＦインピーダンス［Ω］、β：変調係数、ｆｒ：リファレンス周波数［Ｈｚ］、ＫＶ：ＶＣＯ変調感度［Ｈｚ／Ｖ］、Ｑ：電荷［ｑ］、Ｃｆ：ＬＰＦ容量［Ｆ］である。 Further, from the principle of FM modulation, from the relationship of V = Q / C, it is Q / Cf∝Ip / Cf∝Ip / fr. Therefore, Vp∝Ip / fr, and when substituting into the equation (1),

It becomes. Here, Vp (n): Vtune voltage amplitude [Vp], Ip (n): CP output current [A], Z (s): LPF impedance [Ω], β: modulation coefficient, fr: reference frequency [Hz] , KV: VCO modulation sensitivity [Hz / V], Q: charge [q], Cf: LPF capacity [F].

  From equation (1), by reducing the CP current spurious, the spurious due to the CP current mismatch factor theoretically improves by 20 dB / dec.

  From the above equation, the CP current spurious greatly depends on the CP current mismatch. Expressions (1) and (2) indicate that the results of Vtune fluctuation and current spurious are equivalent.

  From this result, it is understood that the reference spurious due to the CP can be suppressed by suppressing the CP current spurious. Since the transient CP current mismatch occurs due to a difference in the timing of rising and falling of the discharge current and the drawing current, it is possible to reduce the reference spurious by mitigating these differences.

  11 to 18 show the simulation results of the CP output current spurious. The simulation is performed using a model in which a subcircuit model such as a parasitic element is applied to a transistor or a passive element, not an ideal model. The CP 101, PFD 102, pulse width adjustment circuit 103, detection circuit 106, bias circuit 104, and LPF 105 are configured at a transistor level, and the control circuit 107 is an ideal model.

  FIG. 11 shows the rise timing of the discharge current and the pull-in current before the pulse adjustment, and FIG. 12 shows the fall timing of the discharge current and the pull-in current before the pulse adjustment. On the other hand, FIG. 13 shows the rise timings of the discharge current and the draw current after the pulse adjustment, and FIG. 14 shows the fall timings of the discharge current and the draw current after the pulse adjustment.

  Comparing FIG. 11 (before pulse adjustment) and FIG. 13 (after pulse adjustment), the difference in the rise timing of the discharge current and the pull-in current after pulse adjustment shown in FIG. 13 (for example, A2 in the figure) is shown in FIG. It turns out that it is improving rather than the pulse adjustment shown (for example, A1 in the figure). Similarly, when FIG. 12 (before pulse adjustment) is compared with FIG. 14 (after pulse adjustment), the difference in the fall timing of the discharge current and the pull-in current after pulse adjustment shown in FIG. It can be seen that this is an improvement over that before the pulse adjustment shown in FIG.

  FIG. 15 shows the current sum (rising) of the discharge current and the drawing current before the pulse adjustment, and FIG. 16 shows the current sum (falling) of the discharging current and the drawing current after the pulse adjustment. Comparing FIG. 15 (before pulse adjustment) and FIG. 16 (after pulse adjustment), it can be seen that the sum of the discharge current and the draw current is also improved after the pulse adjustment than before the pulse adjustment.

  FIG. 17 shows the result of Fourier analysis for the sum of the discharge current and the pull-in current before pulse adjustment, and FIG. 18 shows the result of Fourier analysis for the sum of the discharge current and the pull-in current after pulse adjustment. Results are shown. Comparison of FIG. 17 and FIG. 18 shows that the current at the frequency of Fref × 1, which affects the reference spurious, is reduced to about 1/10 before and after the pulse adjustment. Here, from Equation (2), Superior (1) = 20 × log (0.55 / 0.534) = − 19.7 dB, so that the current spurious is reduced to 1/10, which is caused by the CP current. It can be seen that the reference spurious is reduced by about 19.7 dB. From the above results, it is shown that the reference spurious can be reduced by reducing the current mismatch by adjusting the timing of rising and falling of the CP discharge current and the drawing current.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

100 PLL circuit 101 Charge pump circuit 102 Phase frequency comparator 103 Pulse width adjustment circuit 104 Bias circuit 105 Loop filter 106 Detection circuit 107 Control circuit 301, 302 Delay circuit 303, 304 AND circuit 305, 306 OR circuit 307, 308 Selector 201 Buffer Circuit 202 Integration circuit 203 Analog-to-digital converter 204 Bias circuit 205 Reset switch

Claims (5)

A phase comparator that outputs first and second pulse signals according to the phase difference between the reference signal and the feedback signal;
A pulse width adjusting circuit for generating third and fourth pulse signals, each of which adjusts the pulse width of the first and second pulse signals in accordance with a first control signal;
A charge pump for generating an output current in response to the third and fourth pulse signals;
A loop filter connected to the output of the charge pump for converting current to voltage;
A detection circuit that outputs a detection result obtained by integrating the voltage converted by the loop filter;
And a control circuit that generates the first control signal according to the detection result. In the control circuit, when the first and second pulse signals are output from the phase comparator in the same phase, the timings of the discharge current from the charge pump and the pull-in current coincide with each other. 2. The PLL circuit according to claim 1, wherein the first control signal is output so that a pulse width adjustment circuit generates the pulse signal. The detection circuit includes:
An integrating circuit for integrating the output voltage of the loop filter;
An analog-to-digital converter that converts the voltage value integrated by the integration circuit into a digital code and outputs the detection result, and
2. The PLL circuit according to claim 1, wherein the analog-digital converter converts a voltage value integrated by the integration circuit after a predetermined period from a common mode of an output initial value of the charge pump into a digital code. A bias circuit connected to the output of the charge pump;
The PLL circuit according to claim 3, wherein the bias circuit supplies a predetermined voltage in a common mode of an initial output value of the charge pump. The PLL circuit according to claim 4, wherein the predetermined voltage is substantially ½ of a power supply voltage.

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