TWI538117B - Semiconductor package - Google Patents

Description

Semiconductor package

The present invention relates to a semiconductor package, and more particularly to a semiconductor package in which a semiconductor wafer is disposed on an upper portion of a substrate PCB and solder balls are formed on a lower portion of the substrate PCB.

As an example of a conventional semiconductor package, a semiconductor package 1 shown in FIG. 1 in which a semiconductor wafer 12 is molded of an epoxy resin or the like can be exemplified. In Fig. 1, reference numeral 10 is a molded portion.

When the semiconductor package 1 of FIG. 1 does not employ the substrate PCB 14, it is difficult to arrange the solder balls 16. Thus, in order to mount (mount) the semiconductor package 1 on a test board (PCB; illustration) or the like, the PCB is used as an intermediate medium, and for example, solder balls 16 are soldered. Here, the PCB functioning as an intermediate medium is referred to as a substrate PCB (Substrate PCB) 14.

Accordingly, the semiconductor wafer 12 is electrically contacted with the substrate PCB 14 by various methods, and the substrate PCB 14 functions as a medium capable of soldering a PCB (not shown) actually assembled in the semiconductor package 1.

When such a conventional semiconductor package is mounted on a PCB, it is mounted on a surface of the test board PCB 18 as shown in FIG. In FIG. 2, reference numeral 22 is a connecting line between the solder ball 16 and the PI characteristic improving device 20.

Further, it is known that a PI (Power Integrity) characteristic improving device (for example, a capacitor) 20 is provided under the PCB 18.

Therefore, since the semiconductor package 1 and the PI characteristic improving device 20 have an interval (L1 in FIG. 2) corresponding to the thickness of the PCB 18, the higher the speed of the semiconductor, the more It has the disadvantage of being poor in signal transmission and power transmission.

That is, in Fig. 2, the longer the line length L1, the larger the impedance value (R+j ω L) that hinders the signal transmission, thereby attenuating the signal transmission gain and delaying the time required for signal transmission, which becomes a factor hindering the quick response. Moreover, even if the line length is the same, when the frequency of use increases, the impedance value caused by the inductor rises, which also causes an increase in signal transmission loss. In particular, in a high-speed semiconductor of 600 MHz or more, as shown in FIG. 2, the line length L1 is long, and power cannot follow the speed, which causes a decrease in PI (Power Integrity) characteristics.

As such, PI characteristics are closely related to line length in high speed semiconductors. Accordingly, in order to shorten the line length, the PI characteristic improving device 20 is disposed in the vicinity of the semiconductor package 1. Thus, a proposal is made to assemble the PI characteristic improving device 20 on the upper surface of the PCB 18 independently of the semiconductor package 1.

When the PI characteristic improving device 20 is mounted on the upper surface of the PCB 18 independently of the semiconductor package 1, the line length between the semiconductor package 1 and the PI characteristic improving device 20 becomes shorter than in the case of being mounted under the PCB 18. The PI characteristics are improved.

However, even in the case where the PI characteristic improving device 20 and the semiconductor package 1 are independently mounted on the upper side of the PCB 18, the PI characteristic improving device 20 can only be located in the outer region of the mounting region of the semiconductor package, and thus in the semiconductor and PI characteristics. There is still a distance between the improved devices corresponding to the line length L1 in Fig. 2, and as a result, the limit frequency is reached. When the limit frequency is reached, the same problem as in the related art arises due to the line length between the semiconductor package 1 and the PI characteristic improving device 20.

Further, in the aspect in which the PI characteristic improving device 20 and the semiconductor package 1 are mounted on the upper surface of the PCB 18 independently, since the PI characteristic improving device 20 occupies the mounting area, it is difficult to mount other required devices. That is, the arrangement in which the PI characteristic improving device 20 is mounted on the upper surface of the PCB 18 independently of the semiconductor package 1 is compared with the case where the PI characteristic improving device 20 is mounted on the lower surface of the PCB 18, which results in assembly on the upper surface of the PCB 18. The problem of the area of the device (excluding the device for improving PI characteristics) is reduced.

Korean Public Patent Gazette No. 10-2010-0119676

The present invention has been made in view of the above conventional problems, and an object thereof is to provide a semiconductor package in which a device for improving a PI characteristic is incorporated, whereby PI characteristics can be further improved.

Furthermore, it is another object of the present invention to mount the above-described semiconductor package on a substrate PCB, thereby eliminating the problem of shrinking the area of the test board PCB for other required device assembly.

In order to achieve the above object, a semiconductor package of a preferred embodiment of the present invention includes a semiconductor wafer including: a substrate PCB electrically connected to the semiconductor wafer through a dielectric to form a power supply power layer; and power integrity characteristics The improving device is provided between the semiconductor wafer and the power supply power layer, and is provided on a surface of the power supply power layer in a region other than the region in which the dielectric is formed, and is Power layer electrical connection.

A semiconductor package according to another preferred embodiment of the present invention includes a semiconductor wafer including: a substrate PCB having a semiconductor wafer connected thereto via a dielectric, and a power supply power layer is formed; and power integrity a feature improving member disposed on another surface of the substrate PCB and disposed in an area other than an area where the dielectric is disposed for electrical connection when the substrate PCB is mounted on the test board PCB, the power integrity The characteristic improving element is electrically connected to the power supply power layer.

The power layer is formed into a shape in which one or more sub power layers are laminated, and a power supply conductive layer is patterned on the one or more sub power layers; and the power integrity characteristic improving element penetrates the power layer And obtaining power from the power layer through vias (electrical connection channels or vias) electrically connected to one or more of the conductive layers.

According to the invention constructed as above, the power integrity (PI) feature improving component is mounted on the bottom surface of the substrate PCB to improve power integrity characteristics. A power supply power supply layer for supplying power to the element is provided inside the semiconductor package.

The power integrity characteristics can be improved when the power integrity characteristic improving component is located outside the semiconductor package while being placed inside the semiconductor package (ie, the bottom surface of the substrate PCB). In particular, the size of the semiconductor package can be optimized by providing a power integrity characteristic improving component in an available area.

Further, there is no need to additionally allocate a space for setting the power integrity characteristic improving element outside the semiconductor package as compared with the related art. In this way, even when the power integrity characteristic improving element is provided outside the semiconductor package, even in the case of a high-speed semiconductor of 600 MHz or more, the PI (Power Integrity) characteristic can be sufficiently prevented from deteriorating.

Further, the power integrity characteristic improving element is provided between the semiconductor wafer and the power supply power layer. Thereby, both the power integrity characteristics can be improved and the size of the semiconductor package can be optimized.

Further, a power integrity characteristic improving element is provided inside the semiconductor package. Thereby, since the device mounting region is enlarged as compared with the conventional method in which the power integrity characteristic improving member is disposed on the PCB, it is possible to easily assemble other required devices and to assemble more devices.

1‧‧‧Semiconductor package

10‧‧‧Molding Department

12‧‧‧Semiconductor wafer

14‧‧‧Substrate PCB

16,36‧‧‧ solder balls

18‧‧‧PCB

20‧‧‧Power Integrity Improvement Components

30‧‧‧Power supply power layer

31‧‧‧The first sub-power layer

32‧‧‧Second sub-power layer

33‧‧‧ third sub-power layer

34‧‧‧ fourth sub-power layer

41~50‧‧‧Electrical connection channel (via) (or through hole)

41a~50a‧‧‧land (or pad)

41b~46b‧‧‧land (or pad)

51‧‧‧ first hole

52‧‧‧second hole

310‧‧‧First sub-conducting layer

320‧‧‧Second sub-conducting layer

330‧‧‧The third sub-conducting layer

340‧‧‧ fourth sub-conducting layer

FIG. 1 is a view showing an example of a conventional semiconductor package.

FIG. 2 is a view for explaining a problem of a conventional semiconductor package.

Fig. 3 is a view showing a semiconductor package structure of a first embodiment of the present invention.

Fig. 4 is a view showing a state of a bottom surface of Fig. 3;

Fig. 5 is a view showing a semiconductor package structure of a second embodiment of the present invention.

Figure 6 is a perspective view of Figure 5.

Fig. 7 is a view for explaining in detail the power supply layer for power supply shown in Fig. 5;

Fig. 8 is a cross-sectional view taken along line A-A of Fig. 7;

9A to 9C are views showing one power layer in which a plurality of conductive layers are formed.

Hereinafter, a semiconductor package of an embodiment of the present invention will be described below with reference to the drawings. Before the present invention is described in detail, it should be emphasized that the terms or vocabulary in the specification and claims of the following description should not be construed as a general or lexical meaning. Therefore, the embodiments described in the present specification and the configurations shown in the drawings are merely preferred embodiments of the present invention, and do not represent the entire technical idea of the present invention. Therefore, in the present application, there may be a substitute for these configurations. A variety of equivalents and variations.

(First Embodiment)

3 is a view showing a semiconductor package structure according to a first embodiment of the present invention, and FIG. 4 is a view showing a state of a bottom surface of FIG. 3. In the components of the first embodiment, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted.

The semiconductor package of the first embodiment includes a semiconductor wafer 12.

The semiconductor wafer 12 is molded by an epoxy resin or the like, and a portion where the semiconductor wafer 12 is molded is referred to as a molded portion 10. A variety of semiconductors (e.g., memory) may be included within the semiconductor wafer 12. Depending on the purpose, the semiconductor within the semiconductor wafer 12 performs various functions and should be supplied with power to the semiconductor to enable it to perform the corresponding functions. To this end, the semiconductor wafer 12 requires at least one or more power sources. For example, it can be divided into a normally-on power supply and a data input/output power supply (speed is faster than a normally-on power supply). Semiconductor wafer 12 may also be referred to as a wafer.

The semiconductor wafer 12 is mounted on the upper surface of the power supply power layer 30 of the substrate PCB 14 . Further, a power supply power layer 30 is formed on the upper portion of the substrate PCB 14. In the first embodiment, the power layer 30 is composed of four sub power layers 31, 32, 33, 34 which are configured in a laminated shape. The four sub power layers 31, 32, 33, 34 are the same as the sub power layers in the second embodiment which will be described later, and therefore are replaced with the description relating to the second embodiment which will be described later.

The first embodiment is characterized in that a power integrity (PI) feature improving component (for example, a capacitor) 20 is mounted on the bottom surface of the substrate PCB 14. Then, A power supply power layer 30 for supplying power to the power integrity characteristic improving element 20 is provided inside the corresponding semiconductor package.

The higher the speed of the semiconductor, the more closely the power is related to the length of the line (power cable). The power integrity characteristic improving component 20 is preferably located as close as possible to the semiconductor package. Therefore, as the first embodiment of the present invention, when the power integrity characteristic improving element 20 is placed inside the semiconductor package (i.e., the bottom surface of the substrate PCB 14), the semiconductor package and the power integrity characteristic can be improved to the utmost. The distance between the elements 20 is thus the most effective in improving the power integrity characteristics.

In the first embodiment, the power supply power layer 30 and the substrate PCB 14 are composed of the same material. In order to facilitate the understanding of the drawings, the power supply power layer 30 and the substrate PCB 14 shown in the drawing are different from each other, but a four-layer power supply of the same material as that of the substrate PCB 14 is substantially laminated on the upper portion of the substrate PCB 14. The power layer 30 is used. That is, it is possible to be regarded as a whole in appearance.

Solder balls 16 are formed on the bottom surface of the substrate PCB 14. The solder ball is an example of a dielectric between the substrate PCB and an external device (for example, a test board PCB), and a plurality of dielectric materials such as bumper bonding or conductive wire bonding may be used in addition to the solder balls.

The power integrity characteristic improving member 20 is provided in the bottom surface of the substrate PCB 14 except for the region in which the dielectric is located (i.e., the usable region).

By arranging the power integrity characteristic improving member 20 in an available region in the bottom surface of the substrate PCB 14, the size of the corresponding semiconductor package can be optimized.

Of course, the size (i.e., thickness) of the power supply layer 30 may be slightly larger than that of the conventional semiconductor package. However, even if the power supply power layer 30 is formed, the substrate PCB of the present invention having the power supply power layer can be formed with the same thickness as the thickness of the conventional substrate PCB, and even if the power supply layer is used for power supply, the present invention The thickness of the semiconductor package is slightly larger than the thickness of conventional semiconductor packages, due to the assembly of higher-profile devices (such as tantalum capacitors) on the PCB. Therefore, it is not a big problem to increase the size slightly.

Further, it is not necessary to additionally allocate the installation space of the power integrity characteristic improving element 20 outside the semiconductor package as compared with the related art. Further, compared with the case where the power integrity characteristic improving element is provided outside the semiconductor package, the distance between the semiconductor wafer and the power integrity characteristic improving element is shortened, and even in the case of a high speed semiconductor of 600 MHz or more, it is sufficient. Prevents the degradation of PI (Power Integrity) characteristics.

Further, in the first embodiment, the power supply power layer 30 may be formed on the bottom surface of the substrate PCB 14, and the circuit of the power supply power layer 30 may be in contact with the solder ball 16. This is because the electrical connection between the power layer 30 and the power integrity characteristic improving element 20 can be realized even if the power supply power layer 30 is formed on the bottom surface of the substrate PCB 14 .

(Second embodiment)

Fig. 5 is a view showing a structure of a semiconductor package according to a second embodiment of the present invention, and Fig. 6 is a perspective view of Fig. 5. Among the constituent elements of the second embodiment, the same constituent elements as those of the above-described first embodiment are denoted by the same reference numerals.

In the semiconductor package of the second embodiment, the semiconductor wafer 12 is mounted on the upper surface of the power supply power layer 30 of the substrate PCB 14 via the solder balls 36. Wherein the solder ball is an example of a dielectric for realizing electrical connection between the semiconductor wafer and the substrate PCB 14 , and the electrical connection can be realized by bumper bonding or conductive wire bonding in addition to the solder ball (in the first embodiment, the semiconductor wafer is also connected through the dielectric) The substrate PCB has a small interval as compared with the second embodiment, and therefore the illustration of the dielectric and the interval is omitted.

In the second embodiment, the power integrity characteristic improving member 20 is disposed between the semiconductor wafer 12 and the substrate PCB 14. In other words, the power integrity characteristic improving element 20 is mounted on the upper surface of the power supply power layer 30, and is disposed in the remaining area (i.e., the usable area) except the area in which the dielectric solder balls 36 are formed. By providing the power integrity characteristic improving member 20 in an available region between the semiconductor wafer 12 and the substrate PCB 14, the size of the corresponding semiconductor package can be optimized. And, as needed A spacer (not shown) for reliably ensuring the arrangement interval of the dielectric or power integrity characteristic improving element 20 may be provided between the semiconductor wafer and the substrate PCB.

Similarly to the substrate PCB of the first embodiment, the substrate PCB 14 of the second embodiment includes the power supply power layer 30. More preferably, the power supply power layer 30 included in the substrate PCB 14 of the second embodiment is also provided on the upper surface of the substrate PCB 14, so that the power supply power layer 30 is brought close to the semiconductor wafer and the power integrity characteristic element.

The semiconductor package of the second embodiment does not need to additionally allocate the installation space of the power integrity characteristic improving element 20 outside the semiconductor package as compared with the conventional semiconductor package. Moreover, the distance between the semiconductor wafer and the power integrity characteristic improving element is shortened not only in the semiconductor package of the first embodiment but also in the case of a high-speed semiconductor of 600 MHz or more. Prevent PI (Power Integrity) characteristics from degrading.

Next, the power supply power layer 30 will be described in more detail. The power layer 30 of the first embodiment and the power layer 30 of the second embodiment are constructed of the same material in the same configuration. The description of the power layer 30 to be described later can also be understood as an explanation of the power layer 30 of the first embodiment. Fig. 7 is a view for explaining in detail the power supply layer for power supply shown in Fig. 5;

The power supply power layer 30 is configured in a shape in which a plurality of sub power layers 31, 32, 33, and 34 are laminated. Each of the sub-power layers is composed of a conductive layer 310, 320, 330, 340 formed on a substrate and an insulating layer covering the entire substrate on which the conductive layer is formed, and is formed with a plurality of holes penetrating the sub-power layer. The hole formed in the sub-power layer is connected to the hole penetrating through the substrate PCB to constitute an electrical connection channel for realizing electrical connection between the semiconductor wafer and the PCB. For this purpose, the inside of the hole is subjected to gold plating. This electrical connection channel is called a via (or via).

7 is a view showing how the electrical integrity characteristic improving element 20, each sub power layer, and via are electrically connected, and only the conductive regions in the laminated sub power layer, that is, via 42 to 50, and the conductive layers 310, 320, 330 are displayed. , 340 and improved power integrity characteristics A diagram of the component 20 is used.

The plurality of conductive layers 310, 320, 330, 340 are conductive layers respectively formed on the laminated plurality of sub-power layers, and have a first hole 51 and a second hole 52.

Wherein, the first hole 51 and the second hole 52 do not penetrate through a substantial hole of each sub-power layer, but a region where a conductive layer is not formed on the sub-power layer, and the first hole 51 is a conductive layer for avoiding the sub-power layer. The second hole 52 is a region where the conductive layer is originally formed in contact with the via, and the second hole 52 is a region where the conductive layer is originally formed, but the conductive layer region which is removed during the formation of the via hole in the sub-power layer has a via profile An area of the same size that does not form a conductive layer.

Each conductive layer is used to connect vias that supply the same type of power source. That is, each conductive layer is patterned to interconnect vias that are electrically connected to the sub power layers.

Further, since the conductive layer is formed in the widest possible region, the electric resistance between the interconnected vias can be reduced, so that it is preferable to form the conductive layer in the widest possible region. That is, it is preferable to form the entire region of the plurality of vias penetrating the sub power layer except for the via which is not electrically connected to the least via which is not electrically connected (ie, the first hole). The diameter of the first hole 51 formed on the second conductive layer 320 of FIG. 7 is larger than the diameter of the second hole 52, and thus does not come into contact with the vias 42, 43, 47, 50, 44, 45. The second hole 52 formed in the second conductive layer 320 of FIG. 7 is in contact with vias 41, 48, 49, 46. Among them, vias 42, 43, 47, 50, 44, 45 which are not in contact with the first holes 51 are used for connection with the conductive layers of the other sub power layers. Accordingly, the vias connected to the other sub power layers penetrate through the holes of the corresponding sub power layer and are connected to the other sub power layers in a state where they do not contact the holes of the corresponding sub power layers to prevent interference.

When the first to fourth sub-power layers 31 to 34 are planarly viewed in the vertical direction, the holes in which the sub-power layers are opposed to each other are vias forming vias, and may be formed to have the same diameter, but may be formed to be different from each other as needed. a conductive layer of a sub-power layer having a diameter and electrically contacting the corresponding via is formed at a corresponding position with a second hole 52 having the same hole as via, and a conductive layer of the sub-power layer not in contact with the corresponding via is corresponding The region has a first aperture 51 that is larger than the via.

The conductive layer 310 of the first sub power layer shown in FIG. 7 is smaller in size than the conductive layers 320, 330, 340 of the second to fourth sub power layers. For example, when power is supplied only on one side (that is, when power supply to only one side is required), the first sub power layer 310 does not need to be formed wider, and therefore, in order to constitute the first sub power layer in the minimum area 310, which constitutes the first sub-power layer 310 less. Since the range of vias 41 to 50 connected to the second to fourth sub power layers 320, 330, and 340 is wide, the second to fourth sub power layers 320, 330, and 340 are formed to be wider in order to cover the entire area.

The vias 41 to 46 are for supplying power to the semiconductor wafer 12, and the vias 47, 48, 49, and 50 are for supplying power to the power integrity characteristic improving element 20. That is, the vias 47, 48, 49, and 50 form a circuit for the sub-power layer connected to the power integrity characteristic improving element 20 between the sub power layers which are doubled from each other.

It can be considered that two power sources of (+) and (-) are applied to the power layer 30. That is, two power supplies such as VDD(+) and VSS(-), VDDQ(+), and VSSQ(-) are applied to the power layer 30. In the second embodiment, two kinds of power sources are applied to the power layer 30, but they may be one type of power source or three or more types of power sources as needed.

Fig. 8 is a view specifically showing an interlayer connection structure in a sub-power layer structure in which dielectrics such as solder balls 36 are provided in land (or pads) 41a, 42a, 43a, 44a, 45a, 46a. Lands (or pads) 41b, 42b, 43b, 44b, 45b, 46b are electrically connected to the PCB 18 (see FIG. 2) via solder balls 16. Lands (or pads) 47a, 48a, 49a, 50a are electrically connected to the PCB 18 (see FIG. 2) via solder balls 16.

"B" of FIG. 8 indicates that via 44 is in contact with the second conductive layer 320, and "C" indicates that via 43 penetrates the second conductive layer 320 in a state of being non-contact with the second conductive layer 320. Here, the term "contact" means that the via 44 is in electrical contact with the conductive layer of the corresponding sub-power layer, and the so-called "through in the non-contact state" means that the via 44 is separated from the conductive layer of the corresponding sub-power layer so as to be in electrical contact. The conductive layer is penetrated through the state.

Thus, as shown in FIG. 8, via41~50 is formed vertically, but via41~50 is in contact with or not in contact with the conductive layer according to the conductive layer pattern of each sub-power layer.

In FIG. 8, when it is assumed that two power sources, such as VDD(+) and VSS(-) or VDDQ(+) and VSSQ(-), are applied to the power layer 30, the third sub-power layer 33 is used. For VSS(-) and VSSQ(-), the second sub power layer 32 is used for VDD(+), and the fourth sub power layer 34 is used for VDDQ(+). Among them, the third sub-power layer 33 is commonly used as a (-) power source, and thus becomes a common ground layer. Further, it can be considered that the second sub power layer 32 and the third sub power layer 33 are doubled, and the third sub power layer 33 and the fourth sub power layer 34 are doubled. At this time, one via can be electrically connected to the two sub power layers. In addition, the first sub power layer 31 can be used as an auxiliary power supply such as VDD' or VDDQ'.

The above description has been given of the case where two power sources are applied to the three sub power layers, but two power sources can be applied to the four sub power layers. For example, the first sub-power layer is for VDD(+), the second sub-power layer is for VSS(-), and the two are doubled with each other; the third sub-power layer is for VDDQ(+), and the fourth sub-power layer is for For VSSQ(-), the two are paired with each other. At this time, in order to suppress parasitic capacitance, a blocking layer may be provided between the second sub power layer and the third sub power layer or the conductive layers of the second sub power layer and the third sub power layer may be sufficiently separated.

In addition, it is also possible to apply two or more types of power sources to one sub power layer. That is, for example, as shown in FIG. 9(A), two conductive layers O, P separated from each other may be formed in one sub-power layer, thereby applying two power sources to one sub-power layer, as shown in FIG. 9(B). As shown, three conductive layers O, P, and Q separated from each other are formed in one sub-power layer, thereby applying three power sources to one sub-power layer, or as shown in FIG. 9(C), to a sub-power layer. Apply four power supplies. As for forming a plurality of separate conductive layers to form a power layer with several sub-power layers, one skilled in the art can select one from the design of the semiconductor package and the type of power source used in the semiconductor package.

In the case where two or more types of power sources are applied to one power layer, the power integrity characteristic improving element is located between two separate conductive layers X, and when connected to the power integrity characteristic improving element 20 When one via47 of via 47 and 48 is connected to the (-) terminal, another via48 is connected to the corresponding (+) Terminal.

The via for transmitting the signal is not shown in FIG. 8, but it can be understood that the via for transmitting the signal exists independently of the aforementioned via 41~50. The via for transmitting signals can be formed vertically as shown in FIG. 8, or can be connected through an internal pattern.

Further, in FIGS. 3 and 5, both the via-through power layer 30 and the substrate PCB 14 connected to the power integrity characteristic improving element 20 are shown, but in FIG. 5, the power integrity characteristic improving member 20 is provided. Since it is located between the semiconductor wafer 12 and the power layer 30, the via connected to the power integrity characteristic improving element 20 can be formed so as not to penetrate the substrate PCB 14 as needed.

In addition, the present invention is not limited to the above-described embodiments, and modifications and variations can be made without departing from the spirit and scope of the invention.

10‧‧‧Molding Department

12‧‧‧Semiconductor wafer

14‧‧‧Substrate PCB

16‧‧‧ solder balls

20‧‧‧Power Integrity Improvement Components

30‧‧‧Power supply power layer

31‧‧‧The first sub-power layer

32‧‧‧Second sub-power layer

33‧‧‧ third sub-power layer

34‧‧‧ fourth sub-power layer

Claims (6)

A semiconductor package comprising a semiconductor chip, comprising: a substrate PCB electrically connected to the semiconductor wafer through a dielectric, and a power supply power supply layer; and a power integrity characteristic improving component; Between the semiconductor wafer and the power supply power layer, and a surface of the power supply power layer is disposed in a region other than the region in which the dielectric is formed, and is electrically connected to the power layer The power layer is configured to have a plurality of sub-power layers laminated, and a plurality of sub-power layers are patterned to form a power supply conductive layer, and at least one sub-power layer of the plurality of sub-power layers On top, two or more separate conductive layer patterns are formed for supplying different power sources. A semiconductor package comprising a semiconductor package, comprising: a substrate PCB having a semiconductor wafer connected to a surface thereof via a dielectric; and a power supply power supply layer formed; and power integrity characteristic improvement An element disposed on the other side of the substrate PCB and disposed in an area other than an area where the dielectric is disposed for electrical connection when the substrate PCB is mounted on the test board PCB, the power integrity characteristic improving element Electrically connected to the power supply power layer, wherein the power layer is formed in a shape in which a plurality of sub power layers are laminated, and a power supply conductive layer is patterned on the plurality of sub power layers, and On at least one sub-power layer of the plurality of sub-power layers, two or more separate conductive layer patterns are formed for supplying different power sources. The semiconductor package according to claim 1 or 2, wherein The power integrity characteristic improving element penetrates the power layer and transmits power from the power layer through via that is electrically connected to one or more of the conductive layers. The semiconductor package of claim 3, wherein each of the conductive layers formed in the one or more sub-power layers is patterned to electrically connect the sub-power layers among the plurality of vias of the sub-power layer Connected to each other. The semiconductor package of claim 4, wherein each of the conductive layers is formed in a plurality of vias extending through the sub-power layer except for an inner hole that is not in contact with a via that should not be electrically connected. The entire area where the connected via is located. The semiconductor package of claim 1 or 2, wherein the power layer is composed of one or two sub-power layers.