TWI529931B - Semiconductor device and method for fabricating the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a high voltage field effect transistor and a low on resistance and a method of fabricating the same.

Bipolar-complementary metal-oxide-semiconductor-transistor-emitting diodes (Bipolar-CMOS-LDMOS, BCD) are widely used in power management integrated circuit (PMIC) applications. The BCD technology integrates a bipolar device, a complementary metal oxide semiconductor (CMOS), and a laterally diffused metal-oxide semiconductor (LDMOS) into a single wafer. In a BCD device, the bipolar device is used to drive high current, the CMOS can reduce the power consumption of the digital circuit, and the LDMOS has high voltage processing capability.

LDMOS devices are widely used in everyday applications. The on-resistance is an important factor in the energy consumption of the LDMOS device, and the on-resistance of the LDMOS device is proportional to the energy consumption. As the demand for power-saving and high-performance electronic devices increases, manufacturers are continually seeking ways to reduce the on-resistance and leakage of LDMOS devices. However, reducing the on-resistance is closely related to the off-state breakdown voltage. Specifically, lowering the on-resistance will break The state collapse voltage is greatly reduced. Therefore, the conventional LDMOS device can transmit a high off-state breakdown voltage, but cannot lower the on-resistance.

The LDMOS device includes a drift region and a body region. It has been found through experiments that when the doping concentration of the drift region is increased, the on-resistance of the LDMOS device can be lowered. However, the off-state breakdown voltage of the LDMOS device also decreases as the doping concentration of the drift region increases.

Therefore, there is still a need in the industry for an improved semiconductor device and method of fabricating the same.

An embodiment of the invention provides a semiconductor device comprising: a substrate having a first conductivity type, comprising: a body region having a first conductivity type; a source region formed in the body region; a drift a region having a second conductivity type; and a drain region type formed in the drift region; a multiple reduced surface field (RESURF) structure implanted in the drift region of the substrate; And a gate dielectric layer formed on the substrate, wherein the first conductivity type is opposite to the second conductivity type.

Another embodiment of the present invention provides a method of fabricating a semiconductor device, comprising: providing a substrate having a first conductivity type; implanting a dopant having a first conductivity type in the substrate to define a body region Implanting a dopant having a second conductivity type in the substrate to define a drift region; forming a multiple reduced surface field (RESURF) structure in the drift region; forming a gate The dielectric layer is over the substrate; a source region is formed in the body region; and a drain region is formed in the drift region, wherein the first conductivity type is opposite to the second conductivity pattern.

100‧‧‧LDMOS device

200‧‧‧Semiconductor device

110, 210‧‧‧ base

120, 220‧‧‧ epitaxial layer

122, 212, 222‧‧‧ main body area

124, 214, 224‧ ‧ drift zone

130‧‧‧Shallow trench isolation

150, 250‧‧‧ source area

160, 260‧‧ ‧ bungee area

20, 30, 40, 50‧‧‧ mask layers

300, 400, 600‧‧‧ doping process

500‧‧‧Ion implantation

700‧‧‧Hot growth process

230‧‧‧Multiple surface electric field reduction (RESURF) structure

230a‧‧‧first ion zone

230b‧‧‧Second ion zone

232‧‧‧First ion layer

234‧‧‧Second ion layer

X‧‧‧first horizontal direction

Y‧‧‧second horizontal direction

270‧‧‧First gate dielectric layer

270a‧‧‧steps (step)

272‧‧‧second gate dielectric layer

280‧‧‧ step gate dielectric layer

252‧‧‧ source electrode

262‧‧‧汲electrode

282‧‧‧ gate electrode

290‧‧‧Interlayer dielectric layer

1 is a flow chart showing a manufacturing method of a semiconductor device 200 according to an embodiment of the present invention; and FIGS. 6a to 6d are diagrams showing a step according to an exemplary embodiment. A method of forming a gate dielectric structure 280; a method of forming a step gate dielectric structure 280 according to another exemplary embodiment; and a drawing of a semiconductor device according to an embodiment of the invention; A schematic view of the section of 200.

The making and using of the embodiments of the present invention are described below. However, it will be readily understood that the embodiments of the present invention are susceptible to many specific embodiments of the invention and can The specific embodiments disclosed are merely illustrative of the invention, and are not intended to limit the scope of the invention.

The detailed embodiments are described below in conjunction with the drawings. Wherever possible, the same reference numerals are used in the drawings In the drawings, the shape and thickness are enlarged for clarity and convenience. The following description will specifically address the device of the embodiment of the invention or the forming portion of the component therein. It will be understood that elements not specifically shown or described may be of various different types. It is to be understood that the following drawings are not to scale and are merely illustrative.

Referring to FIG. 1, a conventional LDMOS device 100 is illustrated. The LDMOS device 100 includes a substrate 110 having a body region 122 and a drift region 124 formed therein. The substrate 110 further includes a plurality of shallow trench isolation (STI) 130 formed therein. In the LDMOS device 100, the current flowing from the source 150 to the drain 160 has to be bypassed (as indicated by the dashed line in Fig. 1) due to the obstruction of the STI 130. Such a deviation of the current path causes the LDMOS device 100 to raise the on-resistance.

2a-5e are flowcharts illustrating a method of fabricating the semiconductor device 200 in accordance with an embodiment of the present invention.

2a-2d illustrate a method of fabricating a body region and a drift region of the semiconductor device 200 according to an embodiment. Referring to Figure 2a, a substrate 210 having a first conductivity type is provided. The substrate 210 may be a bulk substrate, or a silicon-on-insulator (SOI) substrate or the like. In some embodiments, substrate 210 can have a p-type first conductivity type, such as a boron-doped matrix. In other embodiments, substrate 210 can have an n-type first conductivity type, such as a phosphorous or arsenic substrate. Other suitable substrates can also be used.

Referring to FIG. 2b, a mask layer 20 is formed on the substrate 210. The mask layer 20 can be a patterned photoresist layer or a hard mask layer (eg, tantalum nitride, or hafnium oxynitride, etc.). After the mask layer 20 is formed, a doping process 300 is performed to selectively incorporate a first conductivity type dopant into the substrate 210 to define the body region 212. In some example embodiments, the concentration of the substrate 210 may be higher than the concentration of the body region 212. For example, when the body region is p-type, the substrate 210 can be highly doped p-type (p+). Next, the mask layer 20 is removed after the body region 212 is formed.

Referring to Figure 2c, another mask layer 30 is formed over the substrate. The mask layer 30 can be a patterned photoresist layer or a hard mask layer (eg, tantalum nitride, or hafnium oxynitride, etc.). After the mask layer 20 is formed, a doping process 400 is performed to selectively incorporate a second conductivity type dopant into the substrate 210 to define the drift region 214. The second conductivity type is opposite to the first conductivity type.

In some embodiments, the drift region 214 can be a wide region formed before the body region 212. As shown in FIG. 3a, body region 212 is formed in drift region 214 by a routing process.

In other embodiments, an epitaxial layer may be formed on the substrate 210 as desired, and the body region and the drift region are formed in the epitaxial layer. Referring to FIG. 3b, an epitaxial layer 220 having a first conductivity type is formed on the substrate 210. In addition, the doping concentration of the substrate 210 is greater than the doping concentration of the epitaxial layer 220. For example, when the first conductivity type is n-type, the semiconductor substrate 210 can be a highly doped n-type (N+) substrate, and the epitaxial layer 220 is a lightly doped n-type (n-) epitaxial layer. Floor. The epitaxial layer 220 having a thickness of 3 to 10 um can be formed by epitaxial growth. In such an embodiment, body region 222 and drift region 224 are formed in epitaxial layer 220. The method of forming the body region 222 and the drift region 224 is similar to the body region 212 and the drift region 214, and therefore will not be described herein to prevent repetition.

Next, after forming the body region 212 and the drift region 214, a step of forming a multiple reduced surface field (RESURF) structure is performed.

4a-4b illustrate a method of fabricating a multiple reduced surface field (RESURF) structure in accordance with an embodiment. Referring to FIG. 3a, a mask layer 40 is formed on the semiconductor substrate 210 (or the epitaxial layer 220) to expose a range defined as a surface electric field reduction region. The mask layer 40 can be a map A photoresist layer or a hard mask layer (for example, tantalum nitride, or hafnium oxynitride, etc.). After the mask layer 40 is formed, a multi-ion ion implantation process 500 is performed to form a multiple RESURF structure 230. A multiple RESURF structure 230 is formed in the drift region 214 (or 224). Referring to FIG. 4b, after forming the multiple RESURF structure 230, the mask layer 40 is removed and an annealing process is performed to activate the implanted ions.

Figures 5a-5h illustrate multiple RESURF structures 230 of different permutations combined in accordance with an embodiment of the present invention. Please refer to FIG. 5a, which illustrates a cross-sectional view of a multiple RESURF structure 230 according to an exemplary embodiment. In this embodiment, the multiple RESURF structure 230 is a multilayer structure including a plurality of first ion regions 230a and a plurality of second ion regions 230b. The multiple RESURF structure 230 is formed by staggering the first ion regions 230a and the second ion regions 230b in the vertical direction. The first and second ion regions 230a, 230b have different conductivity types. In some embodiments, the conductivity patterns of the first ion regions 230a are the same as the first conductivity patterns of the body regions 212, and the conductivity patterns of the second ion regions 230b are the same as the second regions of the drift regions 214. Conductive type. In other embodiments, the conductivity patterns of the first ion regions 230a are the second conductivity type, and the conductivity patterns of the second ion regions 230b are the first conductivity patterns.

Figure 5b depicts a cross-sectional view of a multiple RESURF structure 230 in accordance with another exemplary embodiment. Referring to FIG. 5b, the multiple RESURF structure 230 is a multi-layer structure including a plurality of first ion regions 230a of a first conductivity type and a second ion region 230b of a plurality of second conductivity patterns. In this embodiment, the first ion regions 230a and the second ion regions 230b are staggered in a first horizontal direction x. The first and second ion regions 230a, 230b have different conductivity types. In some embodiments, the first ion regions 230a The conductivity type is the same as the first conductivity type of the body region 212, and the conductivity patterns of the second ion regions 230b are the same as the second conductivity pattern of the drift region 214. In other embodiments, the conductivity patterns of the first ion regions 230a are the second conductivity type, and the conductivity patterns of the second ion regions 230b are the first conductivity patterns.

Referring to Figure 5c, a three-dimensional perspective view of the multiple RESURF structure 230 is depicted in accordance with yet another example embodiment. The multiple RESURF structure 230 is a multilayer structure including a plurality of first ion regions 230a of a first conductivity type and a second ion region 230b of a plurality of second conductivity types. In this embodiment, the first ion regions 230a and the second ion regions 230b are staggered in a second horizontal direction y. The first and second ion regions 230a, 230b have different conductivity types. In some embodiments, the conductivity patterns of the first ion regions 230a are the same as the first conductivity patterns of the body regions 212, and the conductivity patterns of the second ion regions 230b are the same as the second regions of the drift regions 214. Conductive type. In other embodiments, the conductivity patterns of the first ion regions 230a are the second conductivity type, and the conductivity patterns of the second ion regions 230b are the first conductivity patterns.

Referring to FIG. 5d, a cross-sectional view of a multiple RESURF structure 230 is illustrated in accordance with yet another exemplary embodiment. In this embodiment, the multiple RESURF structure 230 is formed by staggering a plurality of first ion layers 232 and second ion layers 234. The first ion layers 232 are formed by the first ion regions 230a. In some embodiments, the first ion layer 232 can be formed by the second ion region 230b. The second ion layers 234 are composite regions composed of a plurality of first ion regions 230a and a plurality of second ion regions 230b staggered in the first horizontal direction x. The first and second ion regions 230a, 230b have different conductivity types state. In some embodiments, the conductivity patterns of the first ion regions 230a are the same as the first conductivity patterns of the body regions 212, and the conductivity patterns of the second ion regions 230b are the same as the second regions of the drift regions 214. Conductive type. In other embodiments, the conductivity patterns of the first ion regions 230a are the second conductivity type, and the conductivity patterns of the second ion regions 230b are the first conductivity patterns.

In some embodiments, as shown in FIG. 5e, the multiple RESURF structure 230 is a multilayer structure composed of a plurality of first ion regions 230a and a plurality of second ion regions 230b staggered in a first horizontal direction x and a vertical direction. . The first and second ion regions 230a, 230b have different conductivity types. In some embodiments, the conductivity patterns of the first ion regions 230a are the same as the first conductivity patterns of the body regions 212, and the conductivity patterns of the second ion regions 230b are the same as the second regions of the drift regions 214. Conductive type. In other embodiments, the conductivity patterns of the first ion regions 230a are the second conductivity type, and the conductivity patterns of the second ion regions 230b are the first conductivity patterns.

Referring to Figure 5f, a three-dimensional perspective view of the multiple RESURF structure 230 is depicted in accordance with an exemplary embodiment. Multiple RESURF Structure 230 The multiple RESURF structure 230 is a multilayer structure composed of a plurality of first ion layers 232 and a plurality of second ion layers 234 staggered in a first horizontal direction x. The first ion layer 232 is a composite region composed of a plurality of first ion regions 230a and a plurality of second ion regions 230b staggered in the second horizontal direction y. The first and second ion regions 230a, 230b have different conductivity types. In some embodiments, the conductivity patterns of the first ion regions 230a are the same as the first conductivity patterns of the body regions 212, and the conductivity patterns of the second ion regions 230b are the same as the second regions of the drift regions 214. Conductive type. In other embodiments, the first ion regions 230a The conductive type is the second conductive type, and the conductive patterns of the second ion regions 230b are the first conductive type.

Referring to Figure 5g, a three-dimensional perspective view of the multiple RESURF structure 230 is depicted in accordance with an exemplary embodiment. Multiple RESURF Structure 230 The multiple RESURF structure 230 is a multilayer structure composed of a plurality of first ion layers 232 and a plurality of second ion layers 234 staggered in a first horizontal direction y. The first ion layers 232 are composite regions in which a plurality of first ion regions 230a and a plurality of second ion regions 230b are staggered in the second horizontal direction x. The second ion layers 234 are formed by a plurality of first ion regions 230a. In some embodiments, the second ion layers 234 are formed by a plurality of second ion regions 230b. The first and second ion regions 230a, 230b have different conductivity types. In some embodiments, the conductivity patterns of the first ion regions 230a are the same as the first conductivity patterns of the body regions 212, and the conductivity patterns of the second ion regions 230b are the same as the second regions of the drift regions 214. Conductive type. In other embodiments, the conductivity patterns of the first ion regions 230a are the second conductivity type, and the conductivity patterns of the second ion regions 230b are the first conductivity patterns.

In some embodiments, as shown in FIG. 5h, the multiple RESURF structure 230 is a multilayer structure composed of a plurality of first ion regions 230a and a plurality of second ion regions 230b staggered in a first horizontal direction y and a vertical direction. . The first and second ion regions 230a, 230b have different conductivity types. In some embodiments, the conductivity patterns of the first ion regions 230a are the same as the first conductivity patterns of the body regions 212, and the conductivity patterns of the second ion regions 230b are the same as the second regions of the drift regions 214. Conductive type. In other embodiments, the conductive patterns of the first ion regions 230a are the second conductivity type, and the second ion regions The conductivity type of 230b is the first conductivity type.

It should be understood that while the above embodiments are directed to a plurality of RESURF structures 230 for a particular arrangement, the invention is not limited to the permutations and combinations shown in Figures 5a-5h. Rather, the invention encompasses various modifications and permutations. For example, as long as the current path from the source region to the drain region can be shortened, the number of ion regions or ion layers of the multiple RESURF structure can be captured more than the multiple RESURF structure 230 shown in the 5a-5h diagram, and the multiple RESURF Each ionic region or ionic layer of the structure can have a different thickness or size. Further, the multiple RESURF structure shown in Figs. 5a to 5h may also be formed in the drift region 224 of the epitaxial layer as in Fig. 3b.

Next, a gate dielectric structure having a step formed on its edge will be described below in accordance with an embodiment.

6a-6d illustrate a method of forming a step gate dielectric structure 280 in accordance with an exemplary embodiment.

Referring to FIG. 6a, after forming the multiple RESURF structure 230, a first gate dielectric layer 270 is formed on the semiconductor substrate 210 (or the epitaxial layer 220). The first gate dielectric layer 270 can include hafnium oxide, tantalum nitride, hafnium oxynitride, high-k dielectrics, other suitable dielectric materials, or combinations of the foregoing. Wherein, the high dielectric constant material may include a metal oxide, for example, Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb An oxide of a metal such as Dy, Ho, Er, Tm, Yb, Lu, or a combination thereof. The first metal dielectric layer 270 can be formed by conventional techniques in the art, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (physical vapor deposition). Vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or a combination of the foregoing. The first gate dielectric layer 270 can have a thickness of about 400 to 5000 angstroms. The first gate dielectric layer 270 can cover both the body region 212 and the drift region 214 (or 222 and 224).

Referring to FIG. 6b, an etch process 600 is performed using a mask layer 50 to remove a portion of the first thyristor layer 270, thereby forming a step 270a on at least one edge of the first thyristor layer 270. (as shown in Figure 6c). The mask layer 50 can be a patterned photoresist layer or a hard mask layer (eg, tantalum nitride, or hafnium oxynitride, etc.). The etch process 600 can be dry etch or wet etch. It should be understood that although the step 270a shown in Fig. 6c is a cliff shape, the step 270a may also be circular or other suitable shape. After forming the step 270a on the edge of the first gate dielectric layer 270, the mask layer 50 is removed.

Next, referring to FIG. 6d, a second gate dielectric layer 272 is formed on the semiconductor substrate 210 (or the epitaxial layer 220). The thickness of the second gate dielectric layer 272 is smaller than the first gate dielectric layer 270. The first gate dielectric layer 270 and the second gate dielectric layer 272 form a step gate dielectric structure 280. The second gate dielectric layer 272 is adjacent to the first gate dielectric layer 270. The second gate dielectric layer 272 has a thickness of about 30 to 1000 angstroms. The second gate dielectric layer 272 can be formed by the same method as the first gate dielectric layer 270, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical gas. Physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or a combination thereof. The material of the second gate dielectric layer 272 may be the same as the first gate dielectric layer 270, for example, hafnium oxide, tantalum nitride, hafnium oxynitride, high-k dielectrics, other suitable dielectric layers. Electrical material, or a combination of the foregoing.

7a-7d illustrate a method of forming a step gate dielectric structure 280 according to another exemplary embodiment.

Referring to FIG. 7a, a first gate dielectric layer 270 is formed on the semiconductor substrate 210 (or the epitaxial layer 220). The first gate dielectric layer 270 can include hafnium oxide, tantalum nitride, hafnium oxynitride, high-k dielectrics, other suitable dielectric materials, or combinations of the foregoing. Wherein, the high dielectric constant material may include a metal oxide, for example, Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb An oxide of a metal such as Dy, Ho, Er, Tm, Yb, Lu, or a combination thereof. The first metal dielectric layer 270 can be formed by conventional techniques in the art, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD). ), thermal oxidation, UV-ozone oxidation, or a combination of the foregoing. The first gate dielectric layer 270 can have a thickness of about 400 to 5000 angstroms. The first gate dielectric layer 270 can cover both the body region 212 and the drift region 214 (or 222 and 224).

Referring to FIG. 7b, a mask layer 60 is formed on the first gate dielectric layer 270. The cap layer 60 has at least one opening 60a for selectively exposing a portion of the first gate dielectric layer 270. The opening 60a can be formed by an etching process.

Referring to FIG. 7c, a thermal growth process 700 is performed on a portion of the first gate dielectric layer 270 exposed to the port. The portion of the first gate dielectric layer 270 (the portion of the thermal growth process 700) is expanded to a greater thickness. In some embodiments, a second thermal growth process can be performed as appropriate to enable The portion of the first gate dielectric layer 270 is further expanded. The expanded portion of the first gate dielectric layer 270 has a thickness of about 2000 to 6000 angstroms. In some embodiments, a portion of the first gate dielectric layer 270 extends into the substrate 210 (or the via layer 220) as shown in FIG.

Referring to FIG. 7d, the mask layer 60 and a portion of the first gate dielectric layer 270 are removed to form the step gate dielectric structure 280.

After forming the step gate dielectric structure 280, a process is performed to form the source and drain regions. Referring to FIG. 8, a source region 250 is formed in the body region 212 (or 222), and a drain region 260 is formed in the drift region 214 (or 224). The source and drain regions 250, 260 can be formed by a doping process as is known in the art, such as an ion implantation process.

Next, fabrication of a semiconductor device 200 is completed by forming a component conventional in a conventional semiconductor device, for example, an inter-layer dielectric (ILD) layer 290, source/drain electrodes 252 and 262, and a gate electrode 282. Referring to FIG. 8, an interlayer dielectric layer 290 may be overlying the semiconductor substrate 210 and have contact holes to expose the source/drain regions 250, 260. It should be noted that the number of contact holes may be two or more depending on the design of the device. The gate electrode 282 can include a single or multi-layer structure formed on the step gate dielectric structure 280. The material forming the gate electrode 282 may include a metal, a doped polysilicon, or a combination of the foregoing. The process of forming the gate electrode 282 may include low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), other suitable processes, or a combination thereof. . The source electrode 252 is formed on the source region 250, and the drain electrode 262 is formed on the drain region 260.

Embodiments of the present invention provide at least the following advantages over conventional LDMOS devices. First, the multiple RESURF structure 230 provides a shorter current path from the source region 250 to the drain region 260 (as indicated by the dashed line in FIG. 8), which reduces the on-resistance of the semiconductor device 200. Moreover, when the on-resistance is lowered, the stepped design of the gate dielectric structure 280 can effectively maintain the breakdown voltage value.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified, replaced and retouched without departing from the spirit and scope of the invention. . For example, those skilled in the art can readily appreciate that many of the features, functions, processes, and materials described herein can be modified within the scope of the invention.

200‧‧‧Semiconductor device

210‧‧‧Base

212‧‧‧ main body area

214‧‧‧ drift zone

250‧‧‧ source area

260‧‧‧Bungee area

230‧‧‧Multiple surface electric field reduction (RESURF) structure

270‧‧‧First gate dielectric layer

270a‧‧‧steps (step)

272‧‧‧second gate dielectric layer

280‧‧‧ step gate dielectric layer

252‧‧‧ source electrode

262‧‧‧汲electrode

282‧‧‧ gate electrode

290‧‧‧Interlayer dielectric layer

Claims (24)

A semiconductor device comprising: a substrate having a first conductivity type comprising: a body region having the first conductivity type; a source region formed in the body region; and a drift region having a a second conductivity type; and a drain region type formed in the drift region; a multiple reduced surface field (RESURF) structure implanted in the drift region of the substrate, wherein The multiple surface electric field reducing structure is a multi-layer structure including a plurality of first ion regions and a plurality of second ion regions, wherein the plurality of first ion regions have the first conductivity type, and the plurality of The second ion region has the second conductivity type, wherein the plurality of first ion regions and the plurality of second ion regions are spaced apart from each other by a distance; and a gate dielectric layer is formed on the substrate; wherein the first A conductivity type is opposite to the second conductivity type. The semiconductor device of claim 1, wherein the plurality of first ion regions and the plurality of second ion regions are staggered in a vertical direction. The semiconductor device of claim 1, wherein the plurality of first ion regions and the plurality of second ion regions are staggered in a horizontal direction. The semiconductor device of claim 1, wherein the plurality of first ion regions and the plurality of second ion regions are staggered in a horizontal direction and a vertical direction. The semiconductor device of claim 1, wherein the multiple RESURF structure is formed between the source region and the drain region. The semiconductor device of claim 5, wherein the edge of the gate dielectric layer comprises a step or a curved shape. The semiconductor device of claim 6, wherein a portion of the gate dielectric layer extends from an upper surface of the substrate into the substrate. The semiconductor device of claim 1, wherein the first conductivity type is an n-type and the second conductivity type is a p-type. The semiconductor device of claim 1, wherein the first conductivity type is a p-type and the second conductivity type is an n-type. The semiconductor device of claim 1, further comprising a source electrode formed on the source region and a drain electrode formed on the drain region. The semiconductor device of claim 1, wherein the substrate further comprises an epitaxial layer, and wherein the body and the drift region are formed in the epitaxial layer, and the gate dielectric layer is formed on the Lei On the crystal layer. A method of fabricating a semiconductor device, comprising: providing a substrate having a first conductivity type; implanting a dopant having the first conductivity type in the substrate to define a body region; implanting a substrate a second conductivity type of dopant in the substrate to define a drift region; forming a multiple reduced surface field (RESURF) structure in the drift region, wherein the multiple surface electric field reducing structure is a multilayer structure including a plurality of first ions a region and a plurality of second ion regions, wherein the plurality of first ion regions have the first conductivity type, and the plurality of second ion regions have the second conductivity pattern, wherein the plurality of first ion regions and The plurality of second ion regions are spaced apart from each other by a distance; a gate dielectric layer is formed over the substrate; a source region is formed in the body region; and a drain region is formed in the drift region; wherein the A conductivity type is opposite to the second conductivity type. The method of fabricating a semiconductor device according to claim 12, wherein the multiple RESURF device is formed by implanting the plurality of first ion regions and the plurality of second ion regions in the drift region. The method of fabricating a semiconductor device according to claim 13, wherein the plurality of first ion regions and the plurality of second ion regions are staggered in a vertical direction. The method of fabricating a semiconductor device according to claim 13, wherein the plurality of first ion regions and the plurality of second ion regions are staggered in a horizontal direction. The method of fabricating a semiconductor device according to claim 13, wherein the plurality of first ion regions and the plurality of second ion regions are staggered in a horizontal direction and a vertical direction. The method of fabricating a semiconductor device according to claim 12, wherein the multiple RESURF structure is formed between the source region and the drain region. The method of fabricating a semiconductor device according to claim 12, wherein the method of forming the gate dielectric layer comprises: forming a first gate dielectric layer on the substrate; forming a patterned mask on the first Determining a first-order region of the first gate dielectric layer on the gate dielectric layer; removing a portion of the first gate dielectric layer by a dry etching or a wet etching process to Forming at least one edge of the gate dielectric layer into a first order or a circle; removing the patterned mask; and forming a second gate dielectric layer on the substrate, the second gate dielectric layer adjoining the first The gate dielectric layer; wherein the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer, and the first gate dielectric layer and the second gate dielectric layer form the gate dielectric layer. The method of fabricating a semiconductor device according to claim 12, wherein the method of forming the gate dielectric layer comprises: forming a dielectric layer on the substrate; forming a pattern having an opening to cover the dielectric And performing a thermal growth process on a portion of the dielectric layer, wherein the portion of the dielectric layer is expanded to a thicker thickness, and wherein the portion of the dielectric layer is from the surface of the substrate Extending into the substrate; Remove the patterned mask. The method of fabricating a semiconductor device according to claim 12, wherein the gate dielectric layer comprises ruthenium oxide, ruthenium nitride, ruthenium carbide, ruthenium oxynitride, or a combination thereof. The method of fabricating a semiconductor device according to claim 12, wherein the first conductivity type is an n-type and the second conductivity type is a p-type. The method of fabricating a semiconductor device according to claim 12, wherein the first conductivity type is a p-type and the second conductivity type is an n-type. The method of fabricating a semiconductor device according to claim 12, further comprising: forming a source electrode on the source region; forming a drain electrode on the drain region; and forming a gate electrode The gate dielectric layer is electrically connected to the source electrode and the drain electrode. The method for fabricating a semiconductor device according to claim 12, further comprising forming an epitaxial layer on the substrate, wherein the body and the drift region are formed in the epitaxial layer, and the gate dielectric layer is Formed on the epitaxial layer.