TWI242818B - Process of mounting a passive component - Google Patents
Process of mounting a passive component Download PDFInfo
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- TWI242818B TWI242818B TW93138381A TW93138381A TWI242818B TW I242818 B TWI242818 B TW I242818B TW 93138381 A TW93138381 A TW 93138381A TW 93138381 A TW93138381 A TW 93138381A TW I242818 B TWI242818 B TW I242818B
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 229910000679 solder Inorganic materials 0.000 claims abstract description 50
- 230000004907 flux Effects 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000003466 welding Methods 0.000 claims description 6
- 239000000084 colloidal system Substances 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 239000008266 hair spray Substances 0.000 claims 1
- 230000035800 maturation Effects 0.000 claims 1
- 238000005476 soldering Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 239000012752 auxiliary agent Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 such as an inductor Substances 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
1242818 五、發明說明(1) ~ -- 【發明所屬之技術領域】 本發明係有關於一種被動元件接合過程,特別係有關 於一種避免助銲劑不當殘留之被動元件接合過程。 【先前技術】 一在習知之半導體封裝領域中,一電路基板除了要承載 二晶片之外、,必要時係會將一被動元件表面接合在該電路 基板上,該被動元件係如電感、電容或電阻等,其係用以 保護晶片或增加電性效能。相關之習知封裝型態S可見於 我國新型專利證號第244576號「晶片封裝結構」。 ' 然而在接合被動元件過程中所使用的助劑 J易殘留在被動元件之下方,不僅會損傷基板,嚴重時 導致電性斷/紐路。請參閱第1圖,一適用於半導體封裝之 基板10係具有一上表面丨丨,在該基板10之該上表面U ^ 形成有一第一接墊12與一第二接墊13,並覆蓋有一銲罩層 1 二=:sk)。該第一接墊12與該第二接墊13係顯露曰 於戎鲜罩層1 4,用以接合一被動元件30之電極。通 嘗20係先塗設在該第一接墊丨2與該第二接墊1 3上,並以。 銲方式使該錫膏20接合該被動元件3〇之兩電極至該^ = 墊12與該第二接墊13。並且在回銲前會提供一助銲劑 (flux),用來幫助該錫膏20銲接在該第—接墊12與該 接墊13之金屬表面。但由於在該被動元件3〇與該 間^留有一間隙31,且在回銲之高溫狀態,該助銲劑係且 有鬲流動性,因此使得該錫膏20與該助銲劑會往該間 流動,並且殘留在該被動元件30之底部而使得該助銲劑不1242818 V. Description of the invention (1) ~-[Technical field to which the invention belongs] The present invention relates to a passive component bonding process, and particularly relates to a passive component bonding process to avoid improper residual flux. [Prior art] In the field of conventional semiconductor packaging, in addition to carrying two chips on a circuit substrate, if necessary, a passive component surface is bonded to the circuit substrate, such as an inductor, capacitor or Resistors, etc., are used to protect the chip or increase electrical performance. The related conventional package type S can be found in China's new patent certificate No. 244576 "chip package structure". '' However, the auxiliary agent J used in the process of bonding passive components is liable to remain under the passive components, which will not only damage the substrate, but also cause electrical disconnection / linkage in severe cases. Referring to FIG. 1, a substrate 10 suitable for a semiconductor package has an upper surface 丨 丨 On the upper surface U ^ of the substrate 10, a first pad 12 and a second pad 13 are formed and covered with Solder shield layer 1 2 =: sk). The first contact pads 12 and the second contact pads 13 are exposed in a covering layer 14 for bonding electrodes of a passive element 30. In general, 20 is first coated on the first pads 2 and the second pads 13 and then. The soldering method causes the solder paste 20 to join the two electrodes of the passive component 30 to the ^ pad 12 and the second pad 13. A flux is provided before reflow to help the solder paste 20 be soldered to the metal surfaces of the first and second pads 12 and 13. However, since there is a gap 31 between the passive component 30 and the space, and the flux is high in the high temperature state of reflow, the solder paste 20 and the flux will flow to the space. And remains on the bottom of the passive element 30 so that the flux does not
第6頁 Ϊ242818 五、發明說明(2) 易被清除。如 現助銲劑之一 13之間擴散之 後’通常另需 封膠體密封該 銲後之錫膏2〇 封膠體時,該 31衝流,即往 接墊12與該第 【發明内容】 本發明之 第2圖所示,在拔除該被動元件3〇之後,發 殘留痕跡21有往該第一接墊12與該第二接\ 現象。此外,在回銲接合有該被動元件3〇之 要執行一封膠步驟,以形成在該基板1〇上之 被動元件30與晶片(圖未繪出)。但由於該回 係,有相當大之熱膨脹係數,在烘烤固化該 錫貧2 0受熱膨脹會沿著殘留有助銲劑之間隙 該被動元件30之底部擴散,而使得在該第二 二接塾13上之錫膏20橋接,造成電性短路。 利用一由可硬 硬化油墨,使 由遠油墨熟化 使助辉劑不會 發明亦揭露由 本發明之 所提供之基板 一第一接塾與 口内之該基板 之接合,且不 本發明之 主要目的在於提供一種被動元件接合過程, 化油墨形成在至少兩接墊之間,再熟化該可 其成為一播牆(dam),且其高度係高於該基 板上之一銲罩^。在回銲接合一被動元件時,該擋牆係已 完成而能阻擋助銲劑在該些接墊間流動,並 殘留在該被動元件與該基板之間。此外,本 該被動元件接合過程形成之半導體封裝構 -人一目的在於提供一種被動元件接合過程, 之銲罩層係具有一開口,其係顯露該基板之 一第二接墊’該可硬化油墨係塗設於在該開 之’丨電層上,適用於微間距微小被動元件 會殘留助銲劑。 程 再一目的在於提供一種被動元件接合過Page 6 Ϊ242818 V. Description of the invention (2) Easy to be removed. For example, after one of the current fluxes 13 diffuses, it is usually necessary to further seal the colloid to seal the post-soldering solder paste 20. When the colloid is sealed, the 31 rushes to the pad 12 and the [invention content] of the present invention. As shown in FIG. 2, after the passive component 30 is removed, a residual trace 21 is sent to the first pad 12 and the second connection phenomenon. In addition, an adhesive step is performed when the passive component 30 is bonded back to form a passive component 30 and a wafer (not shown) formed on the substrate 10. However, due to the return system, there is a considerable thermal expansion coefficient. The thermal expansion of the tin lean 20 during baking and curing will diffuse along the bottom of the passive element 30 with the flux remaining gap, so that the second and second connection The solder paste 20 on 13 bridges, causing an electrical short. The use of a hard-hardenable ink, so that the aging ink does not invent the brightener, and the substrate provided by the present invention, a first connection with the substrate in the mouth, is also disclosed, and the main purpose of the present invention is not A passive component bonding process is provided. The ink is formed between at least two pads, and then it can be matured into a dam, and its height is higher than a solder mask on the substrate. When the passive component is re-soldered, the retaining wall system is completed and can prevent the flux from flowing between the pads and remain between the passive component and the substrate. In addition, the purpose of the semiconductor package structure formed by the passive component bonding process is to provide a passive component bonding process. The solder mask layer has an opening that exposes a second pad of the substrate, the hardenable ink. The coating is applied on the open electrical layer, which is suitable for the fine-pitch micro-passive components which will leave flux. Another purpose is to provide a passive component
第7頁 1242818 五、發明說明(3) 顏色係相同 之殘留痕跡 之被動元件 表面係形成 銲罩層係顯 刷形成一可 油墨係位於 ;接著,熟 形成為一擔 或近似於該銲罩層之顏色,以利 〇 接合過程,包含:提供一基板, 有一第一接墊、一第二接墊以及 露出該第一接墊與該第二接墊; 硬化油墨在該基板之該上表面 該第一接墊與該第二接墊之間且 化(curing)該可硬化油墨,以使 牆Uam);最後,以回銲錫膏方 兀件至該第一接墊與該第二接墊,並提供一 利用該擔牆之 觀察該助銲劑 依本發明 该基板之一上 一銲罩層,該 之後,可以印 上,該可硬化 高於該銲罩層 該可硬化油墨 式銲接一被動 可清潔金屬表面之助銲劑,該助銲劑係被該擋牆阻擋而不 可在該第一接墊與該第二接墊之間流動。 【實施方式】 睛參閱所附圖式,本發明將列舉以下之實施例說明: 一一在本發明之第一具體實施例中,如第3A至”圖所示揭 : 種被動元件接合過程。首先,請參閱第3A圖,提供一 土板11 0,該基板1 1 〇係為一電路基板,例如多層印刷電路 板或多層陶瓷電路板,該基板11〇係具有一上表面m,並 2包含有在内部之至少一介電層112、線路層與鍍通孔(圖 繪出)等等,在該上表面丨丨丨上係形成有一第一接墊 第一接塾114以及一銲罩層ii5(soldermask),該 、曰罩層11 5係顯露出該第一接墊1丨3與該第二接墊11 4,其 7可為部份顯露或完全顯露。在本實施例中,該第一接墊 3與該第二接塾丨丨4係用以接合微間距之被動元件,如電 1242818 五、發明說明(4) ,, 感、電容或電阻等,該銲罩層11 5係可具有一開til 16(如 第4圖所示),以同時顯露該第一接墊113與該第二接墊 11 4。此外,在本實施例中,連接該第一接墊11 3與該第二 接墊1 1 4之跡線是被覆蓋而不顯露在該銲罩層11 5之該開口 116 〇 之後,請參閱第3B圖,將一可硬化油墨1 30圖案化形 成在該基板1 1 0之該上表面1 11上,該可硬化油墨1 3 〇係位 於該第一接墊11 3與該第二接墊1 1 4之間且高於該銲罩層 115。該油墨130係可以選用與該銲罩層115相同之材質或 是其它之可硬化樹脂。該可硬化油墨1 3 〇之形成方式,係 可利用一遮罩120(mask)預先形成於該基板11〇之上表面 111 ’该遮罩120係可以是一種網板(screen)或是一種乾膜 (dry f i lm),該遮罩1 20係至少遮蓋該第一接塾1 1 3與該第 一接墊11 4,並具有一開孔1 2 1,以顯露該基板1 1 〇在該第 一接墊113與該第二接墊114間之上表面ln部位。之後, I利用印刷方式將該可硬化油墨i 3〇塗設於該基板丨丨〇之預 定位置。在本實施例中,該可硬化油墨13〇係塗設於在該 開口116内,且該可硬化油墨13〇係形成在該基 〇 電層112上。 , 接著,晴參閱第冗圖,在移除該遮罩120之前或之 ί本ii(CUring)該可硬化油墨13〇,其係可利用烘烤或 達到熟化之目的,以使形成為一擋牆131 (dam)。 化2 驟係為必要且重要之步驟,其係可使由該可硬 斤形成之该擔牆1 3 1係為抗迴銲溫度之固體且固Page 7 1242818 V. Description of the invention (3) The surface of the passive component with the same color remaining traces is formed as a solder mask layer, and a brush is formed to form an ink-based system. Then, it is cooked into a load or similar to the solder mask layer. The color to facilitate the joining process includes: providing a substrate, a first pad, a second pad, and exposing the first pad and the second pad; and hardening ink on the upper surface of the substrate. Curing the hardenable ink between the first pad and the second pad to make the wall Uam); finally, reflowing the solder paste to the first pad and the second pad, It also provides an observation using the supporting wall, the flux according to the present invention, a solder mask layer on one of the substrates, after which, it can be printed, the hardenability is higher than the solder mask layer, and the hardenable ink-type welding is A flux for cleaning a metal surface, the flux is blocked by the retaining wall and cannot flow between the first pad and the second pad. [Embodiment] Referring to the attached drawings, the present invention will enumerate the following embodiment descriptions:-In the first specific embodiment of the present invention, as shown in Figs. 3A to "", a passive component bonding process is disclosed. First, referring to FIG. 3A, a soil plate 110 is provided. The substrate 1 10 is a circuit substrate, such as a multilayer printed circuit board or a multilayer ceramic circuit board. The substrate 11 has an upper surface m, and 2 It includes at least a dielectric layer 112, a circuit layer, a plated through hole (illustrated in the drawing), and the like. A first pad 114 and a solder mask are formed on the upper surface. Layer ii5 (soldermask), the mask layer 115 is exposed to the first pad 1 3 and the second pad 11 4, and 7 may be partially exposed or completely exposed. In this embodiment, The first contact pad 3 and the second contact 丨 丨 4 are used to join micro-pitch passive components, such as electrical 1242818 V. Description of the Invention (4), inductance, capacitance or resistance, etc. The solder mask layer 11 5 The system may have an opening til 16 (as shown in FIG. 4) to expose the first pad 113 and the second pad 114 at the same time. In addition, in this embodiment, the trace connecting the first pad 11 3 and the second pad 1 1 4 is covered and is not exposed behind the opening 116 of the solder mask layer 115, please refer to FIG. 3B, a hardenable ink 1 30 is patterned on the upper surface 1 11 of the substrate 1 10, and the hardenable ink 1 30 is located on the first pad 11 3 and the second pad 1 1 4 and higher than the solder mask layer 115. The ink 130 can be made of the same material as the solder mask layer 115 or other hardenable resin. The formation of the hardenable ink 1 3 0 can be A mask 120 is formed on the upper surface 111 of the substrate 111 in advance. The mask 120 can be a screen or a dry film, and the mask 120 can be Cover at least the first pad 1 1 3 and the first pad 11 4 and have an opening 1 2 1 to expose the substrate 1 1 〇 between the first pad 113 and the second pad 114 The upper surface ln. After that, I apply the hardenable ink i 30 to a predetermined position of the substrate by printing. In this embodiment, the hardenable ink i 30 is hardened. The ink 130 is coated in the opening 116, and the hardenable ink 130 is formed on the base electric layer 112. Next, referring to the redundant figure, before or after removing the mask 120 This ii (CUring) the hardenable ink 13〇 can be baked or matured to form a retaining wall 131 (dam). The chemical step is a necessary and important step, which is The supporting wall 1 3 1 formed by the hardenable weight can be solid and resistant to reflow temperature.
第9頁 1242818 ___ 五、發明說明(5) 設於該基板1 10。請參閱第3C與4圖,該擋牆131係具有_ 第一牆面132與一第二牆面133,並且該第一牆面132係面 朝向該第^一接塾11 3 ’該第二牆面1 3 3係面朝向該第二接塾 11 4,以利於在進行後續之回銲步驟時阻擋助銲劑。較佳 地,該擋牆1 3 1係具有相對高於該回銲溫度之熔點或玻璃 轉移溫度(glass transition temperature),不會在 0 {日 過程流動與變形。Page 9 1242818 ___ V. Description of the invention (5) It is located on the substrate 1-10. Please refer to FIGS. 3C and 4. The retaining wall 131 has a first wall surface 132 and a second wall surface 133, and the first wall surface 132 is oriented toward the first connection 11 3 'the second The wall surface 1 3 3 is facing the second connection 11 4 to facilitate blocking of the flux during the subsequent reflow step. Preferably, the retaining wall 1 3 1 has a melting point or glass transition temperature that is relatively higher than the reflow temperature, and does not flow and deform during the process of 0 {day.
之後’請參閱第3D與3E圖,以回銲錫奮方式銲接一被 動元件150至該第一接墊113與該第二接墊114 ,該被動元 件150係具有一第一電極151與一第二電極152,在回銲 後,該第一電極1 5 1係被一錫膏1 40接合至該第一接墊 113,該第二電極152被接合至該第二接墊114。在進行烘 烤回銲之前,係提供一助銲劑(f lux),例如松香,用以清 潔該第一接墊11 3與該第二接墊114之金屬表面。該助銲劑 係可被包含於該錫膏1 40内,或是額外自行塗設。請再參 閱第3 E圖,在回鮮時,該助銲劑係具有高流動性,但因其 受到該擔牆131的阻擔而不可在該第一接塾ns與該第二接 墊11 4之間流動,故助銲劑並不會集聚在該被動元件丨5 〇之 底部。較佳地’本發明之被動元件接合過程係另包含有一 助銲劑清洗步驟,由於該助銲劑並不會藏附於該被動元件 150之底部與該基板π〇之上表面ln之間,因此易於被清 除。請參閱第5圖,可以利用一破壞性試驗,拔除該被動 π件150,其係可發現所產生之助銲劑痕跡141相當少且不 會往該基板1 ίο在該第一接墊113與該第二接墊114之間的Afterwards, please refer to FIGS. 3D and 3E, and solder a passive element 150 to the first pad 113 and the second pad 114 by reflow soldering. The passive element 150 has a first electrode 151 and a second electrode. The electrode 152 is bonded to the first pad 113 by a solder paste 1 40 after re-soldering, and the second electrode 152 is bonded to the second pad 114. Before performing the baking reflow, a flux, such as rosin, is provided to clean the metal surfaces of the first pad 113 and the second pad 114. The flux can be contained in the solder paste 1 40, or it can be applied by itself. Please refer to FIG. 3E again. During the refreshing process, the flux has high fluidity, but because it is hindered by the supporting wall 131, it is not allowed to connect the first connection ns and the second connection pad 11 4 The flux flows between them, so the flux does not collect at the bottom of the passive component. Preferably, the passive component bonding process of the present invention further includes a flux cleaning step. Since the flux is not hidden between the bottom of the passive component 150 and the upper surface ln of the substrate π, it is easy Cleared. Referring to FIG. 5, a destructive test can be used to remove the passive π member 150, which can be found that the generated flux traces 141 are relatively small and will not go to the substrate 1. At the first pad 113 and the Between the second pads 114
第10頁 1242818 五、發明說明(6) 地,該=沪係為該擋牆131之阻擋效果所造成。較佳 色“广:色係相同或近似於該銲罩層115之顏 〜辨識该助銲劑痕跡141。 後續姑t於該基板11(3係適用於半導體封裝,在進行 一曰、M ISI ^中在該基板11 0之上表面111可設置至少Page 10 1242818 V. Description of the invention (6) The Shanghai system is caused by the blocking effect of the retaining wall 131. Better color: Wide: The color is the same or similar to the color of the solder mask layer 115 ~ Identify the flux trace 141. Subsequently, the substrate 11 (3 series is suitable for semiconductor packaging, and M ISI ^ The upper surface 111 of the substrate 110 may be provided at least
m _ 繪出),並可再執行一封膠步驟,請參閱第3F 膠俨係形成於該基板110之上表面111,該封 ;各 糸可岔該封晶片、該被動元件1 5 0與該經過回銲之 、月1/ 0。僅管該經過回銲之該錫膏i 4 〇之熱膨脹係數相當 大於該封膠體16 0之熱膨脹係數,但在烘烤固化該封膠體 160之過程,在該被動元件丨5〇底部不會殘留過量助銲劑, 不會幫助該錫膏14〇往該第一接墊113與該第二接墊114之 間衝流’達到内含被動元件之良好封裝品質。 依據本發明之第二具體實施例,第6圖係為一被動元 件銲接在一基板上之截面示意圖。一基板2丨〇係具有一上 表面211,在該上表面211係形成有一第一接墊2 12、一第 二接墊213以及一銲罩層214,該銲罩層214係顯露該第一 接墊212與該第二接墊213。在本實施例中,該第一接墊 212與該第二接墊2 13係為銲罩界定連接墊(Solder Mask Def ined pad,SMD pad)。之後,由一可硬化油墨加以熟 化形成之擋牆220係形成在該基板21 0之該上表面211上, 該擋牆2 2 0係位於該銲罩層2 1 4上且在該第一接墊21 2與該 第二接墊213之間。一錫膏230係形成於該第一接墊21 2與 該第二接墊2 13上,之後,回銲該錫膏230,以銲接一被動 Ηm _ draw), and can perform another glue step, please refer to the 3F glue system is formed on the substrate 110 on the top surface 111, the seal; each seal can branch the sealed wafer, the passive component 1 50 and After re-soldering, the month is 1/0. Although the thermal expansion coefficient of the solder paste i 4 〇 after re-soldering is considerably larger than the thermal expansion coefficient of the sealing compound 160, but in the process of baking and curing the sealing compound 160, there will be no residual at the bottom of the passive component Excessive flux will not help the solder paste 14 to flow between the first pad 113 and the second pad 114 to achieve a good package quality containing passive components. According to a second specific embodiment of the present invention, FIG. 6 is a schematic cross-sectional view of a passive component soldered to a substrate. A substrate 2 has an upper surface 211 on which a first pad 2 12, a second pad 213, and a solder mask layer 214 are formed. The solder mask layer 214 exposes the first The pad 212 and the second pad 213. In this embodiment, the first pads 212 and the second pads 2 13 are solder mask-defining pads (SMD pads). After that, a retaining wall 220 formed by curing with a hardenable ink is formed on the upper surface 211 of the substrate 21 0, and the retaining wall 2 2 0 is located on the welding mask layer 2 1 4 and on the first connection. Between the pad 21 2 and the second pad 213. A solder paste 230 is formed on the first pad 21 2 and the second pad 2 13, and then the solder paste 230 is re-soldered to solder a passive Η
IMI 第11頁 1242818IMI Page 11 1242818
第12頁 五、發明說明(7) 元件240,該被動元件240係具有一第一電極241與一第二 電極24 2,分別被銲接至該第一接墊2 1 2與該第二%墊 2 1 3。並且在回銲時所提供可清潔金屬表面之助銲劑係被 該擋牆220阻擋而不可在該第一接墊212與該第二接墊213 之間流動,以利清除,不會殘留在該被動元件24〇與該 板210之間。 本發明之保護範圍當視後附之申請專利範圍所界定者 任何熟知此項技藝者,在不脫離々 圍内所作之任何變化盥攸并仏府 奴κ货评和靶 改,均屬於本發明之保護輯圍。Page 12 V. Description of the invention (7) Element 240, the passive element 240 has a first electrode 241 and a second electrode 24 2 which are soldered to the first pad 2 1 2 and the second% pad, respectively. 2 1 3. In addition, the flux that can clean the metal surface provided during reflow is blocked by the retaining wall 220 and cannot flow between the first pad 212 and the second pad 213 to facilitate removal and not remain in the Between the passive element 24o and the board 210. The scope of protection of the present invention shall be deemed to be defined by the scope of the appended patent application. Any person who is familiar with the art and does not deviate from any changes within the scope of the scope and evaluation and target modification belongs to the present invention. Protection of the compilation.
圖式簡單說明 圖式簡單說明 第· 1 圖:習知被動元件銲接在一基板上之截面示意 圖, 。 第 2 圖 局部不意圖 習知在拔除被動元件之後,該基板之上表面 第3A至3F圖:依據本發明之第一具體實施例,一被動元件 在一基板上銲接過程之截面示意圖; 第4 圖:依據本發明之第一具體實施例,在銲接前該 基板之上表面局部示意圖;Brief Description of the Drawings Brief Description of the Drawings Figure 1: A schematic cross-sectional view of a conventional passive component soldered to a substrate. Figure 2 is not intended to be familiar. After removing the passive component, the upper surface of the substrate is 3A to 3F. According to the first specific embodiment of the present invention, a schematic cross-sectional view of the welding process of a passive component on a substrate; Figure: Partial schematic diagram of the upper surface of the substrate before soldering according to a first embodiment of the present invention;
第、5 —圖:依據本發明之第一具體實施例,在銲接並拔 除被動7L件之後,該基板之上表面局部示意圖;及 \ 6 圖·依據本發明之第二具體實施例,一被動元件 鲜接在一基板上之截面示意圖。 元件符號簡單說明 1 〇 基板 11 上 13 第二接墊 14 銲 20 錫膏 21 助 30 被動元件 31 間 110 基板 111 上 113 第一接墊 114 第 116 開口 120 遮 130 油墨 131 擋 133 第二牆面 表面 12 第一接墊 罩層 銲劑殘留痕跡 隙 表面 112介電層 二接墊 11 5銲罩層 罩 121開口 牆 132第一牆面Figures 5 and 5: According to the first specific embodiment of the present invention, a partial schematic diagram of the upper surface of the substrate after welding and removal of the passive 7L component; and Figure 6 according to the second specific embodiment of the present invention, a passive A schematic cross-sectional view of a component freshly attached to a substrate. Brief description of the component symbols 1 〇 On the substrate 11 13 Second pad 14 Solder 20 Solder paste 21 Help 30 Passive components 31 Room 110 On the substrate 111 On 113 First pad 114 The 116 Opening 120 Cover 130 Ink 131 Block 133 Second wall surface Surface 12 First solder mask layer residual trace gap surface 112 Dielectric layer two pads 11 5 solder mask layer 121 opening wall 132 first wall surface
第13頁 1242818 1 4 1 助銲劑殘留痕跡 151 第一電極 152 第二電極 圖式簡單說明 140錫膏 150被動元件 1 6 0 封膠體 2 1 0基板 2 1 3 第二接墊 2 2 1 第一牆面 2 4 0被動元件 211 上表面 214 銲罩層 2 2 2 第二牆面 241 第一電極 2 1 2 第一接墊 220擋牆 230錫膏 242 第二電極 aPage 13 1242818 1 4 1 Traces of flux residues 151 First electrode 152 Second electrode pattern Brief description 140 Solder paste 150 Passive component 1 6 0 Sealant 2 1 0 Substrate 2 1 3 Second pad 2 2 1 First Wall surface 2 4 0 Passive component 211 Upper surface 214 Solder mask layer 2 2 2 Second wall surface 241 First electrode 2 1 2 First pad 220 Retaining wall 230 Solder paste 242 Second electrode a
第14頁Page 14
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW93138381A TWI242818B (en) | 2004-12-10 | 2004-12-10 | Process of mounting a passive component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW93138381A TWI242818B (en) | 2004-12-10 | 2004-12-10 | Process of mounting a passive component |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI242818B true TWI242818B (en) | 2005-11-01 |
| TW200620492A TW200620492A (en) | 2006-06-16 |
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| TW93138381A TWI242818B (en) | 2004-12-10 | 2004-12-10 | Process of mounting a passive component |
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| TW (1) | TWI242818B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI428066B (en) * | 2011-11-21 | 2014-02-21 | 臻鼎科技股份有限公司 | Electronic component mounting method |
| CN104795363A (en) * | 2014-01-17 | 2015-07-22 | 菱生精密工业股份有限公司 | Copper-clad substrate with barrier structure and manufacturing method thereof |
| CN104867901A (en) * | 2014-02-25 | 2015-08-26 | 矽品精密工业股份有限公司 | Substrate structure and semiconductor package |
| CN112259531A (en) * | 2020-02-03 | 2021-01-22 | 友达光电股份有限公司 | Light emitting diode display |
| CN112993122A (en) * | 2020-09-24 | 2021-06-18 | 重庆康佳光电技术研究院有限公司 | Substrate, manufacturing method thereof and display panel |
| CN114695632A (en) * | 2020-12-25 | 2022-07-01 | 株式会社日本显示器 | LED module and display device including the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI460842B (en) * | 2011-01-24 | 2014-11-11 | 力成科技股份有限公司 | Mechanically assembled passive component package structure and substrate manufacturing method thereof |
-
2004
- 2004-12-10 TW TW93138381A patent/TWI242818B/en not_active IP Right Cessation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI428066B (en) * | 2011-11-21 | 2014-02-21 | 臻鼎科技股份有限公司 | Electronic component mounting method |
| CN104795363A (en) * | 2014-01-17 | 2015-07-22 | 菱生精密工业股份有限公司 | Copper-clad substrate with barrier structure and manufacturing method thereof |
| CN104867901A (en) * | 2014-02-25 | 2015-08-26 | 矽品精密工业股份有限公司 | Substrate structure and semiconductor package |
| CN112259531A (en) * | 2020-02-03 | 2021-01-22 | 友达光电股份有限公司 | Light emitting diode display |
| CN112259531B (en) * | 2020-02-03 | 2023-06-02 | 友达光电股份有限公司 | Light emitting diode display |
| CN112993122A (en) * | 2020-09-24 | 2021-06-18 | 重庆康佳光电技术研究院有限公司 | Substrate, manufacturing method thereof and display panel |
| CN114695632A (en) * | 2020-12-25 | 2022-07-01 | 株式会社日本显示器 | LED module and display device including the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200620492A (en) | 2006-06-16 |
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