TWI528461B - Semicondoctor process - Google Patents

Description

Semiconductor process

The present invention relates to a semiconductor process, and more particularly to a semiconductor process for forming a two-layer cap layer on a gate structure.

As the size of semiconductor components shrinks, maintaining the performance of small-sized semiconductor components is currently the main goal of the industry. In order to improve the performance of semiconductor components, various Fin-shaped field effect transistors (FinFETs) have been developed. The fin field effect transistor component has several advantages. First, the process of the fin field effect transistor device can be integrated with the conventional logic device process, so that it has considerable process compatibility. Secondly, since the three-dimensional structure increases the contact area between the gate and the substrate, the gate can be increased. Control of the charge in the channel region, thereby reducing the Drain Induced Barrier Lowering (DIBL) effect and the short channel effect caused by small-sized components; in addition, since the same length of the gate has more The large channel width also increases the amount of current between the source and the drain.

In general, the fin field effect transistor component includes a fin structure stacked on a substrate, a gate structure and a cap layer, and a spacer located on a side of the gate structure. In the process of forming a fin field effect transistor element, the method of forming the spacer is to completely cover a layer of spacer material and then etch the spacer on the side of the gate structure. How to control the height of the gate structure and the cover layer relative to the gap wall will affect the electrical quality of the fin field effect transistor component. For example, when the height of the spacer is lower than the thickness of the gate structure and the gate structure is exposed, the gate structure (generally composed of polysilicon or metal) may generate poly-bump in subsequent processes. Or leakage and other issues. Alternatively, when the spacer is higher than the height of the cap layer, the subsequent process time and process cost may be increased, or the subsequent process may be difficult. However, when the spacer material is etched to form the spacers, the spacer material on the substrate between the fin structures is difficult to etch clean, which may cause difficulty in subsequent processes such as epitaxy, metal telluride or contact plugs. If the etching time is to be completely removed, the problem of over-etching of the spacers is likely to occur, and the gate structure is exposed.

The invention provides a semiconductor process for forming a two-layer cap layer on a gate structure. When a spacer material is subsequently deposited and etched to form a spacer on the side of the gate structure, the gap between the fin structures can be completely removed. The wall material does not overetch the spacers to expose the gate structure.

The present invention provides a semiconductor process that includes the following steps. First, a fin structure is formed on a substrate. Next, a gate structure and a cap layer are formed, wherein the gate structure spans a portion of the fin structure and a portion of the substrate, the cap layer is on the gate structure, and the cap layer includes a first cap layer on the gate structure and A second cover layer is on the first cover layer. Subsequently, a spacer material is formed to cover the second cover layer, the fin structure and the substrate. Then, the spacer material is etched to expose the sidewalls of the second cap layer and form a spacer on the side of the gate structure. Then, the second cover layer is removed.

Based on the above, the present invention proposes a semiconductor process that forms a two-layer cap layer on the gate structure. In this way, after the formation of the two-layer cap layer, the spacer material is deposited and etched to completely remove the spacer material between the fin structures when the spacers are formed on the sides of the gate structure, but the over-etching is not excessively etched. The spacers, in turn, prevent the gate structure from being exposed, thereby avoiding problems such as poly-bump or leakage, and reducing the electrical quality of the formed semiconductor structure.

1-9 are perspective views of a semiconductor process in accordance with a first embodiment of the present invention. Figure 10 is a perspective view showing a semiconductor process of a second embodiment of the present invention. As shown in FIG. 1, a fin structure 112 is formed on a substrate 110. In detail, the substrate 110 is, for example, a substrate, a germanium-containing substrate, a tri-five-layer coated substrate (eg, GaN-on-silicon), a graphene-on-silicon or a germanium overlay. A semiconductor substrate such as a silicon-on-insulator (SOI) substrate. The method of forming the fin structure 112 may include providing a piece of substrate (not shown), forming a hard mask layer (not shown) thereon, and patterning it to define a bottom portion underneath The position of the fin structure 112 to be formed in the material. Next, an etching process is performed to form the fin structure 112 in a bulk substrate (not shown). Thus, the fabrication of the fin structure 112 on the substrate 110 is completed. In one embodiment, after forming the fin structure 112, the hard mask layer (not shown) is removed, and a three-gate tri-gate MOSFET can be formed in a subsequent process. As a result, since the fin structure 112 has three direct contact faces (including two contact sides and a contact top surface) between the subsequently formed dielectric layers, it is called a tri-gate field effect transistor (tri-gate). MOSFET). Compared with the planar field effect transistor, the three-gate field effect transistor can have a wider carrier channel width under the same gate length by using the above three direct contact surfaces as a channel through which the carrier flows. Double the drain drive current at the same drive voltage. In another embodiment, a hard mask layer (not shown) may be left, and another multi-gate MOSFET having a fin structure is formed in a subsequent process due to retention. A hard mask layer (not shown) has only two contact sides between the fin structure 112 and the subsequently formed dielectric layer.

In addition, as described above, the present invention can also be applied to other kinds of semiconductor substrates. For example, in another embodiment, an insulating substrate (not shown) is provided and etched by etching and lithography. The formation of the fin structure on the insulating substrate can be completed by covering the single crystal germanium layer on the insulating substrate (not shown) and stopping at the oxide layer. In addition, in order to clearly disclose the present invention, only two of the fin structures 112 of the present embodiment are shown, but the fin structures 112 to which the present invention can be applied may also be one or plural. A shallow trench isolation (STI) structure 114 is then formed between the fin structures 112.

As shown in FIG. 2, a gate structure 120 is formed to span a portion of the fin structure 112 and a portion of the substrate 110. The gate structure 120 can include a buffer layer (not shown), a dielectric layer 122, and a gate layer 124. The gate structure 120 further has a cap layer 130 for use as a hard mask for the etching process. The cap layer 130 is a stacked cap layer structure including a first cap layer 132 on the gate structure 120. And a second cap layer 134 on the first cap layer 132. For example, the buffer layer material (not shown), the dielectric layer material (not shown), the gate layer material (not shown), and the first cap layer material (not shown) may be completely and sequentially covered. And a second cover material (not shown). Then, the second cap layer material (not shown), the first cap layer material (not shown), the gate layer material (not shown), and the dielectric layer material are patterned, for example, by an etching and lithography process. The buffer layer material (not shown) is formed, and a stacked buffer layer (not shown), a dielectric layer 122, a gate layer 124, a first cap layer 132, and a second cap layer 134 are formed.

The buffer layer (not shown) may be, for example, an oxide layer; the dielectric layer 122 is, for example, a metal-containing dielectric layer, which may include a hafnium oxide or a zirconium oxide, but the present invention does not This is limited. Furthermore, the dielectric layer 122 can be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and hafnium silicon oxynitride (HfSiON). , aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), oxidation Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), yttrium Oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr) A group consisting of _1-x TiO ₃ , BST), but the invention is not limited thereto. In this embodiment, the gate layer 124 is a polysilicon sacrificial gate layer, which will be replaced by a metal gate in a subsequent process, but in other embodiments, the gate layer 124 may be a polysilicon layer or a Metal layer, etc. In the present embodiment, the first cap layer 132 is a nitride layer, and the second cap layer 134 is an oxide layer, but the invention is not limited thereto. In a preferred embodiment, the first cap layer 132 and the second cap layer 134 have different etch selectivity ratios, that is, for an etch process, the two have different etch rates. As a result, when the second cap layer 134 is removed in the subsequent process, the first cap layer 132 can be completely retained without causing the first cap layer 132 to be damaged due to over-etching.

As shown in Fig. 3, the blanket forming a spacer material 140' covers the second cover layer 134, the fin structure 112, and the substrate 110 in its entirety. The spacer material 140' is, for example, a single layer or a multilayer composite structure composed of a material such as tantalum nitride or tantalum oxide.

The first embodiment is respectively presented below, as shown in Figures 4-6; or the second embodiment is shown in Figure 10. The two embodiments depend on the etching selectivity of the second cap layer 134 and the spacer material 140', the relative thickness of the second cap layer 134 and the portion of the fin structure 112a that protrudes from the shallow trench isolation structure 114.

First embodiment:

As shown in Fig. 4, the spacer material 140' is etched to form spacers 140 on a portion of the substrate 110 on the side of the gate structure 120, and substantially, the spacers 140 are not formed on the sides of the fin structure 112. Furthermore, in the present embodiment, the height H of the spacer 140 is preferably greater than (including equal to) the thickness h1 of the gate structure 120, but less than (including equal to) the thickness of the gate structure 120 plus the first cap layer 132. H1+h2, that is, the top end of the spacer 140 is located on the side wall of the first cap layer 132, and the sidewall of the second cap layer 134 is completely exposed. In this way, the gate structure 120 can be prevented from being exposed, and when the second cap layer 134 is removed in a subsequent process, there is no problem that the spacer wall 140 protrudes from the top surface S1 of the first cap layer 132. In a specific implementation, the present embodiment can control the height H of the spacer 140 by adjusting the thickness of the second cap layer 134 and selecting the second cap layer 134 and the spacer material 140' to have an appropriate etching selectivity. For example, when the thickness of the second cap layer 134 and the portion of the fin structure 112a protruding from the shallow trench isolation structure 114 are the same, the material whose etching rate of the second cap layer 134 is smaller than the etching rate of the spacer material 140' may be selected. Since the etch rate of the spacer material 140' is faster, a structure in which the second cap layer 134 remains and the sidewalls of the second cap layer 134 are completely exposed when the spacer 140 is formed can be generated as shown in FIG. At this time, the spacer material 140' between the fin structures 112 other than the spacers 140 has been completely removed. In addition, when the etching rate of the second cap layer 134 is equal to the etching rate of the spacer material 140', the thickness of the second cap layer 134 may be set to be larger than the thickness of the portion of the fin structure 112a protruding from the shallow trench isolation structure 114. As a result, when the spacer 140 is formed, the second cap layer 134 remains, and the sidewall of the second cap layer 134 has completely exposed the structure, and the gap between the fin structures 112 other than the spacer 140 is completely removed. Wall material 140'. Of course, the second cap layer 134 and the spacer material 140' having different etching selectivity ratios, and the second cap layer 134 having different thicknesses and the partial fin structure 112a protruding from the shallow trench isolation structure 114 may also be selected, depending on the process And actual structural needs. In addition, since the spacer material 140' is a single layer or a multilayer composite structure composed of a material such as tantalum nitride or tantalum oxide, the spacer 140 may be, for example, a single layer composed of a material such as tantalum nitride or tantalum oxide or Multi-layer composite structure.

Next, as shown in FIGS. 5-6, the second cap layer 134 on the first cap layer 132 is removed. In detail, as shown in FIG. 5, a photoresist P is formed to cover the fin structure 112 and the substrate 110, and the second cap layer 134 is exposed. Next, as shown in FIG. 6, the second cover layer 134 is removed. Then, remove the photoresist P.

In this embodiment, the height H of the spacer 140 can be well controlled according to the parameter adjustment of the appropriate etching selection ratio and relative thickness, but in other embodiments or due to process variation, the spacer 140 protrudes from the first cap layer. The top surface S1 of the 132 may be removed from the spacer 140 protruding from the top surface S1 of the first cap layer 132 by a planarization process or other processes in the subsequent process after the second cap layer 134 is removed.

In this embodiment, the spacers 140 are formed first, and then the second cap layers 134 are completely removed. The next embodiment completely removes the second cap layer 134 while forming the spacers 140.

Second embodiment:

As shown in Fig. 10, when the spacers 140 are formed by etching the spacer material 140', the second cap layer 134 is completely removed. In detail, when the etching rate of the second cap layer 134 is equal to the etching rate of the spacer material 140', the thickness of the second cap layer 134 may be set to be equal to the thickness of the partial fin structure 112a protruding from the shallow trench isolation structure 114. As such, the second cap layer 134 can be removed together when the spacers 140 are formed, and the spacer material 140' between the fin structures 112 other than the spacers 140 is completely removed. Alternatively, the spacer 140 can be formed by adjusting the etching rate of the second cap layer 134 and the spacer material 140', and the thickness of the second cap layer 134 and a portion of the fin structure 112a protruding from the shallow trench isolation structure 114. At the same time, the second cap layer 134 is removed, and the spacer material 140' between the fin structures 112 other than the spacers 140 is completely removed. Of course, in the present embodiment, it is preferable to consider that the height H of the finally formed spacer 140 is greater than the thickness h1 of the gate structure 120, but smaller than the thickness h1+h2 of the gate structure 120 plus the first cap layer 132. In this way, the gate structure 120 can be prevented from being exposed, and there is no problem that the spacers 140 protrude from the top surface S1 of the first cap layer 132.

According to the above two embodiments, it is emphasized that when the spacer material 140' is etched to form the spacer 140, the height of the spacer 140 formed is preferably greater than (including equal to) the thickness h1 of the gate structure 120 to avoid the gate. The pole structure 120 is exposed; and the height of the spacer 140 is preferably lower than (including equal to) the top surface S1 of the first cover layer 132 to avoid the spacer after the second cover layer 134 is removed in the subsequent process (not drawn The protrusions are protruded from the first cap layer 132, resulting in an increase in subsequent process time and cost or difficulty in the process. Further, when the spacer 140 is formed, the spacer material 140' other than the spacer 140 needs to be completely removed. However, after forming the spacers 140, the spacer material 140' on the substrate 110 between the fin structures 112 remains. Although the spacer material 140' is removed by over-etching, the spacers 140 are caused to pass. Etching exposes the gate structure 120. Accordingly, the present invention is directed to a method of forming the first cap layer 132 and the second cap layer 134 to solve this problem.

As shown in FIGS. 4-6 (or as shown in FIG. 10), after the spacers 140 are formed, as shown in FIG. 7, an epitaxial structure 152 is selectively formed on the fin structures 112. In other embodiments, an epitaxial structure 152 can also be formed in the fin structure 112. In this embodiment, the second cap layer 134 is removed to form the epitaxial structure 152. However, in another embodiment, the epitaxial structure 152 may be formed first, and then the second cap layer 134 may be removed, depending on the process and Depending on the situation. Next, a source/drain region 154 is formed in the fin structure 112 on the side of the spacer 140, for example, by a bevel ion implantation process. In the present invention, the second cap layer 134 is removed to form a source/drain region 154, so that the bevel ion implantation process can be sufficiently performed on the top and sidewall of the fin structure 112, and in the fin structure 112. The source/drain regions 154 are formed intact, but the invention is not limited thereto. In the present embodiment, the source/drain region 154 is completely included in the epitaxial structure 152, but in other embodiments, the epitaxial structure 152 may also be completely contained in the source/drain region 154, or epitaxial. Only a portion of the structure 152 and the source/drain regions 154 overlap.

Then, a metal telluride (not shown) is selectively formed on the source/drain region 154, and a contact etch stop (CESL) layer (not shown) and an interlayer dielectric layer (not shown) are completely covered. The fin structure 112, the substrate 110, and the first cap layer 132 are further subjected to, for example, a chemical mechanical polishing process to planarize the interlayer dielectric layer (not shown), and the first cap layer may be removed together during planarization. 132, an interlayer dielectric layer 160 is formed and the gate layer 124 is exposed.

As shown in Figures 8-9, a metal gate replacement process is performed to replace the gate layer 124 with the metal gate 170. In detail, as shown in FIG. 8, for example, the gate layer 124 is removed by an etching process to etch a groove R. This embodiment is an example of a Gate Last for High-K First process before the high dielectric constant dielectric layer is formed. Therefore, the dielectric layer 122 is exposed after etching the recess R. However, in other embodiments, the dielectric layer 122 is also etched away to expose the buffer layer if it is a gated high dielectric constant layer (Gate Last for High-K Last) process. The invention is not limited thereto, and the invention can also be applied to a Gate Last for High-K Last (Buffer Layer First) process after the front buffer layer is followed by a high dielectric constant dielectric layer or The post-buffer layer is followed by a high-potential dielectric layer (Gate Last for High-K Last, Buffer Layer Last) process.

As shown in FIG. 9, a barrier layer (not shown) is selectively formed to conformably cover the recess R, wherein the barrier layer (not shown) may be made of titanium, titanium nitride, tantalum, tantalum nitride, or the like. The single or multilayer structure formed by the material to avoid diffusion of metal atoms subsequently formed thereon. Continuing, a work function metal layer (not shown) and a low resistivity material (not shown) are formed on the barrier layer (not shown), and the low resistivity material (not shown) and the work are formed. A function metal layer (not shown), a barrier layer (not shown) are planarized to form a barrier layer (not shown), a work function metal layer 172, and a low resistivity material 174 in the recess R, Form the desired fin field effect transistor component. The work function metal layer 172 is a metal that satisfies the required work function of the transistor, and may be a single layer structure or a composite layer structure, such as titanium nitride (TiN), titanium carbide (TiC), Tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminide (TiAl) or aluminum titanium nitride (TiAlN) . Moreover, the work function metal layer 170 can be, for example, a titanium metal layer suitable for forming a PMOS transistor (having a work function between about 4.8 eV and 5.2 eV). Of course, the work function metal layer can also be, for example, a titanium aluminide metal layer suitable for forming an NMOS transistor (the work function is between about 3.9 eV and 4.3 eV). The low resistivity material 174 may be composed of a low resistance material 174 such as aluminum, tungsten, titanium aluminum alloy (TiAl) or cobalt tungsten phosphide (CoWP).

In summary, the present invention provides a semiconductor process that forms a stacked first cap layer and a second cap layer on the gate structure. In this way, when the spacer material is deposited and etched subsequently to form a spacer on the side of the gate structure, the spacer material between the fin structures can be completely removed, but the spacer is not excessively etched, thereby preventing The gate structure is exposed to avoid problems such as poly-bump or leakage, which reduces the electrical quality of the formed semiconductor structure. Specifically, the foregoing objects can be achieved by adjusting the etching selectivity of the second cap layer and the spacer material, or/and the relative thickness of the second cap layer and a portion of the fin structure protruding from the shallow trench isolation structure. The process step can be, for example, method 1: etching the spacer material to form a spacer, and after exposing the second cover layer, removing the second cover layer. Method 2: When the spacer material is etched to form the spacer, the second cover layer is completely removed. In addition, the first cap layer and the second cap layer preferably have different etching selectivity ratios, that is, for an etching process, the two have different etching rates. As such, when the second cap layer is subsequently removed, the first cap layer can be completely retained without causing the first cap layer to be damaged due to over-etching.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

110. . . Base

112. . . Fin structure

112a. . . Partial fin structure

114. . . Shallow trench isolation structure

120. . . Gate structure

122. . . Dielectric layer

124. . . Gate layer

130. . . Cover

132. . . First cover

134. . . Second cover

140. . . Clearance wall

140’. . . Spacer material

152. . . Epitaxial structure

154. . . Source/bungee area

160. . . Interlayer dielectric layer

170. . . Metal gate

172. . . Work function metal layer

174. . . Low resistivity material

H. . . height

H1, h1+h2. . . thickness

P. . . Photoresist

R. . . Groove

S1. . . Top surface

1-9 are perspective views of a semiconductor process in accordance with a first embodiment of the present invention.

Figure 10 is a perspective view showing a semiconductor process of a second embodiment of the present invention.

110. . . Base

112. . . Fin structure

112a. . . Partial fin structure

114. . . Shallow trench isolation structure

120. . . Gate structure

122. . . Dielectric layer

124. . . Gate layer

130. . . Cover

132. . . First cover

134. . . Second cover

140. . . Clearance wall

H. . . height

H1, h1+h2. . . thickness

S1. . . Top surface

Claims (19)

A semiconductor process includes: forming a fin structure on a substrate; forming a gate structure and a cap layer, wherein the gate structure spans a portion of the fin structure and a portion of the substrate, the cap layer is on the gate a pole structure, and the cover layer comprises a first cover layer on the gate structure and a second cover layer on the first cover layer; forming a spacer material to completely cover the second cover layer and the fin a structure and the substrate; etching the spacer material to expose all sidewalls of the second cap layer to form a spacer on a side of the gate structure and covering a portion of the sidewall of the first cap layer; and removing the sidewall Second cover layer. The semiconductor process of claim 1, wherein the first cap layer and the second cap layer have different etching selectivity ratios. The semiconductor process of claim 2, wherein the first cap layer comprises a nitride layer and the second cap layer comprises an oxide layer. The semiconductor process of claim 1, wherein the second cap layer and the spacer material have different etch selectivity ratios. The semiconductor process of claim 4, wherein the spacer material comprises a nitride layer and the second cover layer comprises an oxide layer. The semiconductor process of claim 1, wherein the second cap layer is completely removed after etching the spacer material. The semiconductor process of claim 1, wherein the second cap layer is completely removed when the spacer material is etched. The semiconductor process of claim 1, wherein the thickness of the second cap layer is equal to the thickness of the fin structure. The semiconductor process of claim 1, wherein the cover layer has a thickness greater than a thickness of the fin structure. The semiconductor process of claim 1, wherein after removing the second cap layer, further comprising: forming a source/drain region in the fin structure on a side of the spacer. The semiconductor process of claim 10, wherein before forming the source/drain region, the method further comprises: forming an epitaxial structure on the fin structure or in the fin structure. The semiconductor process of claim 11, wherein the epitaxial structure is formed after removing the second cap layer. The semiconductor process of claim 11, wherein the epitaxial structure is formed prior to removing the second cap layer. The semiconductor process of claim 10, wherein after forming the source/drain region, further comprising: forming an interlayer dielectric layer to completely cover the first cap layer, the fin structure, and the substrate; The interlayer dielectric layer is planarized to remove the first cap layer. The semiconductor process of claim 14, wherein after removing the first cap layer, further comprising: performing a metal gate replacement process. The semiconductor process of claim 1, wherein the spacer material other than the spacer is completely removed when the spacer material is etched. The semiconductor process of claim 1, wherein etching the spacer material completely exposes sidewalls of the second cap layer. The semiconductor process of claim 1, wherein the spacer has a height greater than a thickness of the gate structure and less than a thickness of the gate structure plus the first cap layer. The semiconductor process as described in claim 1 of the patent application, in forming the gate structure The method further includes: forming a shallow trench isolation structure between the gate structure and a portion of the substrate.