TWI521705B - Finfet and method of fabricating finfet - Google Patents

Description

Fin field effect transistor and its process

The present invention relates to a fin field effect transistor (FinFETs) and a process thereof, and in particular to a fin field effect transistor (FinFETs) and a process thereof, which are modified in a field effect transistor by performing a processing process The physical or chemical properties of the metal layer.

In the conventional semiconductor industry, polycrystalline lanthanide is widely used in semiconductor components such as metal-oxide-semiconductor (MOS) transistors as a standard gate filling material. However, as the size of the MOS transistor continues to shrink, the conventional polysilicon gate causes a decrease in component efficiency due to boron penetration effects, and an unavoidable depletion effect, etc., resulting in an equivalent gate. The thickness of the dielectric layer increases, and the value of the gate capacitance decreases, which leads to the dilemma of the deterioration of the component driving capability. Therefore, the semiconductor industry has tried to replace the traditional polysilicon gate with a new gate filling material, for example, by using a work function metal to form a metal gate for matching a high dielectric constant (High-K). The control electrode of the gate dielectric layer.

However, with the development of semiconductor components, their specifications and performance requirements have become increasingly stringent. How to further improve the electrical properties of the metal gate, such as the threshold voltage of the metal gate, in order to achieve the desired specifications of the semiconductor components under various process limitations, limitations of various material characteristics, and size limitations of semiconductor components. The problem.

The invention provides a fin field effect transistor (FinFET) and a process thereof for changing a physical property or a chemical property of a metal layer in a field effect transistor by performing a processing process to improve a threshold voltage of, for example, a metal layer The electrical properties of the field effect transistor.

The present invention provides a fin field effect transistor (FinFET) process comprising the following steps. First, a substrate is provided. Next, a first fin field effect transistor and a second fin field effect transistor are formed on the substrate, wherein the first fin field effect transistor comprises a first metal layer, and the second fin field effect transistor The crystal contains a second metal layer. Then, a processing process is performed on the first metal layer, and the threshold voltage of the first fin field effect transistor is changed.

The invention provides a field effect transistor, comprising a first fin field effect transistor having the same conductivity and a second fin field effect transistor on a substrate, wherein the first fin field effect transistor comprises a The first metal layer, the second fin field effect transistor comprises a second metal layer, and the first metal layer and the second metal layer are of the same material but different thicknesses.

The invention provides a field effect transistor, comprising a first fin field effect transistor having the same conductivity and a second fin field effect transistor on a substrate, wherein the first fin field effect transistor comprises a The first metal layer, the second fin field effect transistor comprises a second metal layer, and the first metal layer and the second metal layer are different materials.

Based on the above, the present invention provides a fin field effect transistor and a process thereof, which perform a processing process on at least one of two or more fin field effect transistors to individually change the fin field effect The physical or chemical properties of the metal layer in the transistor, which in turn changes the overall electrical parameters such as the threshold voltage of the fin field effect transistor.

1-2 are perspective views of a fin field effect transistor process in accordance with an embodiment of the present invention. As shown in Fig. 1, first, a substrate 110 is provided. Then, a first fin field effect transistor 120' and a second fin field effect transistor 130' are formed on the substrate 110.

In detail, the method of forming the first fin field effect transistor 120' and the second fin field effect transistor 130' may include providing a piece of substrate (not shown) on which a hard mask is formed a layer (not shown) and patterned to define a first fin structure 124 and a second fin shape of the first fin field effect transistor 120' to be formed correspondingly in the underlying bulk substrate The second fin structure 134 of the field effect transistor 130' is at the location of the substrate 110. Then, an etching process is performed to form the first fin structure 124 and the second fin structure 134 on the substrate 110 in a bulk substrate (not shown). Thus, the fabrication of the first fin structure 124 and the second fin structure 134 on the substrate 110 is completed.

Then, an insulating structure 112 is formed on the substrate 110 between the first fin structure 124 and the second fin structure 134. The insulating structure 112 may be a shallow trench insulating structure, but the invention is not limited thereto. . In one embodiment, after forming the first fin structure 124 and the second fin structure 134, the hard mask layer (not shown) is removed, and a three-gate field effect transistor (tri-) can be formed in a subsequent process. Gate MOSFET). As a result, since the first fin structure 124 and the second fin structure 134 and the subsequently formed dielectric layer have three direct contact surfaces (including two contact sides and a contact top surface), it is called a three gate. Polar field effect transistor (tri-gate MOSFET). Compared with the planar field effect transistor, the three-gate field effect transistor can have a wider carrier channel width under the same gate length by using the above three direct contact surfaces as a channel through which the carrier flows. Double the drain drive current at the same drive voltage. In another embodiment, a hard mask layer (not shown) may be left, and another multi-gate MOSFET having a fin structure may be formed in a subsequent process. Since the hard mask layer (not shown) is retained, there are only two contact sides between the first fin structure 124 and the second fin structure 134 and the dielectric layer to be subsequently formed.

In addition, as described above, the present invention can also be applied to other kinds of semiconductor substrates. For example, in another embodiment, a covered insulating substrate (not shown) is provided and etched by etching and lithography. The formation of the fin structure on the insulating substrate can be completed by covering the single crystal germanium layer on the insulating substrate (not shown) and stopping at the oxide layer.

In addition, in order to clearly disclose the present invention, the first fin structure 124 and the second fin structure 134 are illustrated in the first embodiment, but the first fin field effect transistor 120' and the second fin field effect transistor. In 130', the fin structure to which the present invention can be applied may also be one or more than two.

Then, after the first fin structure 124 and the second fin structure 134 are formed, a dielectric layer (not shown), an electrode layer (not shown), and a cap layer (not shown) are sequentially formed. The first fin structure 124 and the second fin structure 134 are disposed on the first fin structure 124 and then patterned to form a dielectric layer 142, an electrode layer 144, and a cap layer 146. Then, a sidewall 148 is formed on the side of the dielectric layer 142, the electrode layer 144, and the cap layer 146. The dielectric layer 142 may include an oxide layer; the electrode layer 144 may be a polysilicon layer; the cap layer 146 may be a nitride layer, but the invention is not limited thereto. Then, a source/drain region 149 is formed in the first fin structure 124 and the second fin structure 134 on the side of each sidewall 148, respectively, by a process such as oblique ion implantation. Thus, the fabrication of the first fin field effect transistor 120' and the second fin field effect transistor 130' is completed. Of course, the first fin field effect transistor 120' and the second fin field effect transistor 130' have a polycrystalline germanium electrode at this time, which will be replaced by a metal electrode in a subsequent process. In addition, the present invention can also be integrated into a gate-first process, and the electrode layer 144 is formed by directly selecting a suitable metal material layer together with the polysilicon layer.

As shown in FIG. 2, an interlayer dielectric layer (not shown) is overlaid on the substrate 110, the first fin structure 124, the second fin structure 134, the sidewall spacers 148, and the cap layer 146, and then planarized. An interlayer dielectric layer 150 is formed. Wherein, the planarization process may include a process such as chemical mechanical polishing or etching, and the cap layer 146 is removed together to expose the electrode layer 144. Thereafter, the electrode layer 144 is removed to form a recess R. In the subsequent process, each metal material is filled into the recesses R of the first fin structure 124 and the second fin structure 134 to form a first fin field effect transistor 120 and a second. The fin field effect transistor 130, which may comprise different or identical metal layers. In order to clearly reveal the structures of the first fin field effect transistor 120 and the second fin field effect transistor 130, the following section 3-10 shows the AA' section line and BB along the second figure. A schematic cross-sectional view of the first fin field effect transistor 120 and the second fin field effect transistor 130 as viewed in the section line.

As shown in Fig. 3, it is a schematic cross-sectional view taken along line AA' and BB' hatching in Fig. 2. The sidewall 148 and the interlayer dielectric layer 150 are respectively disposed on the first fin structure 124 and the second fin structure 134. The source/drain region 149 is located in the first fin structure 124 and the second fin structure 134 on the side of the sidewall spacer 148. The sidewall 148 surrounds a recess R to expose a portion of the first fin structure 124 and the second fin structure 134. In detail, as shown in the hatching of FIG. 2AA, the first fin field effect transistor 120 is formed on the first fin structure 124, and in the third figure, the C area is correspondingly formed to form the first a region of the fin field effect transistor 120; and as shown in the BB' hatching of FIG. 2, a second fin field effect transistor 130 is formed on the second fin structure 134, and the D region is formed correspondingly. The area of the second fin field effect transistor 130.

As shown in FIG. 4, a buffer layer 162 and a dielectric layer 164 are sequentially formed on the first fin structure 124 and the second fin structure 134. The buffer layer 162 is, for example, an oxide layer, and the dielectric layer 164 is typically a high-k dielectric layer. The high-k dielectric layer may be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), and oxidation. Aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconia ( Zirconium oxide, ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), niobium oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr _1- A group consisting of _x TiO ₃ , BST).

As shown in FIG. 5, a bottom barrier layer 172 is formed on the dielectric layer 164. The bottom barrier layer 172 can be, for example, a titanium nitride layer, but the invention is not limited thereto. Next, in the embodiment, a bottom process barrier layer 172 of the D region may be selectively performed to change the physical properties or chemical properties of the bottom barrier layer 172 of the D region to change the D region. The work function of the gate electrode of the formed transistor, in turn, changes the threshold voltage of the transistor formed in the D region. Of course, in another embodiment, only one processing process P1 may be performed on the bottom barrier layer 172 of the C region to change the threshold voltage of the transistor formed in the C region. Alternatively, different processing processes are respectively performed on the bottom barrier layer 172 of the C region and the bottom barrier layer 172 of the D region, and the threshold voltage of the transistor formed in the C region and the electricity formed in the D region are respectively adjusted. The threshold voltage of the crystal. As shown in FIG. 5, only the processing process P1 is shown in the D region, which means that the processing process P1 acts only on the bottom barrier layer 172 of the D region. However, in practice, for example, a patterned mask (not shown) may be used to cover the C region to expose the D region, and then the processing process P1 may be fully performed, so that only the bottom barrier of the D region can be achieved. The purpose of the layer 172 is the same, and vice versa, the processing of the C area is also the same, and will not be described here.

After forming the bottom barrier layer 172 on the dielectric layer 164, an etch stop layer (not shown) may be selectively formed on the bottom barrier layer 172, wherein the etch stop layer (not shown) may include a The tantalum nitride layer, but the invention is not limited thereto.

It should be noted that the processing process P1 may include an etching process, a doping process, an oxidation process, a nitridation process, or a fluorination process, but the invention is not limited thereto. The processing process P1 functions to change the physical properties and/or chemical properties of the bottom barrier layer 172, wherein the physical properties may include the thickness, hardness, density, or reflectivity of the bottom barrier layer 172, and the chemical properties may include a bottom resistance. Bonding, reactivity or etching rate of the barrier layer 172. In this way, the present invention can change the physical properties or chemical properties of the bottom barrier layer 172 by performing at least one processing process, thereby adjusting the threshold voltage isoelectric parameters of the formed transistor to meet the requirements of the component. In addition, the processing process P1 of the present invention may be performed after the underlying barrier layer 172 is formed, or may be performed after forming an etch stop layer (not shown), or may be performed separately after forming both. Of course, the practice of the invention can also be applied to other metal layers that are subsequently formed.

As shown in FIG. 6, a first work function layer 174 is formed on the bottom barrier layer 172, wherein the first work function layer 174 includes a titanium nitride layer or an aluminum titanium layer, but the invention is not limited thereto. Depending on the electrical properties of the transistor. Thereafter, a processing process P2 can be selectively performed on the first work function layer 174 of the D region to change the work function of the gate electrode of the transistor formed in the D region, thereby changing the transistor formed in the D region. Threshold voltage. Similarly, as shown in FIG. 6, only the processing process P2 is shown in the D region, indicating that the processing process P2 acts only on the first work function layer 174 of the D region. However, in practice, for example, a patterned mask (not shown) may be used to cover the C area to expose the D area, and then the processing process P2 may be fully performed, so that only the first work of the D area can be achieved. The purpose of function layer 174 is to serve. On the contrary, the handling of the C area is also the same, and will not be repeated here.

Similarly, the processing process P2 may include an etching process, a doping process, an oxidation process, a nitridation process, or a fluorination process, but the invention is not limited thereto. The effect of the processing process P2 may change the physical properties and/or chemical properties of the first work function layer 174, wherein the physical properties may include the thickness, hardness, density, or reflectivity of the first work function layer 174, etc., and the chemical properties may include Bonding, reactivity or etching rate of the first work function layer 174, and the like. In this way, the present invention can change the physical properties or chemical properties of the first work function layer 174 by performing at least one processing process, thereby adjusting the threshold voltage isoelectric parameters of the formed transistor to meet the requirements of the component. .

In addition, in another embodiment of the present invention, the metal layers of the first fin field effect transistor and the work function layer of the second fin field effect transistor may also be different materials or stacked structural layers, such as Figures 7-8. As shown in FIG. 7, a mask layer P is overlaid on the D region to remove the first work function layer 174 of the C region. As shown in FIG. 8, a second work function layer 176 is formed on the bottom barrier layer 172 of the C region. In this embodiment, the second work function layer 176 includes a titanium nitride layer or an aluminum titanium layer, but the invention is not limited thereto, and depends on the electrical properties of the transistor. Then, a processing process P3 can be selectively performed on the second work function layer 176. Since the mask layer P has covered the D region, the processing process P3 acts only on the second work function layer 176. The processing process P3 is similar to the processing processes P1 and P2, and therefore will not be described again.

Alternatively, after removing the first work function layer 174 of the C region as shown in FIG. 7, the mask layer P is removed, and a second work function layer 176 is simultaneously formed on the bottom barrier layer 172 of the C region and The first work function layer 174 of the D region. Then, a processing process P3 can be selectively performed on the second work function layer 176 of the C region and/or the D region to change the work function of the gate electrode of the transistor formed in the C region and/or the D region. The threshold voltage of the transistor formed in the C region and/or the D region is further changed. The processing process P3 is similar to the processing processes P1 and P2, and therefore will not be described again.

As shown in FIG. 9, a top barrier layer 178 is simultaneously formed on the second work function layer 176 of the C region and the first work function layer 174 of the D region. The top barrier layer 178 is, for example, a titanium nitride layer or the like. As shown in FIG. 10, a low resistivity material 180 is formed over the top barrier layer 178. The low resistivity material 180 can be composed, for example, of a material such as aluminum or copper. After forming the top barrier layer 178, or after forming the low resistivity material 180, a processing process (like the processing processes P1, P2, and P3) may be selectively performed to adjust the top barrier of the C or D region. The physical properties and/or chemical properties of layer 178 or low resistivity material 180. Finally, each metal layer can be re-planarized to expose the interlayer dielectric layer, as well as various subsequent transistor processes.

In general, the first fin field effect transistor 120 can include a first metal layer including at least one barrier layer (eg, a bottom barrier layer 172 and a top barrier layer 178), a first work a function layer 174 and a stacked metal layer such as a low resistivity material 180; the second fin field effect transistor 130 may include a second metal layer including at least one barrier layer (eg, a bottom barrier layer 172 and A top barrier layer 178), a second work function layer 176, and a low resistivity material 180 are stacked metal layers. The present invention achieves modulation first by performing at least one processing process to individually change at least one of the first metal layers or individually change the physical properties and/or chemical properties of at least one of the second metal layers. The purpose of the overall electrical properties of the fin field effect transistor 120 or the second fin field effect transistor 130. For example, the threshold voltage of the first fin field effect transistor 120 or the second fin field effect transistor 130 is modulated. Specifically, the processing process may include an etching process, a doping process, an oxidation process, a nitridation process, or a fluorination process, etc., and the material properties that can be adjusted may be, for example, a work function value, a volume, and a gate. Extreme leakage current, equivalent current density, etc.

It should be noted that in the present invention, both the first fin field effect transistor 120 and the second fin field effect transistor 130 have the same conductivity type. Specifically, the first fin field effect transistor 120 and the second fin field effect transistor 130 may both be N-type transistors or may all be P-type transistors. In other words, by using the processing process of the present invention, the threshold voltage isoelectric parameters of the same electrical fin field effect transistor 120 can be changed. In this way, the function of individually fine-tuning the same electrical transistor can be achieved to meet the requirements of each component.

For example, as depicted in FIG. 10, the present invention can form a field effect transistor, which can include a first fin field effect transistor 120 and a second fin field effect transistor 130 having the same conductivity. Located on a substrate 110. For example, the first fin field effect transistor 120 and the second fin field effect transistor 130 are all N-type transistors. Or for example, the first fin field effect transistor 120 and the second fin field effect transistor 130 are all P-type transistors. The first fin field effect transistor 120 includes a first metal layer, which may include at least one barrier layer (eg, a bottom barrier layer 172 and a top barrier layer 178), a first work function layer 174, and a The low resistivity material 180; the second fin field effect transistor 130 may include a second metal layer including at least one barrier layer (eg, a bottom barrier layer 172 and a top barrier layer 178), a first A two work function layer 176 and a low resistivity material 180.

In an embodiment, for example, an etching process may be performed on at least one of the first metal layer or the second metal layer to change the thickness thereof, so that the first metal layer and the second metal layer are the same material but different. thickness. Alternatively, in another embodiment, for example, a modification process may be performed on at least one of the first metal layer or the second metal layer to change its chemical properties, so that the first metal layer and the second metal layer have Different materials.

In addition, in other embodiments, the present invention is also applicable to fin field effect transistors having different conductivity types. For example, the first fin field effect transistor 120 can be a P-type transistor and the second fin field effect transistor 130 can be an N-type transistor. As such, the first fin field effect transistor 120 and the second fin field effect transistor 130 may employ a first work function layer 174 as a titanium nitride layer and a second work function layer 176 as an aluminum titanium layer to match differently. The first fin field effect transistor 120 and the second fin field effect transistor 130 are electrically limited, but the invention is not limited thereto.

In summary, the present invention provides a fin field effect transistor and a process thereof for performing at least one of two or more fin field effect transistors to individually change each fin shape. The physical and/or chemical properties of the metal layer in the field effect transistor, which in turn changes the overall electrical parameters of the fin field effect transistor. For example, the threshold voltage isoelectricity of the fin field effect transistor is required to meet the component requirements. Specifically, the processing process may include an etching process, a doping process, an oxidation process, a nitridation process, or a fluorination process. The physical properties of the metal layer that can be altered by the processing process can be, for example, the thickness, hardness, density, or reflectivity of the metal layer, and the chemical properties of the metal layer can be, for example, the bonding, reactivity, or etch rate of the metal layer.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

110. . . Base

112. . . Insulation structure

120, 120’. . . First fin field effect transistor

124. . . First fin structure

130, 130’. . . Second fin field effect transistor

134. . . Second fin structure

142. . . Dielectric layer

144. . . Electrode layer

146. . . Cover

148. . . Side wall

149. . . Source/bungee area

150. . . Interlayer dielectric layer

162. . . The buffer layer

164. . . Dielectric layer

172. . . Bottom barrier

174. . . First work function layer

176. . . Second work function layer

178. . . Top barrier

180. . . Low resistivity material

C, D. . . region

P. . . Mask layer

P1, P2, P3. . . Processing process

R. . . Groove

1-2 are perspective views of a fin field effect transistor process in accordance with an embodiment of the present invention.

Fig. 3-10 is a schematic cross-sectional view showing the process of the fin field effect transistor according to the AA' hatching and the BB' hatching in Fig. 2.

110. . . Base

124. . . First fin structure

134. . . Second fin structure

148. . . Side wall

149. . . Source/bungee area

150. . . Interlayer dielectric layer

162. . . The buffer layer

164. . . Dielectric layer

172. . . Bottom barrier

174. . . First work function layer

C, D. . . region

P2. . . Processing process

Claims (19)

A fin field effect transistor (FinFET) process includes: providing a substrate; forming a first fin field effect transistor and a second fin field effect transistor on the substrate, wherein the first fin shape The field effect transistor includes a first metal layer, and the second fin field effect transistor includes a second metal layer, wherein the first metal layer and the second metal layer each comprise a barrier layer and a work function a metal layer, a low resistivity material or a combination of the three; and performing a processing process on the first metal layer to change the threshold voltage of the first fin field effect transistor. The fin field effect transistor process of claim 1, wherein the first fin field effect transistor and the second fin field effect transistor have the same conductivity type. The fin field effect transistor process of claim 2, wherein the first fin field effect transistor and the second fin field effect transistor are both N type transistors or both are P type Crystal. The fin field effect transistor process of claim 1, wherein the process comprises an etching process, a doping process, an oxidation process, a nitridation process or a fluorination process. The fin field effect transistor process described in claim 1 of the patent application, wherein the Treating the process to the first metal layer comprises changing physical properties of the first metal layer. The fin field effect transistor process of claim 5, wherein the physical property comprises a thickness, a hardness, a density or a reflectance of the first metal layer. The fin field effect transistor process of claim 1, wherein performing the process in the first metal layer comprises changing a chemical property of the first metal layer. The fin field effect transistor process of claim 7, wherein the chemical property comprises a bond, a reactivity or an etch rate of the first metal layer. The fin field effect transistor process of claim 1, wherein the first metal layer and the second metal layer each comprise a barrier layer, a work function metal layer, a low resistivity material or three a combination of people. The fin field effect transistor process of claim 1, wherein the step of forming the first fin field effect transistor and the second fin field effect transistor on the substrate comprises: forming a a first fin structure and a second fin structure on the substrate; respectively forming a dielectric layer on the first fin structure and the second fin structure; respectively forming a bottom barrier layer in each of the Forming a first work function layer on the bottom barrier layer on the first fin structure; forming a second work function layer on the bottom barrier layer on the second fin structure; Forming a top barrier layer on the first work function layer and the second work function layer respectively; and forming a low resistivity material on each of the top barrier layers, wherein the first metal layer is included in the first The bottom barrier layer on a fin structure, the first work function layer, the top barrier layer, and the low resistivity material, and the second metal layer includes the bottom resistance on the second fin structure a barrier layer, the second work function layer, the top barrier layer, and the low resistivity material. The fin field effect transistor process of claim 10, wherein the processing is performed to form the bottom barrier layer, the first work function layer, the second work function layer, and the top barrier The treatment process is performed after the layer or the low resistivity material. A field effect transistor comprising: a first fin field effect transistor having the same conductivity and a second fin field effect transistor on a substrate, wherein the first fin field effect transistor comprises a first a metal layer, the second fin field effect transistor includes a second metal layer, and the first metal layer and the second metal layer are of the same material but different thicknesses, wherein the first metal layer and the first The two metal layers each comprise a barrier layer, a work function metal layer, a low resistivity material or a combination of the three. The field effect transistor of claim 12, wherein the first metal layer and the second metal layer each comprise a stacked metal layer. The field effect transistor of claim 13, wherein at least one of each of the metal layers of the stack of the first metal layers and the metal layers of the stack of the second metal layers have different thicknesses. The field effect transistor of claim 12, wherein the first fin field effect transistor and the second fin field effect transistor have different threshold voltages. A field effect transistor comprising: a first fin field effect transistor having the same conductivity and a second fin field effect transistor on a substrate, wherein the first fin field effect transistor comprises a first a metal layer, the second fin field effect transistor includes a second metal layer, and the first metal layer and the second metal layer are different materials, wherein the first metal layer and the second metal layer are both A barrier layer, a work function metal layer, a low resistivity material, or a combination of the three is included. The field effect transistor of claim 16, wherein the first metal layer and the second metal layer each comprise a stacked metal layer. The field effect transistor of claim 17, wherein at least one of each of the metal layers of the stack of the first metal layer and the metal layer of the stack of the second metal layer has a different material. The field effect transistor according to claim 16, wherein the first fin is The field effect transistor and the second fin field effect transistor have different threshold voltages.