TWI523081B - Semiconductor process - Google Patents

Description

Semiconductor process

The present invention relates to a semiconductor process, and more particularly to a semiconductor process in which an epitaxial structure can be grown with respect to a germanium-rich layer by forming a germanium-rich layer on the sidewalls of the insulating structure.

As semiconductor processes enter the deep submicron era, such as processes below 65 nanometers (nm), the drive current of MOS transistor components has become increasingly important. In order to improve the performance of components, the so-called "strained-silicon technology" has been developed in the industry. The principle is mainly to form an epitaxial structure to strain the germanium lattice of the gate channel portion, so that the charge passes through the strain. The moving force of the gate channel is increased, thereby achieving the purpose of making the MOS transistor operate faster.

However, many problems arise in the application of strained-silicon technology. For example, in the case of a fin field effect transistor element, the structure of the fin field effect transistor includes at least one fin structure, and the insulating structure is located between the fin structures. When the strained germanium structure is used to grow the epitaxial structure on the fin structure, the epitaxial structure cannot be grown by the insulating structure, and a gap is formed between the epitaxial structure and the insulating structure. Once the epitaxial structure cannot fill the insulating structure, the volume of the epitaxial structure can be reduced, the shape of the epitaxial structure cannot be formed, and the performance of the epitaxial structure can be reduced. The structure located thereon, for example, the gate structure spanned thereon or the interlayer dielectric layer, the contact hole etch stop layer, the metal pillar, etc. formed thereon are difficult to planarly contact with the epitaxial structure, thereby reducing the fin The quality of the field effect transistor.

The present invention provides a semiconductor process by forming a layer of germanium-rich layer on the sidewall of the insulating layer so that the epitaxial structure can grow on the semiconductor substrate in accordance with the germanium-rich layer.

The present invention provides a semiconductor process comprising the steps described below. First, a semiconductor substrate is provided wherein the semiconductor substrate has a patterned insulating layer and one of the patterned insulating layers opens to expose one of the enamel regions of the semiconductor substrate. Then, a ruthenium-rich layer is formed on the sidewall of the opening. Then, an epitaxial process is performed to form an epitaxial structure on the enamel region within the opening.

Based on the above, the present invention provides a semiconductor process in which at least one layer of a germanium-rich layer is formed on a sidewall of the patterned insulating layer, so that the epitaxial structure can be grown by the germanium-rich layer when the epitaxial structure is formed on the tantalum substrate. . In this way, the epitaxial structure formed by the invention can be closely adhered to the patterned insulating layer to promote the optimal performance of the epitaxial structure.

The present invention proposes two embodiments for forming an epitaxial structure in a fin field effect transistor, but the semiconductor process of the present invention can also be applied to a bulk semiconductor substrate to form a planar transistor. It is within the scope of the invention to apply the spirit of the invention.

1-8 are schematic cross-sectional views showing a semiconductor process according to a first embodiment of the present invention. Figure 9 is a perspective view showing the semiconductor process of the first embodiment of the present invention. First, as shown in Fig. 1, a semiconductor substrate 110 is provided. The semiconductor substrate 110 is, for example, a germanium substrate, a germanium-containing substrate, a tri-five-layer overlying substrate (eg, GaN-on-silicon), a graphene-on-silicon or a silicon-on-insulator (silicon). -on-insulator, SOI) A semiconductor substrate such as a substrate. The semiconductor substrate 110 has a fin structure 112. The method of forming the fin structure 112 can be as follows, but the present invention is not limited thereto. First, a piece of substrate (not shown) is provided on which a patterned hard mask layer 120 is formed to define the location of the fin structure 112 to be formed correspondingly in the underlying bulk substrate. The patterned hard mask layer 120 can generally include an oxide layer 122 and a nitride layer 124. Next, an etching process is performed to form at least one fin structure 112 in a bulk substrate (not shown). In this way, the fabrication of the fin structure 112 is completed. In this embodiment, after the fin structure 112 is formed, the patterned hard mask layer 120 can be removed in a subsequent process, so that a three-gate tri-gate MOSFET can be formed in a subsequent process. As a result, since the fin structure 112 has three direct contact faces (including two contact sides and a contact top surface) between the subsequently formed dielectric layers, it is called a tri-gate field effect transistor (tri-gate). MOSFET). Compared with the planar field effect transistor, the three-gate field effect transistor can have a wider carrier channel width under the same gate length by using the above three direct contact surfaces as a channel through which the carrier flows. Double the drain drive current at the same drive voltage.

In addition, the present invention can also be applied to other kinds of semiconductor substrates. For example, in another embodiment, a covered insulating substrate (not shown) is provided, and the insulating substrate is etched by etching and lithography. The fabrication of the fin structure on the insulating substrate is completed by stopping the single crystal layer on the oxide layer. This is well known to the average person, and will not be repeated.

In addition, in order to clearly disclose the present invention, only one of the fin structures 112 of the present embodiment is shown, but the fin structure 112 to which the present invention can be applied may also be plural.

As shown in FIG. 2, a patterned insulating layer 130 is formed in the semiconductor substrate 110. The method of forming the patterned insulating layer 130 may include the following steps. First, after the fin structure 112 is formed on the semiconductor substrate 110, the semiconductor substrate 110 around each fin structure 112 is relatively formed with a plurality of recesses R in the semiconductor substrate 110 due to etching. Then, a liner layer (not shown) may be selectively formed on the sidewalls S1 and the bottom surface of each of the recesses R. The liner layer (not shown) may be, for example, a nitride layer or an oxide layer/nitridation layer. Layer (ON). Then, an insulating material (not shown) is filled in each of the grooves R, and then an etching or planarization process is performed. Thus, the fabrication of the patterned insulating layer 130 is completed. In this embodiment, the patterned insulating layer 130 is a shallow trench isolation structure, but in other embodiments, it may be an insulating layer formed by other methods. Additionally, the planarization process can utilize the patterned hard mask layer 120 as a stop layer. If the patterned insulating layer 130 is prepared by an etching process, the opening of the patterned insulating layer 130 may be greater than or equal to the width of the fin structure 112, and when the opening of the patterned insulating layer 130 is larger than the width of the fin structure 112, Subsequently formed epitaxial structures may be located on both contact sides of the fin structure 112.

As shown in FIG. 3, the hard mask layer 120 is removed. Thus, the patterned insulating layer 130 can form at least one opening R1 to expose one of the enamel regions A1 of the semiconductor substrate 110. In other words, the enamel region A1 is the top surface of the fin structure 112.

As shown in Figures 4-5, a germanium-rich layer 140 is formed on the sidewall S2 of the opening R1. In detail, as shown in Fig. 4, a ytterbium-rich film layer 140' is formed on the semiconductor substrate 110 and the sidewall S2 and the top surface S4 of the patterned insulating layer 130, for example, by a deposition process. Next, as shown in FIG. 5, the germanium-rich film layer 140' on the semiconductor substrate 110 and the top surface S4 of the patterned insulating layer 130 may be removed, for example, by an etching process, while exposing the top surface of the fin structure 112. Quality area A1.

It is noted that the present invention particularly forms a germanium-rich layer 140 on the sidewall S2 of the patterned insulating layer 130, so that the epitaxial structure subsequently formed on the fin structure 112 can be grown by adhering to the germanium-rich layer 140. The epitaxial structure and the patterned insulating layer 130 can be closely adhered to prevent the epitaxial structure from filling the opening R1 as in the prior art, and the gap is formed with the patterned insulating layer 130, thereby reducing the efficiency of the epitaxial structure and the fin field. The problem of deterioration of the performance of the effect transistor. Specifically, the germanium-rich layer 140 has a germanium content greater than one-third of the total content. In an embodiment, the germanium-rich layer 140 is a dielectric layer, but the invention is not limited thereto. Therefore, the germanium content of the germanium-rich layer 140 is greater than that of the patterned insulating layer 130, such as cerium oxide, so that the epitaxial structure is more likely to adhere to the germanium-rich layer 140. In the present embodiment, the germanium-rich layer 140 comprises a nitrogen-rich germanium-rich layer. In a preferred embodiment, the germanium-rich layer 140 comprises a layer of germanium nitride.

As shown in FIG. 6, an epitaxial process P is performed to form an epitaxial structure 150 on the enamel region A1 in the opening R1. The epitaxial structure P can be, for example, a germanium epitaxial structure, a germanium carbon epitaxial structure, and a germanium epitaxial structure. The invention is not limited thereto, and depends on the electrical properties and use of the transistor to be formed. set. In the present embodiment, the top surface S5 of the epitaxial structure 150 is flush with the top surface S4 of the patterned insulating layer 130. However, in other embodiments, the top surface S5 of the epitaxial structure 150 may protrude from the patterned insulating layer 130; or, the top surface S5 of the epitaxial structure 150 is located below the top surface S4 of the patterned insulating layer 130. The relative position of the top surface S5 of the epitaxial structure 150 and the top surface S4 of the patterned insulating layer 130 depends on the structure to be formed and the subsequent collocation process.

In addition, as shown in FIG. 7, another embodiment of the present invention may directly form a patterned insulating layer 130 on a semiconductor substrate 110, and then form a sidewall S2 of at least one opening R1 of the patterned insulating layer 130. A germanium-rich layer 140 is further subjected to an epitaxial process to sequentially form a fin structure 112 and an epitaxial structure on an enamel region A1 of the semiconductor substrate 110 exposed by the opening R1 in the patterned insulating layer 130. 150, or form an epitaxial structure 150 directly on the enamel region A1 as a fin structure. Similarly, the epitaxial structure 150 formed here can also be grown by attaching the germanium-rich layer 140 so that the epitaxial structure 150 and the patterned insulating layer 130 can be closely adhered to avoid gaps with the patterned insulating layer 130. . Moreover, the epitaxial structure 150 can also protrude, lower than or cut the top surface of the patterned insulating layer 130, depending on the structure to be formed and the process of subsequent collocation.

As shown in FIG. 8, the patterned insulating layer 130 is selectively etched back, and the epitaxial structure 150 extending from the fin structure 112 protrudes from the patterned insulating layer 130', and the germanium-rich layer 140 is removed. A three-gate tri-gate MOSFET is formed in the subsequent process, but the invention is not limited thereto. In another embodiment, the patterned insulating layer 130 can be fully etched back to the fin structure 112 to directly protrude from the patterned insulating layer 130'. Then, as shown in FIG. 9, a gate structure 160 is formed on the partial epitaxial structure 150 and the fin structure 112. The gate structure 160 may include a gate dielectric layer 162 and a gate electrode 164. a sidewall (not shown) or the like, and the gate dielectric layer 162 may comprise hafnium oxide or hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), tannic acid Hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), cerium oxide (yttrium oxide, Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), strontium zirconate ( hafnium zirconium oxide, HfZrO _4), tantalum oxide bismuth strontium _{(strontium bismuth tantalate, SrBi 2 Ta} 2 O 9, SBT), lead zirconate titanate _{(lead zirconate titanate, PbZr x Ti} 1-x O 3, PZT) with a titanium group strontium barium _{(barium strontium titanate, Ba x SRE} -x TiO 3, BST) composed of a high dielectric constant The dielectric layer and the gate structure 160 may comprise polysilicon or gate having a barrier layer, metal layer and the work function of the primary conductive metal such as a metal gate. Of course, the light can further form a lightly doped source/drain region, a source/drain region (not shown), form a metal halide, form a contact hole etch stop layer, form an interlayer dielectric layer, form a metal pillar, etc. Contact plugs, etc., which are well known to those of ordinary skill, are not described in detail.

It is to be noted that the epitaxial structure 150 of the present embodiment completely covers the fin structure 112, so that the subsequently formed gate structure 160, source/drain regions and the like are directly formed thereon or therein. In an embodiment, the epitaxial structure 150 may also be formed only between the fin structure 112 and the gate structure 160 (as shown in FIG. 12). In another embodiment, the epitaxial structure 150 can be formed on the fin structure 112 outside of the gate structure 160. For example, the epitaxial structure 150 may be formed at a source/drain region, which may be formed before/after the source/drain region, or formed together with the source/drain regions. The position at which the epitaxial structure is placed depends on the desired semiconductor structure and the subsequent processing of the compound. However, regardless of the application, the present invention contributes to improving the growth of the epitaxial structure.

As a result, the present invention first forms a germanium-rich layer 140 on the sidewall S2 of the patterned insulating layer 130 (as shown in FIG. 5), and then forms an epitaxial structure 150 on the enamel region A1 of the opening R1. Therefore, the epitaxial structure 150 can closely adhere to the germanium-rich region A1 and grow upward. Therefore, the epitaxial structure 150 formed by the invention can achieve the shape to be formed, and the subsequent structure can be straddle or evenly contacted with the subsequent structure; further, the epitaxial structure 150 formed by the invention is attached to the rich The germanium layer 140 grows and its volume can be maximized to maximize the space to achieve the best transistor performance.

The first embodiment proposed above is an embodiment in which an epitaxial structure is formed first to form a gate structure. A second embodiment is further described below, which first forms a gate structure and then forms an epitaxial structure.

10-11 are perspective views of a semiconductor process according to a second embodiment of the present invention. First, the steps of FIGS. 1-3 are first performed to form the semiconductor substrate 110 having the fin structure 112; the patterned insulating layer 130 is formed in the semiconductor substrate 110; and the hard mask layer 120 is removed to expose the fins below Shaped structure 112. Next, as shown in FIG. 10, the patterned insulating layer 130 of the partial region A2 is etched back so that the fin structure 112 is opposite to the patterned insulating layer 130 of the protruding portion region A2 to form a gate across the fin structure 112. Extreme trench T. In other embodiments, the gate trench T may be formed in a plurality of stripes in the patterned insulating layer 130.

As shown in FIG. 11, a gate structure 160 is formed in the gate trench T and on the fin structure 112. The gate structure 160 can include a gate dielectric layer 162 and a gate electrode 164, a sidewall (not shown), and the like. The gate dielectric layer 162 may include hafnium oxide or be selected from hafnium oxide (HfO ₂ ), hafnium niobate (HfSiO ₄ ), niobium oxynitride (HfSiON), and aluminum oxide (Al ₂ O ₃ ). , La ₂ O ₃ , Ta ₂ O ₅ , Y ₂ O ₃ , ZrO ₂ , SrTiO ₃ , Zirconium oxynitride ₄ ), barium zirconate (HfZrO ₄ ), barium oxide (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium titanate (Ba a high-k dielectric layer of the group of _x SRE _-x TiO ₃ , BST), and the gate structure 160 may comprise a polysilicon gate or a barrier layer, a work function metal layer and a main conductive metal, etc. Metal gate. Then, by using the foregoing method, the germanium-rich layer 140 is formed on the sidewall S2 of the patterned insulating layer 130, and then an epitaxial structure (not shown) is formed on the fin structure 112 outside the gate structure 160. The fused layer 140 is grown to adhere to the epitaxial structure (not shown) and the patterned insulating layer 130. In another embodiment, after forming the gate structure 160, a groove is etched before the corresponding source/drain region on the fin structure 112, and the pattern is insulated by the foregoing method. A germanium-rich layer 140 is formed on the sidewall S2 of the layer 130, and then an epitaxial structure (not shown) is formed therein. In a preferred embodiment, the recess (not shown) may have a diamond-shaped cross-sectional structure, so that the epitaxial structure (not shown) formed therein has better applied pressure to the gate channel. effect. However, whether the epitaxial structure is formed on the fin structure 112 or the fin structure 112, both ends of the axial direction X of the epitaxial structure and the germanium-rich layer 140 on the sidewall S2 of the patterned insulating layer 130. Close contact. In other words, before forming an epitaxial structure (not shown), the first embodiment needs to form a germanium-rich layer 140 on the sidewall S2 of the patterned insulating layer 130, and then form an epitaxial structure on the fin structure 112. medium up. Thus, the epitaxial structure (not shown) can grow with the germanium-rich layer 140.

Of course, after forming an epitaxial structure (not shown), the ion implantation process may be further performed to form a lightly doped source/drain region, a source/drain region, and a metal germanide; a contact hole etch stop layer is formed. Forming an interlayer dielectric layer; forming a metal pillar, etc., without further elaboration.

The above is only the application of the second embodiment of the present invention, and the present invention can also be applied to various semiconductor processes, and will not be described again due to space limitations. Where the invention is applied, the method of forming at least one germanium-rich layer to cause the epitaxial structure to adhere to its growth may be within the scope of the present invention.

In summary, the present invention provides a semiconductor process in which at least one layer of germanium is formed on the sidewall of the patterned insulating layer, so that the epitaxial structure can be adhered to the germanium-rich layer when the epitaxial structure is formed on the tantalum substrate. growing up. In this way, the epitaxial structure formed by the invention can be closely adhered to the patterned insulating layer to promote the optimal performance of the epitaxial structure. For example, the epitaxial structure of the present invention can achieve the desired shape to facilitate the subsequent structure to be spanned or uniformly contacted thereon; the epitaxial structure of the present invention can reach the maximum volume as much as possible, so as to fully utilize the space to reach the maximum Good transistor performance.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

110. . . Semiconductor substrate

112. . . Fin structure

120. . . Hard mask layer

122. . . Oxide layer

124. . . Nitride layer

130, 130’. . . Patterned insulation

140. . . Rich layer

140’. . . Rich film layer

150. . . Epitaxial structure

160. . . Gate structure

162. . . Gate dielectric layer

164. . . Gate electrode

A1. . . Tannin region

A2. . . partial area

P. . . Epitaxial process

R. . . Groove

R1. . . Opening

S1, S2. . . Side wall

S4, S5. . . Top surface

T. . . Gate ditches

X. . . Axial

1-8 are schematic cross-sectional views showing a semiconductor process according to a first embodiment of the present invention.

Figure 9 is a perspective view showing the semiconductor process of the first embodiment of the present invention.

10-11 are perspective views of a semiconductor process according to a second embodiment of the present invention.

Figure 12 is a perspective view of a semiconductor process in accordance with an embodiment of the present invention.

110. . . Semiconductor substrate

112. . . Fin structure

130. . . Patterned insulation

140. . . Rich layer

150. . . Epitaxial structure

A1. . . Tannin region

P. . . Epitaxial process

R1. . . Opening

S1, S2. . . Side wall

S4, S5. . . Top surface

Claims (19)

A semiconductor process comprising: providing a semiconductor substrate having a patterned insulating layer, and opening one of the patterned insulating layers to expose a germanium region of the semiconductor substrate; forming a germanium-rich layer in the opening a sidewall; and performing an epitaxial process to form an epitaxial structure on the germanium region within the opening, wherein the epitaxial structure is formed by attaching the germanium-rich layer. The semiconductor process of claim 1, wherein the patterned insulating layer comprises a shallow trench insulating structure. The semiconductor process of claim 1, wherein the step of forming the patterned insulating layer comprises: forming a plurality of recesses in the semiconductor substrate; forming a liner layer on sidewalls of each of the recesses And filling an insulating material into each of the grooves. The semiconductor process of claim 1, wherein the step of forming the germanium-rich layer comprises: forming a germanium-rich film layer on the semiconductor substrate and sidewalls and a top surface of the patterned insulating layer; The ruthenium rich film layer is disposed on the semiconductor substrate and on the top surface of the patterned insulating layer. The semiconductor process of claim 1, wherein the cerium-rich layer has a cerium content greater than one third of the total content. The semiconductor process of claim 5, wherein the cerium-rich layer comprises a nitrogen-rich cerium-rich layer. The semiconductor process of claim 6, wherein the germanium-rich layer comprises a tetra-triazine layer. The semiconductor process of claim 1, wherein the semiconductor substrate comprises a semiconductor substrate having a fin structure. The semiconductor process of claim 8, wherein the enamel region is a top surface of the fin structure. The semiconductor process of claim 9, wherein after performing the epitaxial process, further comprising: etching back the patterned insulating layer, causing the epitaxial structure to protrude from the patterned insulating layer; and forming a gate The pole structure is on a portion of the fin structure. The semiconductor process of claim 10, wherein the epitaxial structure Formed between the fin structure and the gate structure. The semiconductor process of claim 10, wherein the epitaxial structure is formed on the fin structure outside the gate structure. The semiconductor process of claim 9, wherein the epitaxial structure completely covers the fin structure. The semiconductor process of claim 9, wherein before forming the germanium-rich layer, the method further comprises: etching back the patterned insulating layer of the partial region to make the patterned insulating region of the protruding portion of the fin structure And forming at least one gate trench in the patterned insulating layer; and forming a gate structure in the gate trench and the fin structure. The semiconductor process of claim 14, wherein the epitaxial structure is formed on the fin structure outside the gate structure. The semiconductor process of claim 1, wherein the epitaxial structure protrudes from the patterned insulating layer. The semiconductor process of claim 1, wherein a top surface of the epitaxial structure is located below a top surface of the patterned insulating layer. The semiconductor process of claim 1, wherein a top surface of the epitaxial structure is flush with a top surface of the patterned insulating layer. The semiconductor process of claim 1, wherein the epitaxial structure comprises a germanium epitaxial structure, a germanium carbon epitaxial structure, and a germanium epitaxial structure.