TWI520238B - Semiconductor package and its manufacturing method - Google Patents

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a wafer level semiconductor package and a method of fabricating the same.

With the evolution of semiconductor technology, semiconductor packages have been developed in many different package types, and in order to pursue the thinness and thinness of semiconductor packages, a chip scale package (CSP) has been developed, which is characterized by The wafer size package only has dimensions that are equal or slightly larger than the wafer size.

However, the above-mentioned CSP structure has the disadvantage that the application of the rewiring technology or the conductive traces disposed on the wafer are often limited by the size of the wafer or the size of the active surface thereof, especially when the integration of the wafer is increased and the wafer size is shrinking. In this case, the wafer does not even provide enough surface to accommodate a larger number of solder balls to electrically connect with the outside world, thus developing a fan-out package.

In the process of the conventional fan-out package, the semiconductor wafer is first adhered to a film, and then encapsulated by the encapsulant to cover the non-active surface and side of the semiconductor wafer, and then removed by heating. The film to The active surface of the semiconductor wafer is exposed, and finally a line repeating (RDL) structure is formed on the active surface of the semiconductor wafer and the encapsulant, and a cutting operation is performed.

However, in the above-mentioned package molding process, the semiconductor wafer is supported only by the adhesive film, so the film and the encapsulant are prone to serious warpage problems, especially when the thickness of the encapsulant is thin, the warpage problem is more In order to be serious, the subsequent re-wiring process requires an additional hard carrier to fix the encapsulant to the hard carrier through a glue, but when the carrier and the adhesive are subsequently removed. Will cause problems with residual glue.

In view of the above, U.S. Patent No. 8,334,174 discloses a method of forming a fan-out type package which utilizes a hard layer to increase strength to avoid warpage in subsequent processes.

The method of manufacturing the fan-out package 1 is as disclosed in Figures 1A to 1E.

As shown in FIG. 1A, the semiconductor wafer 12 having the opposite active surface 12a and the non-active surface 12b is bonded to the carrier 10 having the adhesive film 11 by the active surface 12a; as shown in FIG. 1B, The package molding process is performed, and the hard layer 14 and the cladding layer 13 are pressed together with the carrier 10 to which the semiconductor wafer 12 is bonded, so that the semiconductor wafer 12 is embedded in the cladding layer 13; and the film is heated and removed. 11 and the carrier 10, the active surface 12a of the semiconductor wafer 12 is exposed, as shown in FIG. 1C; then, as shown in FIG. 1D, the through hole 15a penetrating the cladding layer 13 and the hard layer 14 is formed; As shown in Fig. 1E, the conductive material 15 is plated in the through hole 15a, and the line redistribution structure 16 is formed by the line repeating (RDL) technique, and then the cutting operation is performed.

However, in the foregoing process, the conductive material 15 is formed by electroplating to the through hole After 15a, it often causes an overburden state, as shown in Figure 1D'. Therefore, the overburden 15' generated by the electroplating step is required to be removed by a chemical mechanical polish (CMP) and etching before the circuit re-routing process, which causes cumbersome process and increases cost.

Therefore, how to provide a package and a manufacturing method to ensure the electrical connection quality between the circuit layer and the pad, and improve the reliability of the product, and reduce the process cost, is an important issue.

In view of the above-mentioned deficiencies of the prior art, the present invention provides a method for fabricating a semiconductor package, comprising: bonding a first semiconductor wafer having a first active surface and a first non-active surface to a first active surface thereof by an adhesive layer Bonding to a carrier; forming a cladding layer covering the first semiconductor wafer on the carrier; and bonding a substrate having the first surface and the second surface to the cladding with the first surface thereof a plurality of electrical connection pads on the first surface of the substrate; removing the carrier and the adhesive layer to expose the first active surface of the first semiconductor wafer; forming a plurality of through holes in the cladding layer And exposing the electrical connection pad of the substrate; forming a first circuit layer on the cladding layer, and forming a conductive via hole electrically connected to the first circuit layer and the electrical connection pad in the through hole.

The present invention further provides a semiconductor package comprising: a cladding layer having opposite top and bottom surfaces; a plurality of conductive vias formed in the cladding layer and extending through the top surface and the bottom surface; a layer formed on a top surface of the cladding layer and a conductive via; the first semiconductor wafer is embedded in In the cladding layer, the first semiconductor wafer has a first active surface exposed to the top surface and a first non-active surface opposite the first active surface; and the substrate has a first surface opposite to the first surface The surface is bonded to the bottom surface of the cladding layer, and the first surface of the substrate has a plurality of electrical connection pads electrically connected to the conductive via.

In the method of fabricating the semiconductor package of the present invention, the step of forming the first circuit layer and the conductive via comprises: forming a barrier layer opening on the first active surface of the cladding layer and the first semiconductor wafer a resist layer, wherein the via hole is exposed to expose the via hole; the conductive via hole is formed in the via hole, and the first circuit layer is formed in the resist layer opening; and the resist layer is removed.

In the method of fabricating a semiconductor package of the present invention, before the forming of the resist layer, forming a conductive layer on the first active surface of the first semiconductor wafer and the cladding layer, and including removing the resist layer Thereafter, the conductive layer covered by the resist layer is removed.

In another embodiment of the method of fabricating a semiconductor package of the present invention, a second semiconductor wafer is disposed on a first surface of the substrate. In the above method for fabricating a semiconductor package of the present invention, the second semiconductor wafer has a second active surface and a second non-active surface, and the second active surface is bonded to the first surface.

In the method of fabricating a semiconductor package of the present invention, after forming the first circuit layer, forming a build-up structure on the cladding layer and the first circuit layer, and electrically connecting the build-up structure to the first A wiring layer and a first semiconductor wafer. In the above method for fabricating a semiconductor package of the present invention, a build-up layer is formed on the build-up structure, and the solder resist layer has a substrate for guiding The opening of the electrical component.

In the semiconductor package of the present invention, a conductive layer is provided between the first circuit layer and the cladding layer, between the conductive via and the cladding layer, and between the conductive via and the electrical connection pad.

In another embodiment of the semiconductor package of the present invention, a second semiconductor wafer disposed and electrically connected to the substrate is included. In the foregoing semiconductor package of the present invention, the second semiconductor wafer has a second active surface and a second non-active surface, and is bonded to the first surface by the second active surface, and the second semiconductor The wafer is embedded in the cladding.

In an embodiment of the semiconductor package of the present invention, a build-up structure is formed on the top surface of the cladding layer and electrically connected to the first circuit layer and the first semiconductor wafer. In the foregoing semiconductor package of the present invention, a solder resist layer is formed on the buildup structure, and the solder resist layer has an opening for implanting the conductive member.

In the semiconductor package and the method of manufacturing the same, the conductive via and the second circuit layer are respectively formed on the second surface of the substrate, and the electrical connection pad and the second circuit layer are formed by the conductive via Electrical connection.

In the foregoing semiconductor package and method of fabricating the same, the first active surface of the first semiconductor wafer has a plurality of electrode pads, and the first semiconductor wafer is electrically connected to the buildup structure by the electrode pads.

As can be seen from the above, the semiconductor package of the present invention and its manufacturing method are supported by a substrate to overcome the disadvantage that the prior art is prone to warpage. Moreover, the manufacturing method of the semiconductor package of the present invention can directly form a circuit layer and a conductive via hole by using a resist layer, so that no carrier is generated, and the semiconductor can be simplified. The process of the body package.

1‧‧‧Fan-out package

10, 20‧‧‧ Carrying parts

11‧‧‧film

12‧‧‧Semiconductor wafer

12a‧‧‧Action surface

12b‧‧‧Non-active surface

13‧‧‧Cladding

14‧‧‧hard layer

15‧‧‧Electrical materials

15’‧‧‧ Carrier

15a, 25a‧‧‧through

16‧‧‧Line redistribution structure

2, 3‧‧‧ semiconductor package

21‧‧‧Adhesive layer

22‧‧‧First semiconductor wafer

22’‧‧‧Second semiconductor wafer

22a‧‧‧First action surface

22a’‧‧‧second action surface

22b‧‧‧First non-active surface

22b’‧‧‧Second non-active surface

220‧‧‧electrode pad

23‧‧‧Cladding

23a‧‧‧Top

23b‧‧‧ bottom

231‧‧‧First line layer

24‧‧‧Substrate

24a‧‧‧ first surface

24b‧‧‧second surface

240‧‧‧Electrical connection pads

241‧‧‧Electrical through holes

242‧‧‧Second circuit layer

25‧‧‧ Conductive through hole

250‧‧‧ Conductive layer

26‧‧‧Resist layer

260‧‧‧ openings

27‧‧‧Additional structure

270‧‧‧ openings

271‧‧‧Replacement layer

28‧‧‧Conductive components

1A to 1E are schematic cross-sectional views showing a method of fabricating a fan-out type package disclosed in U.S. Patent No. 8,334,174, wherein the 1D' figure is a schematic cross-sectional view showing a transition state in the process of achieving FIG. 1E; 2I is a schematic diagram of a method of fabricating a semiconductor package of the present invention; and FIG. 3 is a schematic cross-sectional view showing another embodiment of the semiconductor package of the present invention.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second", "top", "bottom" and "one" are used in this manual for the convenience of description, not for The scope of the invention can be implemented, and the relative changes or adjustments of the invention are considered to be within the scope of the invention.

First embodiment

2A to 2I are schematic cross-sectional views showing a method of fabricating the semiconductor package 2 of the present invention.

As shown in FIG. 2A, the first semiconductor wafer 22 having the first active surface 22a and the first non-active surface 22b is bonded to a carrier 20 by an adhesive layer 21, wherein the first semiconductor wafer 22 is The first active surface 22a is bonded to the adhesive layer 21.

In this embodiment, the first active surface 22a of the first semiconductor wafer 22 has a plurality of electrode pads 220, and the first semiconductor wafer 22 is electrically connected to the subsequently disposed build-up structure by the electrode pads 220.

As shown in FIG. 2B, a cladding layer 23 covering the first semiconductor wafer 22 is formed on the carrier 20.

In this embodiment, the material of the coating layer 23 includes, but is not limited to, an encapsulant or a soft material. In the embodiment, the soft material is ABF (Ajinomoto Build-up Film) and BT (Bismaleimide-Triacine). , Polyimide (PI), polymerized siloxanes (silicone) or epoxy resin.

As shown in FIG. 2C, a substrate 24 having a first surface 24a and a second surface 24b opposite thereto is attached to the cladding layer 23 with its first surface 24a, and the first surface 24a of the substrate 24 is disposed. There are a plurality of electrical connection pads 240.

In the embodiment, the conductive via 241 and the second wiring layer 242 are respectively formed on the substrate 24 and the second surface 24b, and the electrical connection pad 240 and the second wiring layer 242 are electrically conductive. The through holes 241 are electrically connected. In the present embodiment, the substrate is not particularly limited. In practice, there are many types of substrates, and for example, a multilayer wiring (not shown) may be provided inside, and the present invention is not limited to this embodiment.

As shown in FIG. 2D, the carrier 20 and the adhesive layer 21 are removed, and the first active surface 22a of the first semiconductor wafer 22 is exposed.

In this embodiment, the manner of removing the carrier and the adhesive layer is not particularly limited, and details are not described herein again.

As shown in FIG. 2E, a plurality of through holes 25a are formed in the cladding layer 23, and the electrical connection pads 240 of the substrate 24 are exposed.

In the present embodiment, the manner of forming the through holes 25a is not particularly limited, and is formed by a conventional method such as mechanical punching or laser drilling, and will not be described herein.

As shown in FIG. 2F, a conductive layer 250 is formed on the first active surface 22a of the first semiconductor wafer 22 and the cladding layer 23.

As shown in FIG. 2G, a resist layer 26 having a resist opening 260 is formed on the conductive layer 250, and the via hole 260 exposes the through holes 25a.

In the present embodiment, the formation manner and material of the resist layer 26 are not particularly limited, and details are not described herein again.

As shown in FIG. 2H, a first wiring layer 231 is formed on the cladding layer 23, and a conductive via 25 electrically connected to the first wiring layer 231 and the electrical connection pad 240 is formed in the through hole 25a. The resist layer 26 and the conductive layer 250 it covers are then removed.

As shown in FIG. 2I, a build-up structure 27 is formed on the cladding layer 23 and the first circuit layer 231, and the build-up structure 27 is electrically connected to the first The circuit layer 231 is connected to the first semiconductor wafer 22, and a solder resist layer 271 is formed on the build-up structure 27, and the solder resist layer 271 has an opening 270 for implanting the conductive member 28.

In this embodiment, the method for forming the build-up structure is not particularly limited, and may be set by using a conventional RDL process, which will not be described herein, and the present invention may also form the conductive via without electroplating. 25 and the first wiring layer 231, and thus it is not necessary to form the conductive layer 250.

Referring to FIG. 2I, the semiconductor package 2 of the present invention comprises: a cladding layer 23 having opposing top surfaces 23a and bottom surfaces 23b; and a plurality of conductive vias 25 formed in the cladding layer 23 and extending through The top surface 23a and the bottom surface 23b are formed on the top surface 23a of the cladding layer 23 and the conductive via 25; the first semiconductor wafer 22 is embedded in the cladding layer 23, The first semiconductor wafer 22 has a first active surface 22a having a plurality of electrode pads 220 exposed on the top surface 23a and a first non-active surface 22b opposite to the first active surface 22a; and a substrate 24 having a relative The first surface 24a and the second surface 24b are coupled to the bottom surface 23b of the cladding layer 23, and the first surface 24a of the substrate 24 has a plurality of electrical connections electrically connected to the conductive via 25 Sexual connection pad 240.

In this embodiment, the semiconductor package 2 is formed between the first circuit layer 231 and the cladding layer 23, between the conductive via 25 and the cladding layer 23, and between the conductive via 25 and the electrical connection pad. a conductive layer 250 of 240; the semiconductor package 2 includes a build-up structure 23 formed on the top surface 23a of the cladding layer 23, and electrically connected to the first circuit layer 231 and the first semiconductor wafer 22; And the semiconductor package 2 is further included in the buildup junction The solder resist layer 271 is formed on the structure 27, wherein the solder resist layer 271 has an opening 270 for implanting the conductive member 28.

FIG. 3 is a cross-sectional view showing another embodiment of the semiconductor package 3 of the present invention. The present embodiment is substantially the same as the foregoing embodiment, and the main difference is that the semiconductor package 3 in this embodiment is different. The second semiconductor wafer 22' includes a second active surface 22a' and a second non-active surface 22b', and is bonded to the first surface 24a of the substrate 24 by the second active surface 22a', and The second semiconductor wafer 22' is embedded in the cladding layer 23.

The semiconductor package 3 is formed on the first surface 24a of the substrate 24 and has a second active surface 22a' and a second non-active layer before the substrate 24 is disposed on the cladding layer 23. a second semiconductor wafer 22' of the face 22b', and the second semiconductor wafer 22' is bonded to the first surface 24a by the second active surface 22a'. The detailed manufacturing method of the semiconductor package 3 has the technical field. Generally, the knowledge person can understand according to the specification and the schema, so it will not be described again.

In summary, the semiconductor package of the present invention and the manufacturing method thereof are supported by a substrate to avoid warpage and thereby improve product yield; further, the method for fabricating the semiconductor package of the present invention can directly form a circuit layer and a conductive layer. The holes, therefore, do not produce a carrier, do not require a chemical mechanical polishing process, and can simplify the process of the semiconductor package, thereby reducing the cost.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. change. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Semiconductor package

22‧‧‧First semiconductor wafer

22a‧‧‧First action surface

22b‧‧‧First non-active surface

220‧‧‧electrode pad

23‧‧‧Cladding

23a‧‧‧Top

23b‧‧‧ bottom

231‧‧‧First line layer

24‧‧‧Substrate

24a‧‧‧ first surface

24b‧‧‧second surface

240‧‧‧Electrical connection pads

241‧‧‧Electrical through holes

242‧‧‧Second circuit layer

25‧‧‧ Conductive through hole

25a‧‧‧Tongkong

250‧‧‧ Conductive layer

27‧‧‧Additional structure

270‧‧‧ openings

271‧‧‧Replacement layer

28‧‧‧Conductive components

Claims (17)

A method of fabricating a semiconductor package, comprising: bonding, by an adhesive layer, a first semiconductor wafer having a first active surface and a first non-active surface to a carrier by a first active surface; Forming a cladding layer covering the first semiconductor wafer; and bonding a substrate having the first surface and the second surface to the cladding layer with the first surface thereof, and the first surface of the substrate a plurality of electrical connection pads; removing the carrier and the adhesive layer, exposing the first active surface of the first semiconductor wafer; forming a plurality of through holes in the cladding layer to expose the electrical connection pads of the substrate; And forming a first circuit layer on the cladding layer, and forming a conductive via hole electrically connected to the first circuit layer and the electrical connection pad in the through hole. The method of manufacturing the semiconductor package of claim 1, wherein the step of forming the first circuit layer and the conductive via comprises: the cladding layer and the first active surface of the first semiconductor wafer Forming a resist layer having a barrier opening, and exposing the via hole to the via hole; forming the conductive via hole in the via hole, and forming the first circuit layer in the barrier layer opening; Remove the barrier layer. The method for manufacturing a semiconductor package according to claim 2, further comprising forming a conductive layer on the first active surface of the first semiconductor wafer and the cladding layer before forming the resist layer, and further comprising After removing the resist layer, the conductive layer covered by the resist layer is removed. The method of manufacturing the semiconductor package of claim 1, wherein the substrate and the second surface are respectively formed with a conductive via and a second circuit layer, and the electrical connection pad and the second circuit The layer is electrically connected by the conductive via. The method of fabricating a semiconductor package according to claim 1, wherein the first surface of the substrate is provided with a second semiconductor wafer. The method of fabricating a semiconductor package according to claim 5, wherein the second semiconductor wafer has a second active surface and a second non-active surface, and the second active surface is bonded to the first On the surface. The method for manufacturing a semiconductor package according to claim 1, further comprising forming a build-up structure on the cladding layer and the first circuit layer after forming the first circuit layer, and forming the build-up structure Optionally connected to the first circuit layer and the first semiconductor wafer. The method of fabricating a semiconductor package according to claim 7, further comprising forming a solder resist layer on the build-up structure, and the solder resist layer has an opening for implanting the conductive element. The method of fabricating a semiconductor package according to claim 7, wherein the first active surface of the first semiconductor wafer has a plurality of electrode pads, and the build-up structure is electrically connected to the electrode pads. A semiconductor package comprising: a cladding layer having opposite top and bottom surfaces; a plurality of conductive vias formed in the cladding layer and extending through the top surface and the bottom surface; the first circuit layer is formed On the top surface of the cladding layer and the conductive via hole; the first semiconductor wafer is embedded in the cladding layer, and the first semiconductor wafer has a first active surface exposed on the top surface and opposite to the first a first non-active surface of the active surface; and a substrate having opposite first and second surfaces, and the first surface is bonded to the bottom surface of the cladding layer, and the first surface of the substrate has a plurality of An electrical connection pad electrically connected to the conductive via. The semiconductor package of claim 10, wherein a conductive layer is disposed between the first circuit layer and the cladding layer, between the conductive via and the cladding layer, and between the conductive via and the electrical connection pad. . The semiconductor package of claim 10, wherein the substrate and the second surface are respectively formed with a conductive via and a second circuit layer, and the electrical connection pad and the second circuit layer The conductive vias are electrically connected. The semiconductor package of claim 10, further comprising a second semiconductor wafer disposed and electrically connected to the substrate. The semiconductor package of claim 13, wherein the second semiconductor wafer has a second active surface and a second non-active surface, and the second active surface is bonded to the first surface And The second semiconductor wafer is embedded in the cladding layer. The semiconductor package of claim 10, further comprising a build-up structure formed on a top surface of the cladding layer and electrically connected to the first wiring layer and the first semiconductor wafer. The semiconductor package of claim 15, wherein the solder resist layer is formed on the buildup structure, and the solder resist layer has an opening for implanting the conductive component. The semiconductor package of claim 15, wherein the first active surface of the first semiconductor wafer has a plurality of electrode pads, and the first semiconductor wafer is electrically connected to the build-up layer by the electrode pads structure.