TWI518853B - Semiconductor package and its manufacturing method - Google Patents

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package having a dielectric layer and a method of fabricating the same.

With the evolution of semiconductor technology, semiconductor manufacturers have developed different package types, and in order to pursue the thinness and thinness of semiconductor packages, a development of a sufficient surface area to carry more input/output (I/) has been developed. O) Wafer Level Chip Scale Package (WLCSP), and a re-distribution layer (RDL) is formed on the semiconductor wafer to redistribute the pads on the semiconductor wafer to the Desire to position.

However, in the manufacturing method of such a package, in order to make the processing steps simple and good in yield, the semiconductor wafer is often fixed to the carrier by a colloid.

1A to 1D are cross-sectional views showing the fabrication of a conventional wafer level wafer size package.

As shown in FIG. 1A, a heat-expandable tape 101 is adhered to a carrier member 10, and a semiconductor wafer 11 having a plurality of electrode pads 110 is disposed at a predetermined position A on the heat-expandable tape 101.

Next, as shown in FIG. 1B, the heated pressure-sensitive adhesive film 12 is press-bonded to the heat-expandable tape 101 by a press machine, and the semiconductor wafer 11 is covered.

As shown in FIG. 1C, the carrier 10 and the thermal foaming tape 101 are removed, and the semiconductor wafer 11 and its electrode pad 110 are exposed.

As shown in FIG. 1D, a line redistribution structure 15 including a dielectric layer 151, a wiring layer 152, and a protective layer 153 is formed on the semiconductor wafer 11 and the bonding film 12, and is electrically conductive by the wiring layer 152. The blind via 150 is electrically connected to the electrode pad 110.

However, as shown in the left half of the first drawing, when the press is pressed, the heated pressure-sensitive adhesive film 12 generates fluidity, and the semiconductor wafer 11 is pushed to be largely displaced, which is beyond tolerance. The range of the conductive blind vias 150 can not be electrically connected to the electrode pads 110, resulting in abnormalities in subsequent processes and a decrease in product yield.

Therefore, how to avoid various problems in the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned deficiencies of the prior art, the present invention provides a method of fabricating a semiconductor package, comprising: providing a carrier having a release layer thereon; and attaching the opposite active and non-active surfaces to the release layer a semiconductor wafer having an active surface facing the release layer, wherein a non-active surface of the semiconductor wafer is formed with a hydrophobic layer; and a dielectric layer is formed on a surface of the separation layer where the semiconductor wafer is not provided; Covering the encapsulant on the hydrophobic layer and the dielectric layer; pressing a substrate on the encapsulant; and removing The carrier plate and the release layer expose the active surface of the semiconductor wafer.

The invention provides a method for fabricating a semiconductor package, comprising: forming a peeling layer on a carrier plate; and mounting a semiconductor wafer having an opposite active surface and an inactive surface on the peeling layer, the active surface of the semiconductor wafer facing a release layer, and a non-active surface of the semiconductor wafer is formed with a hydrophobic layer; a dielectric layer is formed on the surface of the release layer where the semiconductor wafer is not provided; and the encapsulation colloid is covered on the hydrophobic layer and the dielectric layer; Pressing a substrate on the encapsulant; and removing the carrier and the release layer to expose the active surface of the semiconductor wafer.

In a specific embodiment, after removing the carrier and the release layer, a dielectric redistribution layer electrically connected to the semiconductor wafer is formed on the dielectric layer and the active surface, and the circuit redistribution layer is formed. Afterwards, the substrate is removed, and the plurality of conductive elements are formed on the circuit redistribution layer, and after the conductive elements are formed, the substrate is removed.

In the above method for fabricating a semiconductor package, the surface of the release layer contacting the semiconductor wafer is viscous, and the method of removing the carrier and the release layer is to remove the peel by laser cauterization, chemical immersion or mechanical peeling. a layer, and the hydrophobic layer is a self-assembled monolayer.

According to the method for fabricating the semiconductor package, the material of the hydrophobic layer is OTS (octadecyltrichlorosilane), ODS (octadecyltrimethoxysilane), OTE (octadecyltriethoxysilane), DTS (decyltrichlorosilane), GPTS ((3-glycidoxypropyl) trimethoxysilane), PTS. (propyltrichlorosilane), HMDS (Hexamethyldisilazane) Or ODT (Octadecanethiol).

In the method of fabricating a semiconductor package of the present invention, the substrate is a wafer, and the material of the substrate is an inorganic material or an organic material.

The present invention provides a semiconductor package comprising: a dielectric layer; an encapsulant formed on the dielectric layer; and a semiconductor wafer embedded in the dielectric layer and the encapsulant, and the semiconductor wafer has a relative The active surface and the non-active surface are exposed to the dielectric layer, and the non-active surface is formed with a hydrophobic layer.

In the semiconductor package, the substrate is further disposed on the encapsulant such that the encapsulant is located between the dielectric layer and the substrate.

In the foregoing semiconductor package, a circuit redistribution layer is formed on the dielectric layer and the active surface, and is electrically connected to the semiconductor wafer, and further includes a plurality of conductive elements formed on the circuit redistribution layer. on.

The hydrophobic layer of the semiconductor package of this embodiment belongs to a self assembled monolayer (SAM).

In the semiconductor package, the material of the hydrophobic layer is OTS (octadecyltrichlorosilane), ODS (octadecyltrimethoxysilane), OTE (octadecyltriethoxysilane), DTS (decyltrichlorosilane), GPTS ((3-glycidoxypropyl) trimethoxysilane), PTS (propyltrichlorosilane). HMDS (Hexamethyldisilazane) or ODT (Octadecanethiol), and the substrate is a wafer, and the material of the substrate is inorganic material or organic material.

It can be seen from the above that because the present invention fixes the semiconductor wafer with a dielectric layer The position of the semiconductor wafer can be prevented from shifting during the lamination process, thereby improving the yield of the semiconductor package.

10‧‧‧ Carrier

101‧‧‧Hot foam tape

A‧‧‧predetermined location

11, 20'‧‧‧ semiconductor wafer

110, 201‧‧‧electrode pads

12‧‧‧Press film

15‧‧‧Line redistribution structure

151‧‧‧ dielectric layer

152‧‧‧Line layer

153‧‧‧Protective layer

150‧‧‧conductive blind holes

20‧‧‧Semiconductor wafer

20a‧‧‧Action surface

20b‧‧‧Non-active surface

21‧‧‧hydrophobic layer

30‧‧‧Loading board

31‧‧‧ peeling layer

32‧‧‧Dielectric layer

33‧‧‧Package colloid

34‧‧‧Substrate

35‧‧‧Line redistribution

36‧‧‧Conducting components

1A to 1D are cross-sectional views showing a method of fabricating a conventional wafer level wafer size package; and FIGS. 2A to 2J are cross-sectional views showing a method of fabricating the semiconductor package of the present invention, wherein the 2I' and The 2J' diagram is another embodiment of the 2I and 2J diagrams.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.

2A to 2J are cross-sectional views showing a method of fabricating the semiconductor package of the present invention, wherein the 2I' and 2J' patterns are another of the 2I and 2J patterns. Implementation.

As shown in FIG. 2A, a semiconductor wafer 20 having opposing surface 20a and non-active surface 20b is provided, and a plurality of electrode pads 201 are formed on the active surface 20a.

As shown in FIG. 2B, a hydrophobic layer 21 is formed on the non-active surface 20b of the semiconductor wafer 20. The hydrophobic layer 21 may belong to a self assembled monolayer (SAM), and the thickness of the hydrophobic layer 21 is relatively thin. Preferably, it is 1.5 nm, but not limited thereto, the material of the hydrophobic layer 21 may be OTS (octadecyltrichlorosilane), ODS (octadecyltrimethoxysilane), OTE (octadecyltriethoxysilane), DTS (decyltrichlorosilane), GPTS ((3-glycidoxypropyl) trimethoxysilane ), PTS (propyltrichlorosilane), HMDS (Hexamethyldisilazane) or ODT (Octadecanethiol).

As shown in Fig. 2C, a singulation step is performed to constitute a plurality of semiconductor wafers 20'.

As shown in FIG. 2D, a release layer 31 is formed on a carrier sheet 30; or a carrier sheet 30 having a release layer 31 thereon is provided.

As shown in FIG. 2E, a plurality of semiconductor wafers 20' are attached to the peeling layer 31. The working surface 20a of the semiconductor wafer 20' faces the peeling layer 31, and the peeling layer 31 contacts the semiconductor wafer 20'. The surface is sticky.

As shown in FIG. 2F, a dielectric layer 32 is formed on the surface of the peeling layer 31 where the semiconductor wafer 20' is not provided, and the dielectric layer 32 may be a resist layer due to The hydrophobic layer 21 is formed on the non-acting surface 20b of the semiconductor wafer 20', so that the dielectric layer 32 is less likely to adhere to the hydrophobic layer 21.

As shown in FIG. 2G, the sealing layer 33 is covered on the hydrophobic layer 21 and the dielectric layer 32, and a substrate 34 is pressed onto the encapsulant 33. The material of the substrate 34 is made of inorganic material or organic material.

The substrate 34 can be a semiconductor wafer, and the material of the semiconductor wafer is formed, for example, germanium (Si), ceramic, tantalum carbide (SiC), germanium dioxide (SiO ₂ ), gallium arsenide (GaAs), phosphorus. Gallium arsenide phosphide (GaAsP), indium phosphide (InP), gallium aluminum arsenide (GaAlAs) or indium gallium phosphide (InGaP).

As shown in FIG. 2H, the peeling layer 31 is removed by, for example, laser cauterization, chemical immersion or mechanical peeling, thereby removing the carrier sheet 30 and the peeling layer 31, and exposing the active surface 20a of the semiconductor wafer 20'. .

As shown in FIG. 2I, a circuit redistribution layer 35 electrically connected to the semiconductor wafer 20' is formed on the dielectric layer 32 and the active surface 20a, and a plurality of conductive layers such as solder balls are formed on the circuit redistribution layer 35. Element 36.

As shown in Fig. 2J, the singulation step is performed such that only one semiconductor wafer 20' is contained in a semiconductor package, but the number of the semiconductor wafers 20' is not limited thereto.

Alternatively, as shown in Figs. 2I' and 2J', the substrate 34 is peeled off by a release layer (not shown) between the encapsulant 33 and the substrate 34.

The present invention discloses a semiconductor package comprising: a dielectric layer 32; an encapsulant 33 formed on the dielectric layer 32; and a semiconductor The wafer 20' is embedded in the dielectric layer 32 and the encapsulant 33, and has an opposite active surface 20a and an inactive surface 20b. The active surface 20a is exposed to the dielectric layer 32, and the non-active surface 20b is exposed. The upper layer is formed with a hydrophobic layer 21.

In the foregoing semiconductor package, the substrate 34 is disposed on the encapsulant 33 such that the encapsulant 33 is located between the dielectric layer 32 and the substrate 34, and further includes a circuit redistribution layer 35. The dielectric layer 32 and the active surface 20a are electrically connected to the semiconductor wafer 20', and further comprise a plurality of conductive elements 36 formed on the circuit redistribution layer 35.

The hydrophobic layer 21 of the semiconductor package of the present embodiment belongs to a self assembled monolayer (SAM), and the thickness of the hydrophobic layer 21 is 1.5 nm.

In the semiconductor package, the material of the hydrophobic layer 21 is OTS (octadecyltrichlorosilane), ODS (octadecyltrimethoxysilane), OTE (octadecyltriethoxysilane), DTS (decyltrichlorosilane), GPTS ((3-glycidoxypropyl) trimethoxysilane), PTS (propyltrichlorosilane). HMDS (Hexamethyldisilazane) or ODT (Octadecanethiol), and the substrate 34 is a wafer, and the material of the wafer is made of an inorganic material or an organic material, such as ceramics, tantalum carbide (SiC), cerium oxide. (SiO ₂ ) or semiconductor (such as germanium (Si), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), indium phosphide (InP), aluminum gallium arsenide ( Gallium aluminum arsenide, GaAlAs) or indium gallium phosphide (InGaP), etc., such as plastic, glass fiber reinforced resin (for example, BT (bismaleimide-triazine)), glass fiber reinforced epoxy resin (fiberglass) Reinforced epoxy resin (for example, FR-4) or epoxy (epoxy).

In summary, compared with the prior art, since the present invention forms a hydrophobic layer on the inactive surface of the semiconductor wafer, a subsequent dielectric layer is formed on the periphery of the semiconductor wafer to fix the position of the semiconductor wafer, thereby avoiding The semiconductor wafer is offset during the lamination process, thereby improving the yield of the semiconductor package and reducing the process cost.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

20’‧‧‧Semiconductor wafer

201‧‧‧electrode pads

20a‧‧‧Action surface

20b‧‧‧Non-active surface

21‧‧‧hydrophobic layer

32‧‧‧Dielectric layer

33‧‧‧Package colloid

34‧‧‧Substrate

35‧‧‧Line redistribution

36‧‧‧Conducting components

Claims (20)

A semiconductor package includes: a dielectric layer; an encapsulant formed on the dielectric layer; and a semiconductor wafer embedded in the dielectric layer and the encapsulant, and the semiconductor wafer has a relative active surface The active surface is exposed to the dielectric layer, and the non-active surface is directly contacted with a hydrophobic layer. The semiconductor package of claim 1, further comprising a substrate disposed on the encapsulant such that the encapsulant is located between the dielectric layer and the substrate. The semiconductor package of claim 1, further comprising a circuit redistribution layer formed on the dielectric layer and the active surface, and electrically connected to the semiconductor wafer. The semiconductor package of claim 3, comprising a plurality of conductive elements formed on the circuit redistribution layer. The semiconductor package of claim 1, wherein the hydrophobic layer is a self-assembled monolayer. The semiconductor package according to claim 1, wherein the material for forming the hydrophobic layer is OTS (octadecyltrichlorosilane), ODS (octadecyltrimethoxysilane), OTE (octadecyltriethoxysilane), DTS (decyltrichlorosilane), GPTS ((3-glycidoxypropyl) ) Trimethoxysilane), PTS (propyltrichlorosilane), HMDS (Hexamethyldisilazane) or ODT (Octadecanethiol). The semiconductor package of claim 2, wherein the substrate is a wafer. The semiconductor package according to claim 2, wherein the material of the substrate is an inorganic material or an organic material. A method of fabricating a semiconductor package, comprising: providing a carrier having a release layer thereon; and disposing a semiconductor wafer having opposite active and non-active surfaces on the release layer, the active surface of the semiconductor wafer facing a layer is disposed, and a non-active surface of the semiconductor wafer is directly contacted with a hydrophobic layer; a dielectric layer is formed on a surface of the stripping layer where the semiconductor wafer is not disposed; and the encapsulating layer is covered on the hydrophobic layer and the dielectric layer Pressing a substrate on the encapsulant; and removing the carrier and the release layer to expose the active surface of the semiconductor wafer. A semiconductor package is formed by: forming a peeling layer on a carrier plate; and mounting a semiconductor wafer having opposite working and non-active surfaces on the peeling layer, the working surface of the semiconductor wafer facing the peeling layer And the non-active surface of the semiconductor wafer is directly contacted with a hydrophobic layer; Forming a dielectric layer on the surface of the peeling layer on which the semiconductor wafer is not disposed; covering the sealing layer on the hydrophobic layer and the dielectric layer; pressing a substrate on the encapsulant; and removing the carrier and the peeling layer Exposed to the active surface of the semiconductor wafer. The method for manufacturing a semiconductor package according to claim 9 or 10, after removing the carrier and the release layer, further comprising forming a line connecting the dielectric layer and the active surface to electrically connect the semiconductor wafer Cloth layer. The method of fabricating a semiconductor package according to claim 11 is further comprising forming a plurality of conductive elements on the circuit redistribution layer. The method for manufacturing a semiconductor package according to claim 11 is characterized in that after the circuit redistribution layer is formed, the substrate is removed. The method for fabricating a semiconductor package according to claim 12, after the forming of the conductive elements, comprises removing the substrate. The method of fabricating a semiconductor package according to claim 9 or claim 10, wherein the surface of the release layer contacting the semiconductor wafer is viscous. The method of fabricating a semiconductor package according to claim 9 or claim 10, wherein the carrier layer and the release layer are removed by laser cauterization, chemical immersion or mechanical peeling to remove the release layer. The method of fabricating a semiconductor package according to claim 9 or claim 10, wherein the hydrophobic layer is a self-assembled monolayer. The method for manufacturing a semiconductor package according to claim 9 or 10, wherein the material for forming the hydrophobic layer is OTS (octadecyltrichlorosilane), ODS (octadecyltrimethoxysilane), OTE (0ctadecyltriethoxysilane), DTS (decyltrichlorosilane), GPTS ( (3-glycidoxypropyl)trimethoxysilane), PTS (propyltrichlorosilane), HMDS (Hexamethyldisilazane) or ODT (Octadecanethiol). The method of fabricating a semiconductor package according to claim 9 or claim 10, wherein the substrate is a wafer. The method of manufacturing a semiconductor package according to claim 9 or 10, wherein the material of the substrate is an inorganic material or an organic material.