TWI515745B - Three-dimensional memory device - Google Patents

Description

Three-dimensional memory device 【0001】

 The present invention relates to a memory device, and more particularly to a three-dimensional memory device in which a plurality of memory cells are disposed.

【0002】

 With the advancement of integrated circuit manufacturing technology, a three-dimensional memory device in which a plurality of planar memory cells are stacked has been developed, thereby obtaining a larger storage capacity.

[0003]

 In a three-dimensional memory array, the bit lines are arranged to access different layers in the memory array, so the configuration of the bit lines significantly affects the speed of reading and/or staging the memory. Therefore, how to provide a memory device that can improve the memory reading and/or programming bandwidth is one of the current topics in the industry.

[0004]

 The present invention relates to a three-dimensional memory device in which the conductive structure of the three-dimensional memory device improves the reading and programming bandwidth of the memory.

[0005]

 According to an embodiment, a three-dimensional integrated circuit is provided, including a memory element region, a first stepped structure, a second stepped structure, a first conductive strip, and a second conductive strip. The memory element region includes a first stacked structure and a second stacked structure. The first stacked structure includes a first semiconductor strip and the second stacked structure includes a second semiconductor strip. The first step structure is located on one side of the memory element region, and one end of the first semiconductor strip is connected to the first step structure. The second stepped structure is located on the opposite side of the memory element region, and one end of the second semiconductor strip is connected to the second stepped structure. The first conductive strip is coupled to the first semiconductor strip through the first step structure. The second conductive strip is coupled to the second semiconductor strip through the second step structure.

[0006]

 In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

[0027]

100,800‧‧‧3D memory device
102, 802 (1), 802 (2) ‧ ‧ memory element area
104A, 104B, 804A, 804B, 804C‧‧‧ ladder structure
106(1)-106(8), 806(1)-806(8)‧‧‧ Conductive strip
108(1)-108(8)‧‧‧Stack structure
114‧‧‧conductive plug
112(1)-112(n), 116(1)-116(8), 118(1)-118(8), 120 _{_odd} , 120 _{_even} ‧‧‧ conductive structure
702‧‧‧Sense Amplifier
A1-A4, B1-B4‧‧‧ semiconductor strip
ML1‧‧‧ first metal layer
ML2‧‧‧ second metal layer
ML3‧‧‧ third metal layer
SV‧‧‧ sensing signal
GV‧‧‧Shielding signal
MS‧‧‧ memory cell string
P1‧‧‧Precharge stage
P2‧‧‧Setting and sensing phase
P3‧‧‧Reduction phase
GSL‧‧‧Ground selection line signal
CSL‧‧‧ source line signal
SSL _{_sel ‧‧‧Selected} series connection line signal
SSL _{_unsel ‧‧‧Unselected} series connection line signal
Channel‧‧‧Memory cell channel voltage
ML3 BL‧‧‧ bit line signal of the third metal layer
WL _{_unsel ‧‧‧Unselected} character line signal
WL _{_sel ‧‧‧Selected} character line signal
BLCLAMP‧‧‧ bit line clamp signal
CSL, SSL, BLSEL, BLC, BLK, BLC_I, LPC, BRST, BRSTN, STBN, CNB‧‧‧ signals

【0007】

FIG. 1 is a schematic diagram of a three-dimensional memory device according to an embodiment.
Figure 2 shows a top view of the three-dimensional memory device.
FIG. 3 is a schematic diagram showing an example of a reading operation of the three-dimensional memory device.
Figure 4 is a diagram showing the waveform of the signal read from the three-dimensional memory device.
FIG. 5 is a schematic diagram showing another example of the reading operation of the three-dimensional memory device.
Figure 6 shows a sense amplifier for reading a three-dimensional memory device.
Figure 7 is a diagram showing the waveform of the relevant signal of the sense amplifier reading the three-dimensional memory device.
FIG. 8 is a top view of a three-dimensional memory device in accordance with an embodiment of the present invention.

[0008]

 The following is a detailed description of the embodiments, which are intended to be illustrative only and not to limit the scope of the disclosure. In addition, the drawings in the embodiments omit unnecessary elements to clearly show the technical features of the disclosure.

【0009】

 Please refer to both Figure 1 and Figure 2. FIG. 1 is a schematic diagram of a three-dimensional memory device 100 in accordance with an embodiment. FIG. 2 is a top view of the three-dimensional memory device 100. The three-dimensional memory device 100 includes a memory element region 102, stepped structures 104A, 104B, and a plurality of conductive strips 106(1)-106(8). A plurality of memory cells are defined in the memory element region 102, and each of the conductive strips 106(1)-106(8) is, for example, a bit line (BL) as a memory cell string, respectively.

[0010]

 The memory element region 102 includes a plurality of rows of stacked structures 108(1)-108(8) extending in the X direction. The odd-numbered stacked structures 108(1), 108(3), 108(5), 108(7) are interleaved with the even-numbered stacked structures 108(2), 108(4), 108(6), 108(8) arrangement. The stacked structure 108(1) is parallel and adjacent to the stacked structure 108(2); the stacked structure 108(3) is parallel and adjacent to the stacked structure 108(4); the stacked structure 108(5) is parallel to the stacked structure 108(6) And adjacent; the stacked structure 108(7) is parallel and adjacent to the stacked structure 108(8). The stacked structures 108(1)-108(8) each include a plurality of mutually separated semiconductor stripes (e.g., semiconductor strips A1-A4 in stacked structure 108(1), semiconductor strips B1-B4 in stacked structure 108(2)). As shown in FIG. 1, the semiconductor strips A1-A4 are located in different layers and separated by dielectric strips, and the semiconductor strips B1-B4 are located in different layers and separated by dielectric strips. In order to clearly show the structure of the memory device of the embodiment, Fig. 1 does not show a portion of the dielectric strip.

[0011]

 The conductive structures 112(1)-112(n) are disposed on the sidewalls of the stacked structures 108(1)-108(8) and are disposed apart from each other along the Z direction, for example, as a word line of the three-dimensional memory device 100 (word Line, WL), where n is a positive integer greater than one.

[0012]

 The stepped structure 104A is located on one side of the memory element region 102, and one end of the semiconductor strip of the odd-numbered stacked structures 108(1), 108(3), 108(5), 108(7) is connected to the stepped structure 104A. The stepped structure 104B is located on the opposite side of the memory element region 102, and one end of the semiconductor strip of the even-numbered stacked structures 108(2), 108(4), 108(6), 108(8) is connected to the stepped structure 104B.

[0013]

 Conductive strips 106(1), 106(3), 106(5), 106(7) are staggered with conductive strips 106(2), 106(4), 106(6), 106(8). The conductive strips 106(1), 106(3), 106(5), 106(7) are coupled to the odd-numbered stacked structures 108(1), 108(3), 108(5), 108 through the stepped structure 104A ( 7) The semiconductor strip. In the example of FIG. 1, the conductive strips 106(1), 106(3), 106(5), 106(7) are located in the third metal layer ML3 above the stacked structures 108(1)-108(8), And respectively connected to different layers of the step structure 104A through a conductive plug 114 to electrically connect to different layers of the semiconductors in the stacked structures 108 (1), 108 (3), 108 (5), 108 (7) article. Similarly, the conductive strips 106(2), 106(4), 106(6), 106(8) are located in the third metal layer ML3, and are coupled to the stacked structures 108(2), 108, respectively, through the stepped structure 104B ( 4), different layers of semiconductor strips in 108 (6), 108 (8).

[0014]

 In the example of Figure 1, the conductive strips 106(1)-106(8) are parallel to the semiconductor strips of each of the stacks 108(1)-108(8). Conductive strips 106(1), 106(3), 106(5), 106(7) span over memory element region 102 and stepped structure 104B and are electrically isolated from step structure 104B. Conductive strips 106(2), 106(4), 106(6), 106(8) straddle memory element region 102 and stepped structure 104A and are electrically isolated from step structure 104A. Two adjacent semiconductor strips in the same layer (such as the semiconductor strip A1 of the stacked structure 108(1) of the same layer and the semiconductor strip B1 of the stacked structure 108(2)) and two adjacent conductive strips ( For example, the distance between the conductive strips 106(1) and 106(2)) is equal. Compared with the conventional three-dimensional memory structure, the three-dimensional memory device of the embodiment of the present invention can provide a large read and program bandwidth.

[0015]

 In the example of FIG. 1, conductive structures 116(1), 116(3), 116(5), 116(7) are respectively disposed in odd-row stack structures 108(1), 108(3), 108(5) The sidewalls of the semiconductor strips of 108(7) are adjacent to the stepped structure 104A for use as a series selection line for the odd rows of stacked structures 108(1), 108(3), 108(5), 108(7). Similarly, conductive structures 116(2), 116(4), 116(6), 116(8) are disposed in even rows of stacked structures 108(2), 108(4), 108(6), 108(8), respectively. The sidewalls of the semiconductor strips are adjacent to the stepped structure 104B for use as a series selection line for the even rows of stacked structures 108(2), 108(4), 108(6), 108(8). In other words, in the example of Fig. 1, the series connection of the odd page and the even page is set in the opposite direction.

[0016]

 The conductive structures 116(1)-116(8) are electrically connected to the series connection lines formed by the first metal layer ML1 and the second metal layer ML2, by supplying a voltage to the first metal layer ML1 and the second metal layer ML2 The formed tandem selection line can control the semiconductor strip of the corresponding stacked structure to be a selected state or an unselected state.

[0017]

 The conductive structures 118(1), 118(3), 118(5), 118(7) are disposed on the semiconductor strips of the odd-row stack structures 108(1), 108(3), 108(5), 108(7) The sidewalls are located adjacent to the stepped structure 104B for use as the source lines of the stacked structures 108(1), 108(3), 108(5), 108(7). One end of the semiconductor strip of stacked structures 108(1), 108(3), 108(5), 108(7) terminates in conductive structures 118(1), 118(3), 118(5), 118(7) . Similarly, conductive structures 118(2), 118(4), 118(6), 118(8) are disposed in even row stack structures 108(2), 108(4), 108(6), 108(8) The sidewalls of the semiconductor strip are located adjacent to the stepped structure 104A for use as the source lines of the stacked structures 108(2), 108(4), 108(6), 108(8). One end of the semiconductor strip of stacked structures 108(2), 108(4), 108(6), 108(8) terminates in conductive structures 118(2), 118(4), 118(6), 118(8) .

[0018]

The conductive structure _{120_odd is} disposed on the sidewalls of the semiconductor strips of the odd-row stack structures 108(1), 108(3), 108(5), 108(7) for use as the stacked structures 108(1), 108(3) , 108 (5), 108 (7) ground selection line. Similarly, the conductive structures _{120_even are} disposed on the sidewalls of the semiconductor strips of the even-row stack structures 108(2), 108(4), 108(6), 108(8) for use as the stacked structures 108(2), 108 (4), 108 (6), 108 (8) ground selection line. In one embodiment, the conductive structure as the ground select line is between the conductive structure as the series select line and the conductive structure as the source line, and adjacent to the conductive structure as the source line.

[0019]

 It can be understood that the number of rows of the stacked structure, the number of layers of the semiconductor strip, the number of columns of the word lines, the number of the conductive strips, and the like in the above embodiment are not limited to the number shown in FIG. 1 and can be designed according to actual conditions. Become more or less. Further, the conductive material in the above embodiments may include a metal, a polysilicon, a metal halide, or other suitable material. The dielectric material can include an oxide or a halide such as hafnium oxide, tantalum nitride, or hafnium oxynitride, or other suitable materials.

[0020]

 Referring to FIG. 3, an example of a reading operation of the three-dimensional memory device 100 is illustrated. In the example of Figure 3, an odd page can be selected first. The K layer in the memory device 100 is sensed by applying the sensing signal SV to the conductive strips 106(1), 106(3), 106(5), 106(7) as bit lines (in this example, K=4) The memory cells are shielded by applying a masking signal GV (such as a ground voltage) to the conductive strips 106(2), 106(4), 106(6), 106(8). Next, open the selected even pages. In the present embodiment, the sensing operation can be performed in a word line setting waveform, and thus essentially reads two pages in one waveform, thereby doubling the memory reading speed.

[0021]

FIG. 4 is a diagram showing an example of a signal waveform of the three-dimensional memory device 100. In the precharge phase P1, the ground select line signal (GSL) is set to a high voltage, the source line signal (CSL) is set to the ground voltage, and the select line signal (SSL _{_sel} ) and the unselected series select line are serially connected. The signal (SSL _{_unsel} ) is set to a high voltage to set the memory cell channel (Channel) to the ground level. In the setting and sensing phase P2, the selected string selection line ( _{SSL_sel} ) is applied with a pass voltage (about 6 volts); the unselected string selection line signal ( _{SSL_unsel} ) is set to a low voltage (about - 2 volts; the bit line signal (ML3 BL) of the third metal layer is set to the sense voltage (about 1 volt); the unselected word line signal (WL _{_unsel} ) is set to the pass voltage (about 6 volts) The selected word line signal (WL _{_sel} ) is set to a low voltage (approximately less than 0 volts). By applying a bit line clamp signal (BLCLAMP), the data stored in the memory cell can be sensed through the sensing circuit. The bit line and the sensing phase are set, for example, to repeat the reading of two pages. In the reduction phase P3, the memory cell channel is discharged for recovery to the ground voltage. It is to be understood that the waveform diagrams of FIG. 4 are for illustrative purposes only and are not intended to limit the invention.

[0022]

 Please refer to FIG. 5 , which illustrates another example of a read operation of the three-dimensional memory device 100 . In the example of Fig. 5, two pages can be simultaneously selected for reading, wherein one page is an odd page and the other page is an even page. To double the memory read speed, the bit line and ground select lines are set and all of the serial select lines are turned off.

[0023]

 Please refer to Figure 6 and Figure 7. FIG. 6 illustrates an example of a sense amplifier 702 for reading the three-dimensional memory device 100. FIG. 7 illustrates an example of a waveform of a related signal waveform of the three-dimensional memory device 100 by the sense amplifier 702. As shown in FIG. 7, the related signals of the three-dimensional memory device 100 include signals CSL, SSL, BLSEL, BLC, BLK, BLC_I, LPC, BRST, BRSTN, STBN, and CNB. The sense amplifier 702 performs the conventional memory sensing operation by the above signals, so the operation details of the sense amplifier 702 will not be described herein. For one of the memory strings MS of the three-dimensional memory device 100, the sense amplifier 702 performs current sensing to read the data stored by the particular memory cell.

[0024]

 FIG. 8 is a top view of a three-dimensional memory device 800 in accordance with an embodiment of the present invention. The three-dimensional memory device 800 includes a plurality of memory element regions. As shown in FIG. 8, the three-dimensional memory device 800 includes a plurality of memory element regions 802(1) and 802(2). Memory element regions 802(1), 802(2) are interleaved with a plurality of ladder structures 804A, 804B, 804C. The arrangement of the stack structures in the memory element regions 802(1) and 802(2) is the same as that of the previous embodiment, and therefore will not be described again. Conductive strips 806(1)-806(8) are parallel to the stacked structures in memory element regions 802A and 802B. The conductive strips 806(1), 806(3), 806(5), 806(7) and the stepped structures 804A and 804C are electrically connected through the conductive plug and electrically isolated from the stepped structure 804B (not connected to the stepped structure 804B) . The conductive strips 806(2), 806(4), 806(6), 806(8) and the stepped structure 804B are electrically connected through the conductive plugs and electrically isolated from the stepped structures 804A, 804C (without the stepped structures 804A, 804C) connection). In other words, the conductive strips 806(1), 806(3), 806(5), 806(7) are electrically connected to the stepped structure of the odd columns. The conductive strips 806(2), 806(4), 806(6), 806(8) are electrically connected to the even-numbered column structure. In this embodiment, the position of each of the stepped structures 804A-804C can be translated in the X direction. For example, a shift-scamble design can be used to average the bit line sense capacitance.

[0025]

 According to the above, the three-dimensional memory device of the embodiment of the present invention provides a bit line design with dense spacing. Since the number of bit lines is increased, the three-dimensional memory device of the embodiment of the present invention can provide improved reading and programming bandwidth compared to conventional three-dimensional memory structures.

[0026]

 In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Three-dimensional memory device

102‧‧‧Memory Element Area

104A, 104B‧‧‧ ladder structure

106(1)-106(8)‧‧‧ Conductive strip

114‧‧‧conductive plug

112(1)-112(n), 116(1), 118(1), 120 _{_odd ‧‧‧Electrical} structure

A1-A4, B1-B4‧‧‧ semiconductor strip

ML1‧‧‧ first metal layer

ML2‧‧‧ second metal layer

ML3‧‧‧ third metal layer

Claims (10)

[Item 1] A three-dimensional memory device comprising:
A memory component area, including:
a first stacked structure including a first semiconductor strip; and a second stacked structure including a second semiconductor strip, the second stacked structure being parallel and adjacent to the first stacked structure;
a first step structure, located on one side of the memory element region, one end of the first semiconductor strip is connected to the first step structure;
a second step structure, located on the opposite side of the memory element region, one end of the second semiconductor strip is connected to the second step structure;
a first conductive strip coupled to the first semiconductor strip through the first step structure; and a second conductive strip coupled to the second semiconductor strip through the second stepped structure. [Item 2] The three-dimensional memory device of claim 1, wherein the memory element region further comprises:
a plurality of the first stacked structures, including a plurality of the first semiconductor strips separated from each other; and a plurality of the second stacked structures, including a plurality of the second semiconductor strips separated from each other, the first stacked structures and the plurality of The second stack structure is staggered. [Item 3] A three-dimensional memory device as claimed in claim 2, which comprises:
a plurality of the first conductive strips respectively connected to the first semiconductor strips of different layers through the first stepped structure; and a plurality of the second conductive strips respectively connected to the different layers through the second stepped structure The second semiconductor strips are staggered with the second conductive strips. [Item 4]  The three-dimensional memory device of claim 1, wherein the first conductive strip spans the memory element region and the second step structure, and is electrically isolated from the second step structure; the second conductive A strip spans the memory element region and above the first step structure and is electrically isolated from the first step structure. [Item 5]  The three-dimensional memory device of claim 1, wherein a distance between the first semiconductor strip and the second semiconductor strip is equal to a distance between the first conductive strip and the second conductive strip. [Item 6] A three-dimensional memory device comprising:
a plurality of memory element regions, wherein the first memory element region of one of the memory device regions comprises:
a first stacked structure including a first semiconductor strip; and a second stacked structure including a second semiconductor strip, the second stacked structure being parallel and adjacent to the first stacked structure;
a plurality of step structures, wherein the step structures are staggered with the memory element regions;
a first conductive strip is coupled to the first semiconductor strip through a first stepped structure of the stepped structures, wherein the first conductive strip is electrically connected to the stepped structures of the odd columns; and a second conductive strip The second semiconductor strip is coupled to the second semiconductor strip through one of the stepped structures, wherein the second conductive strip is electrically connected to the even-numbered columns of the stepped structures. [Item 7] The three-dimensional memory device of claim 6, wherein the first memory element region further comprises:
a plurality of the first stacked structures, including a plurality of the first semiconductor strips separated from each other; and a plurality of the second stacked structures, including a plurality of the second semiconductor strips separated from each other, the first stacked structures and the plurality of The second stack structure is staggered. [Item 8] The three-dimensional memory device of claim 7, wherein:
a plurality of the first conductive strips respectively connected to the first semiconductor strips of different layers through the first stepped structure; and a plurality of the second conductive strips respectively connected to the different layers through the second stepped structure The second semiconductor strips are staggered with the second conductive strips. [Item 9]  The three-dimensional memory device of claim 6, wherein the first conductive strip is electrically isolated from the even-numbered columns; the second conductive strip is electrically isolated from the plurality of stepped structures. [Item 10] The three-dimensional memory device of claim 6, wherein a distance between the first semiconductor strip and the second semiconductor strip is equal to a distance between the first conductive strip and the second conductive strip.