TWI506735B - Method of manufacturing non-volatile memory - Google Patents

Description

Non-volatile memory manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a non-volatile memory.

As the semiconductor enters the Deep Sub-Micron process, the size of the component is gradually reduced, and for the memory component, it means that the memory cell size is getting smaller and smaller. On the other hand, as information electronics (such as computers, mobile phones, digital cameras, or personal digital assistants (PDAs)) need to process and store more and more data, the memory required in these information electronics The capacity is getting bigger and bigger. In the case where the size is small and the memory capacity needs to be increased, how to manufacture a memory element having a reduced size, a high degree of integration, and a quality can be a consistent goal of the industry.

Non-volatile memory has become a memory component widely used in personal computers and electronic devices because it has the advantage that the stored data does not disappear after power-off.

A typical non-volatile memory cell system uses a doped polysilicon to form a floating gate and a control gate to form a stacked structure. A dielectric layer is disposed between the floating gate and the substrate, the floating gate and the control gate.

However, the above non-volatile memory cells are required to form a multilayer polycrystalline germanium layer and a multilayer dielectric layer. In the production process, it will go through multiple mask steps and lengthen Production process and costly manufacturing costs.

A conventional NOR-type non-volatile memory cell in which two transistors are connected in series includes a selective transistor and a floating gate transistor. Since the memory cell does not need to form a multi-layer polysilicon layer, the process of the non-volatile memory cell can be integrated with the process of the complementary MOS transistor.

In general, a non-volatile memory is composed of a plurality of memory cells located in a memory cell region and a plurality of logic elements (eg, input/output transistors, core transistors, etc.) located in peripheral circuit regions. The above-mentioned selective transistor and the input/output transistor of the peripheral circuit region are fabricated in the same process. The gate dielectric layer of the input/output transistor is typically thicker to withstand higher operating voltages. However, in the case where the integrated circuit is increased in size and the size of the element is reduced, the size of the memory cell is also smaller. If the thickness of the gate dielectric layer of the selected transistor is the same as the thickness of the gate dielectric layer of the input/output transistor of the peripheral circuit region. When the memory is operated, it is necessary to apply a large voltage to the gate of the selection transistor, so that the driving ability of the non-volatile memory element is lowered. Therefore, how to make non-volatile memory components have higher driving capability will become an important issue.

In view of this, the present invention provides a method of manufacturing a non-volatile memory, which can effectively improve the driving capability of a non-volatile memory element.

The present invention provides a method of producing a non-volatile memory. A substrate is provided. The substrate includes a memory cell region and a first peripheral circuit region. Memory cell package Including the selection of the transistor area. A first gate dielectric layer is formed on the first peripheral circuit region and the substrate on which the transistor region is selected. The first gate dielectric layer has a first thickness. A portion of the first gate dielectric layer on the selected transistor region is removed to form a second gate dielectric layer. The second gate dielectric layer has a second thickness, wherein the second thickness is less than the first thickness.

In an embodiment of the invention, the memory cell region includes a memory cell region. A charge storage structure is formed in the memory cell region. The charge storage structure includes a tunneling dielectric layer and a charge storage layer.

In an embodiment of the invention, the material of the charge storage layer comprises doped polysilicon.

In an embodiment of the invention, the memory cell region includes a memory cell region. A charge storage structure is formed in the memory cell region. The charge storage structure includes a bottom dielectric layer, a charge trapping layer, and a top dielectric layer.

In an embodiment of the invention, the material of the charge trapping layer is one of a group selected from the group consisting of tantalum nitride, hafnium oxynitride, aluminum oxide, cerium oxide, zirconium oxide and other materials capable of storing electric charges. .

In one embodiment of the invention, the first gate dielectric layer acts as a gate dielectric layer for an input/output (I/O) transistor.

In an embodiment of the invention, the first gate dielectric layer has a thickness of 90 Å to 130 Å, and the second gate dielectric layer has a thickness of 50 Å to 90 Å.

In one embodiment of the invention, the step of removing a portion of the first gate dielectric layer on the selected transistor region to form the second gate dielectric layer includes performing a photolithography process.

In an embodiment of the invention, the substrate further includes a second perimeter Circuit area. And forming a first gate dielectric layer on the substrate of the first peripheral circuit region and the substrate for selecting the transistor region, further comprising forming a first gate dielectric layer on the substrate of the second peripheral circuit region. The first gate dielectric layer on the second peripheral circuit region is removed. Forming a third thyristor layer on the substrate on the second peripheral circuit region, the third thyristor layer having a third thickness, wherein the third thickness is less than the second thickness.

In an embodiment of the invention, the memory cell region includes a memory cell region. A charge storage structure is formed in the memory cell region. The charge storage structure includes a tunneling dielectric layer and a charge storage layer.

In an embodiment of the invention, the material of the charge storage layer comprises doped polysilicon.

In an embodiment of the invention, the memory cell region comprises a memory unit. A charge storage structure is formed in the memory cell region. The charge storage structure includes a bottom dielectric layer, a charge trapping layer, and a top dielectric layer. Or the charge storage structure includes a bottom dielectric layer and a charge storage layer.

In an embodiment of the invention, the material of the charge trapping layer is one of a group selected from the group consisting of tantalum nitride, hafnium oxynitride, aluminum oxide, cerium oxide, zirconium oxide and other materials capable of storing electric charges. .

In an embodiment of the invention, the first gate dielectric layer is a gate dielectric layer of an input/output (I/O) transistor, and the third gate dielectric layer is a gate dielectric layer of a core transistor.

In an embodiment of the invention, the first gate dielectric layer has a thickness of 90 Å to 130 Å, the second gate dielectric layer has a thickness of 50 Å to 90 Å, and the third gate dielectric layer has a thickness of 15 Å~40 Å.

In an embodiment of the invention, the step of removing the first gate dielectric layer on the second peripheral circuit region includes performing a photolithography process. The step of forming a third gate dielectric layer on the substrate on the second peripheral circuit region includes performing a thermal oxidation process.

Based on the above, the method for manufacturing a non-volatile memory according to the present invention, the thickness of the gate dielectric layer of the selected cell of the memory cell is smaller than the gate dielectric layer of the input/output (I/O) transistor. The gate dielectric layer of the memory cell is selected at this thickness (50 Å to 90 Å), which allows the transistor to have a small driving current, which in turn has a higher driving capability and a higher guiding for the memory cell. Message rate.

In addition, the method for manufacturing a non-volatile memory according to the present invention can also produce a gate dielectric layer of a core transistor having a thickness (15 Å to 40 Å). This core transistor can withstand low operating voltages. The method for producing a non-volatile memory proposed by the present invention can produce a transistor having gate dielectric layers of various thicknesses.

The above described features and advantages of the present invention will be more apparent from the following description.

First embodiment

1A to 1E are schematic cross-sectional views showing a manufacturing process of a non-volatile memory according to a first embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is first provided. The substrate 100 is, for example, a germanium substrate having an N-type dopant or a P-type dopant. Substrate 100 includes memory cells 102. A first peripheral circuit region 104 and a second peripheral circuit region 106.

In this substrate 100, for example, a plurality of isolation structures (not shown) have been formed. The isolation structure is, for example, a shallow trench isolation (STI) structure. The isolation structure isolates the memory cell region 102, the first peripheral circuit region 104, and the second peripheral circuit region 106. The first peripheral circuit region 104 and the second peripheral circuit region 106 are, for example, transistors for forming voltage characteristics different.

In the present embodiment, the memory cell region 102 includes a memory cell region 108 and a selection transistor region 110. A tunneling dielectric layer 112 is formed in the memory cell region 108. The material of the tunneling dielectric layer 112 includes cerium oxide, and the forming method includes a thermal oxidation method or a chemical vapor deposition method. The thickness of the tunneling dielectric layer 112 is approximately 20 Å to 130 Å. Forming the tunneling dielectric layer 112 in the memory cell region 108, for example, forming a dielectric layer (not shown) on the substrate 100, and then removing the first peripheral circuit region 104 and the second peripheral circuit by using a photolithography technique. The dielectric layer on the substrate 106 and the substrate 100 of the selected transistor region 110 leaves only the tunneling dielectric layer 112 in the memory cell region 108.

Next, a first gate dielectric layer 114 is formed on the first peripheral circuit region 104, the second peripheral circuit region 106, and the substrate 100 of the selective transistor region 110. The material of the first gate dielectric layer 114 is, for example, hafnium oxide, and the method of forming the same includes performing a thermal oxidation process or a chemical vapor deposition process in the furnace tube. In addition, in the embodiment, the first gate dielectric layer 114 has a first thickness T ₁ and the first thickness T ₁ is approximately 90 Å to 130 Å. In the present embodiment, the first gate dielectric layer 114 is formed by a process of a gate dielectric layer of an input/output (I/O) transistor in a composite MOS device (CMOS) process.

Please refer to FIG. 1B. A patterned mask layer 115 is formed on the substrate 100. The material of the patterned mask layer 115 is, for example, a photoresist material. The patterned mask layer 115 exposes the first gate dielectric layer 114 in the selected transistor region 110. The method of forming the patterned mask layer 115 is, for example, a lithography technique. With the patterned mask layer 115 as a mask, a portion of the first gate dielectric layer 114 in the selected transistor region 110 is removed to form a second gate dielectric layer 116. The above removal process includes an etching process such as a dry etching process or a wet etching process. The wet etching process uses, for example, hydrofluoric acid as an etchant. In the above removal process, a feedback system (not shown) is employed to control the second thickness T _{2 of the} second gate dielectric layer 116. Wherein, the feedback system includes a monitoring pattern and a short-cycle measuring wafer, that is, after performing an etching, confirming whether the thickness of the second gate dielectric layer 116 reaches a desired thickness, and continuing etching if the desired thickness is not achieved. The process is continued until the desired thickness is reached. The second thickness T _{2 is} less than the first thickness T ₁ and the second thickness T ₂ is approximately 50 Å to 90 Å. Because the second gate dielectric layer 116 is a film layer obtained by removing a portion of the thickness of the first gate dielectric layer, the material of the second gate dielectric layer 116 is substantially the same as the material of the first gate dielectric layer 114. .

Referring to FIG. 1C, the patterned mask layer 115 is removed. The method of removing the patterned mask layer 115, for example, removes most of the photoresist after the ashing process, and then performs a cleaning process to remove residual photoresist. A patterned mask layer 117 is formed on the substrate 100. The patterned mask layer 117 exposes the first gate dielectric layer 114 in the second perimeter circuit region 106. With the patterned mask layer 117 as a mask, all of the first gate dielectric layers 114 in the second peripheral circuit region 106 are removed to expose the substrate 100 in the second peripheral circuit region 106. The removal step described above includes performing an etching process such as a dry etching process or a wet etching process. Wet The etching process uses, for example, hydrofluoric acid as an etchant.

Referring to FIG. 1D, the patterned mask layer 117 is removed. The method of removing the patterned mask layer 117, for example, first removes most of the photoresist by an ashing process, and then performs a cleaning process to remove residual photoresist. A third gate dielectric layer 118 is formed on the substrate 100 in the second peripheral circuit region 106. The material of the third gate dielectric layer 118 is, for example, hafnium oxide, and the method of forming the same includes performing a thermal oxidation process in the furnace tube. The third gate dielectric layer 118 has a third thickness T ₃ and the third thickness T _{3 is} less than the second thickness T ₂ . In this embodiment, the third thickness T ₃ is about 15 Å to 40 Å. In the present embodiment, the third gate dielectric layer 118 is formed by a process of a gate dielectric layer of a core transistor in a composite MOS device (CMOS) process.

It should be noted that, in the present invention, after the first gate dielectric layer 114 in the second peripheral circuit region 106 is completely removed, a third gate dielectric is formed on the substrate 100 in the second peripheral circuit region 106. Layer 118. Therefore, the third gate dielectric layer 118 and the first gate dielectric layer 114 belong to different film layers formed by different processes. The process method can prevent the formed third gate dielectric layer 118 from being affected by the foregoing process, and can make the third gate dielectric layer 118 have better quality. Next, a conductor layer 120 is formed on the entire substrate 100. The material of the conductor layer 120 is, for example, doped polysilicon. The conductor layer 120 is formed by, for example, forming an undoped polysilicon layer by chemical vapor deposition. The implantation step is formed to form; or formed by chemical vapor deposition using a field implant dopant.

Referring to FIG. 1E, the patterned conductor layer 120, the tunneling dielectric layer 112, the second gate dielectric layer 116, the first gate dielectric layer 114, and the third gate dielectric layer 118, a gate structure 122a to a gate structure 122d are formed on the memory cell region 108, the selection transistor region 110, the first peripheral circuit region 104, and the second peripheral circuit region 106, respectively. The gate structure 122a (charge storage structure) is composed of, for example, a gate 120a and a tunnel dielectric layer 112a. The gate structure 122b is composed of, for example, a gate 120b and a second gate dielectric layer 116a. The gate structure 122c is composed of, for example, a gate 120c and a first gate dielectric layer 114a. The gate structure 122d is composed of, for example, a gate 120d and a third gate dielectric layer 118a. Followed by a space process (not shown).

After the spacer process, the dopant implantation step is performed, and the source region 130a and the drain region 130b are formed in the substrate 100 on both sides of the gate structure 122d; the source is formed in the substrate 100 on both sides of the gate structure 122c. The region 132a and the drain region 132b; doped regions 134a to 134c are formed in the substrate 100 on both sides of the gate structure 122a and the gate structure 122b. The dopant implantation step is, for example, implantation of a dopant into the substrate 100 using ion implantation. The gate structure 122d, the source region 130a, and the drain region 130b constitute a transistor 128 (in this embodiment, for example, a core transistor); the gate structure 122c, the source region 132a, and the drain region 132b constitute a transistor 126 ( In this embodiment, for example, an input/output (I/O) transistor; the gate structure 122a, the gate structure 122b, and the doping regions 134a-134c constitute a memory cell 124, wherein the gate structure 122b, the doping region 134b, and The doped region 134c constitutes the selective transistor 124b, and the gate structure 122a, the doped region 134a, and the doped region 134b constitute the floating gate transistor 124a. The subsequent completion of the memory process is well known to those skilled in the art and will not be described here.

Second embodiment

2A to 2C are schematic cross-sectional views showing a manufacturing process of a non-volatile memory according to a second embodiment of the present invention. The second embodiment is similar to the first embodiment, and therefore the same elements are denoted by the same reference numerals and the description thereof will not be repeated.

Referring to FIG. 2A first, in the embodiment, the substrate 100 includes a memory cell region 202, a first peripheral circuit region 104, and a second peripheral circuit region 106. It is noted that the memory cell region 202 includes a memory cell region 208 and a select transistor region 110. A charge storage structure 212 is formed in the memory cell region 208. The charge storage structure 212 includes a bottom dielectric layer 212a, a charge trapping layer 212b, and a top dielectric layer 212c. The bottom dielectric layer 212a material includes ruthenium oxide, and the formation method thereof includes a thermal oxidation method. The bottom dielectric layer 212a has a thickness of about 20 Å to 40 Å. In the present embodiment, the charge trapping layer 212b is a material capable of trapping charges therein, and is selected from the group consisting of tantalum nitride, hafnium oxynitride, aluminum oxide, cerium oxide, zirconium oxide, and other materials capable of storing electric charges. One of them. The method of forming the charge trapping layer 212b includes a chemical vapor deposition method. The material of the top dielectric layer 212c includes ruthenium oxide, and the formation method thereof includes chemical vapor deposition.

In this embodiment, the step of forming the charge storage structure 212 in the memory cell region 208, for example, prior to the substrate 100, sequentially forms a bottom dielectric layer (not shown), a charge trapping layer (not shown), and a top dielectric. a layer (not shown), then removing the first peripheral circuit region 104, the second peripheral circuit region 106, and the top dielectric layer, the charge trapping layer, and the bottom dielectric on the substrate 100 of the selected transistor region 110 by a photolithography process Electrical layer. The above photolithography process only leaves The bottom dielectric layer 212a, the charge trapping layer 212b, and the top dielectric layer 212c of the lower memory cell region 208 constitute a charge storage structure 212.

Next, a first gate dielectric layer 114 is formed on the substrate 100 of the first peripheral circuit region 104, the second peripheral circuit region 106, and the selective transistor region 110 in the process of the first embodiment. Therefore, in the present embodiment, the first gate dielectric layer 114 is the same as the first gate dielectric layer 114 in the first embodiment, and thus will not be described herein.

Please refer to FIG. 2B. The second gate dielectric layer 116 is formed in the process of the first embodiment (as shown in FIGS. 1B to 1C). The thickness of the second gate dielectric layer 116 is greater than the thickness of the bottom dielectric layer 212a. Next, a third gate dielectric layer 118 is formed in the process of the first embodiment (as shown in FIGS. 1D to 1E). Therefore, the substrate 100 in FIG. 2B includes a charge storage structure 212, a first gate dielectric layer 114, a second gate dielectric layer 116, and a third gate dielectric layer 118. In the present embodiment, the first gate dielectric layer 114, the second gate dielectric layer 116, and the third gate dielectric layer 118 are the same as those of the first embodiment.

Next, a conductor layer 120' is formed on the entire substrate 100. The material and formation method of the conductor layer 120' are the same as those of the conductor layer 120 in the first embodiment. However, in the present embodiment, the conductor layer 120' covers the memory cell region 202 and the memory cell region 208; however, in the first embodiment, the conductor layer 120 covers the memory cell region 102 and the memory cell region 108. That is, the conductor layer 120' is substantially identical to the conductor layer 120 except that the areas covered by the two differ.

Referring to FIG. 2C, the patterned conductor layer 120', the charge storage structure 212, The second gate dielectric layer 116, the first gate dielectric layer 114 and the third gate dielectric layer 118 are in the memory cell region 208, the selection transistor region 110, the first peripheral circuit region 104, and the second peripheral circuit region 106. A gate structure 222a and a gate structure 122b to a gate structure 122d are formed on the upper side. The gate structure 222a includes a gate 120a', a top dielectric layer 212c', a charge trapping layer 212b', and a bottom dielectric layer 212a'. Followed by an interval process (not shown).

After the spacer process, the dopant implantation step is performed, and the source region 130a and the drain region 130b are formed in the substrate 100 on both sides of the gate structure 122d; the source is formed in the substrate 100 on both sides of the gate structure 122c. The region 132a and the drain region 132b; doped regions 134a to 134c are formed in the substrate 100 on both sides of the gate structure 222a and the gate structure 122b. The dopant implantation step is, for example, implantation of a dopant into the substrate 100 using ion implantation. The gate structure 122d, the source region 130a, and the drain region 130b constitute a transistor 128 (in this embodiment, for example, a core transistor); the gate structure 122c, the source region 132a, and the drain region 132b constitute a transistor 126 ( In this embodiment, for example, an input/output (I/O) transistor; the gate structure 222a, the gate structure 122b, and the doping regions 134a-134c constitute a memory cell 224, wherein the gate structure 122b, the doping region 134b, and The doped region 134c constitutes the selective transistor 124b, and the gate structure 222a, the doped region 134a, and the doped region 134b constitute the memory cell transistor 224a. In the present embodiment, the transistor 128 (for example, a core transistor), the transistor 126 (for example, an input/output (I/O) transistor), and the selection transistor 124b are all the same as those of the first embodiment. The same is true, so it will not be specifically described here. The subsequent completion of the memory process is well known to those skilled in the art and will not be described here.

In the first embodiment and the second embodiment, the thickness of the second gate dielectric layer 116a of the selected transistor 124b (about 50 Å to 90 Å) is smaller than the transistor 126 (for example, input/output (I/O)). The thickness of the first gate dielectric layer 114a of the transistor. Moreover, the thickness T ₂ of the second gate dielectric layer 116a of the transistor 124b is selected to be about 50 Å to 90 Å, so that the driving voltage of the selected transistor 124b is higher than that of the transistor 126 (for example, an input/output (I/O) transistor. )small. Furthermore, the manufacturing method of the present invention is applicable to the fabrication of N-type or P-type non-volatile memory, and can be integrated with a process of a composite MOS device (CMOS).

The present invention etches back the first gate dielectric layer 114 using a photolithography process and monitors the process in conjunction with a feedback system. Thus, a thinner second gate dielectric layer 116 having a desired thickness can be fabricated. After the second gate dielectric layer 116 integrates the subsequent processes to form the dielectric layer of the selected transistor, the selected transistor can have a higher driving current. In addition, the present invention also removes the first gate dielectric layer 114 in the second peripheral circuit region 106 by photolithography, and then forms a thin third gate dielectric layer 118, thereby fabricating a higher driving. A transistor with current and a higher rate of guided messages. According to the method of manufacturing a non-volatile memory of the present invention, various transistors having different gate dielectric layer thicknesses can be fabricated as components of peripheral circuits.

In summary, the method for fabricating the non-volatile memory of the present invention can reduce the thickness of the gate dielectric layer of the selected transistor without increasing the complexity of the process, thereby reducing the driving current of the memory cell and It can increase the rate of its guided messages and achieve the advantage of increasing the operating rate of non-volatile memory components. In another aspect, the present invention utilizes different processes to fabricate a core transistor. The gate dielectric layer and the gate dielectric layer of the input/output (I/O) transistor can also form peripheral circuit transistors having different driving capabilities. Moreover, the manufactured core transistor having a thinner gate dielectric layer can have better quality and higher driving current. Therefore, the non-volatile memory manufactured by the manufacturing method of the present invention will have a higher driving ability and can be applied to a design with higher integration.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

102, 202‧‧‧ memory cells

104‧‧‧First peripheral circuit area

106‧‧‧Second peripheral circuit area

108, 208‧‧‧ memory unit area

110‧‧‧Selecting the transistor area

112, 112a‧‧‧ Tunneling dielectric layer

114, 114a‧‧‧ first dielectric layer

115‧‧‧ patterned mask layer

116, 116a‧‧‧Second dielectric layer

117‧‧‧ patterned mask layer

118, 118a‧‧‧ third dielectric layer

120, 120'‧‧‧ conductor layer

120a, 120a', 120b, 120c, 120d‧‧‧ gate

122a, 122b, 122c, 122d, 222a‧‧‧ gate structure

124‧‧‧ memory cells

124a, 124b, 126, 128, 224a‧‧‧ transistors

130a, 132a‧‧‧ source area

130b, 132b‧‧‧ bungee area

134a, 134b, 134c‧‧‧ doped areas

212‧‧‧Charge storage structure

212a, 212a'‧‧‧ bottom dielectric layer

212b, 212b’‧‧‧ Charge trapping layer

212c, 212c'‧‧‧ top dielectric layer

T ₁ ‧‧‧first thickness

T ₂ ‧‧‧second thickness

T ₃ ‧‧‧ third thickness

1A to 1E are schematic cross-sectional views showing a manufacturing process of a non-volatile memory according to an embodiment of the present invention.

2A through 2C are schematic cross-sectional views showing a manufacturing process of a non-volatile memory according to another embodiment of the present invention.

100‧‧‧Base

102‧‧‧ memory area

104‧‧‧First peripheral circuit area

106‧‧‧Second peripheral circuit area

108‧‧‧Memory unit area

110‧‧‧Selecting the transistor area

112a‧‧‧Tunnel dielectric layer

114a‧‧‧First dielectric layer

116a‧‧‧Second dielectric layer

118a‧‧‧ Third dielectric layer

120a, 120b, 120c, 120d‧‧‧ gate

122a, 122b, 122c, 122d‧‧‧ gate structure

124‧‧‧ memory cells

124a, 124b, 126, 128‧‧‧ transistors

130a, 132a‧‧‧ source area

130b, 132b‧‧‧ bungee area

134a, 134b, 134c‧‧‧ doped areas

T ₁ ‧‧‧first thickness

T ₂ ‧‧‧second thickness

T ₃ ‧‧‧ third thickness

Claims (12)

A method of fabricating a non-volatile memory, comprising: providing a substrate, the substrate comprising a memory cell region, a first peripheral circuit region, and a second peripheral circuit region, the memory cell region including a selective transistor region; Forming a first thyristor layer on the first peripheral circuit region and the substrate of the select transistor region, the first thyristor layer having a first thickness; removing the portion of the selected transistor region a first gate dielectric layer to form a second gate dielectric layer, the second gate dielectric layer having a second thickness, wherein the second thickness is less than the first thickness; in the first peripheral circuit region and the In the step of forming a first gate dielectric layer on the substrate of the transistor region, forming the first gate dielectric layer on the substrate of the second peripheral circuit region; removing the second peripheral circuit region a first gate dielectric layer; and a third gate dielectric layer formed on the substrate on the second peripheral circuit region, the third gate dielectric layer having a third thickness, wherein the third thickness is less than the third Second thickness. The method for manufacturing a non-volatile memory according to claim 1, wherein the memory cell region comprises a memory cell region; and a charge storage structure is formed in the memory cell region, the charge storage structure including a tunneling a dielectric layer and a charge storage layer. The method of manufacturing a non-volatile memory according to claim 2, wherein the material of the charge storage layer comprises doped polysilicon. Non-volatile memory as described in claim 1 The manufacturing method, wherein the memory cell region comprises a memory cell region; and forming a charge storage structure in the memory cell region, the charge storage structure comprising a bottom dielectric layer, a charge trapping layer and a top dielectric layer. The method for producing a non-volatile memory according to claim 4, wherein the material of the charge trapping layer is selected from the group consisting of tantalum nitride, bismuth oxynitride, aluminum oxide, cerium oxide, zirconium oxide, and others capable of storing charges. One of the groups of materials. The method of fabricating a non-volatile memory according to claim 1, wherein the first gate dielectric layer functions as a gate dielectric layer of an input/output (I/O) transistor. The method for manufacturing a non-volatile memory according to claim 1, wherein the first gate dielectric layer has a thickness of 90 Å to 130 Å, and the second gate dielectric layer has a thickness of 50 Å to 90 Å. The method of manufacturing a non-volatile memory according to claim 1, wherein the step of removing the portion of the first gate dielectric layer on the selected transistor region to form the second gate dielectric layer Including the lithography process. The method of fabricating the non-volatile memory of claim 4, wherein the thickness of the bottom dielectric layer is less than the second thickness of the second gate dielectric layer. The method of manufacturing a non-volatile memory according to claim 1, wherein the first gate dielectric layer is a gate dielectric layer of an input/output (I/O) transistor, and the third gate dielectric layer As a gate dielectric layer of the core transistor. Non-volatile memory as described in claim 1 The manufacturing method, wherein the first gate dielectric layer has a thickness of 90 Å to 130 Å, the second gate dielectric layer has a thickness of 50 Å to 90 Å, and the third gate dielectric layer has a thickness of 15 Å to 40 Å. The method of manufacturing the non-volatile memory of claim 1, wherein the step of removing the first gate dielectric layer on the second peripheral circuit region comprises performing a photolithography process; The step of forming the third gate dielectric layer on the substrate on the peripheral circuit region includes performing a thermal oxidation process.