TWI566383B - Nonvolatile memory - Google Patents

Description

Non-volatile memory

This invention relates to a semiconductor component, and more particularly to a non-volatile memory.

As the semiconductor enters the Deep Sub-Micron process, the size of the component is gradually reduced, and for the memory component, it means that the memory cell size is getting smaller and smaller. On the other hand, as information electronics (such as computers, mobile phones, digital cameras, or personal digital assistants (PDAs)) need to process and store more and more data, the memory required in these information electronics The capacity is getting bigger and bigger. In the case where the size is small and the memory capacity needs to be increased, how to manufacture a memory element having a reduced size, a high degree of integration, and a quality can be a consistent goal of the industry.

Since the non-volatile memory element has the advantage that the stored data does not disappear after the power is turned off, it has become a memory element widely used in personal computers and electronic devices.

A conventional non-volatile memory consisting of two series of two P-type MOS transistors disposed on the N well as a selective transistor and a floating gate transistor Body composition. Since only one layer of polysilicon is required, the process of such a non-volatile memory can be integrated with the process of the complementary MOS transistor to reduce manufacturing costs.

However, after the transistor is fabricated, and after the subsequent fabrication of the contact window, a contact etch stop layer is formed which covers the floating gate transistor of the memory cell region and the transistor of the peripheral circuit region. The material of the contact etch stop layer is tantalum nitride formed by plasma enhanced chemical vapor deposition, which causes the floating gate transistor to have a low on current and a poor retention performance. . However, if the material of the contact etch stop layer is changed, the performance of the transistor in the peripheral circuit region is affected.

In view of the above, the present invention provides a non-volatile memory that can improve the maintenance performance of a floating gate transistor without affecting the performance of the transistor in the peripheral circuit region and the selection transistor of the memory cell region.

The non-volatile memory of the present invention is disposed on a substrate including a peripheral circuit region and a memory cell region. The non-volatile memory includes a floating gate transistor, a transistor, a Self Alignment Barrier (SAB), a stretched layer, and a contact etch stop layer. The floating gate transistor is disposed in the memory cell region. The transistor is disposed in the peripheral circuit area. The self-aligned barrier layer is disposed on the floating gate of the floating gate transistor. The stretch layer is only placed on the floating gate. A contact etch stop layer covers the entire transistor.

In an embodiment of the invention, the contact etch stop layer is more covered A floating gate transistor; the stretch layer is disposed between the contact etch stop layer and the self-aligned barrier layer and completely surrounds the floating gate.

In an embodiment of the invention, the stretch layer is disposed on the self-aligned barrier layer and partially surrounds the floating gate.

In an embodiment of the invention, the contact etch stop layer further covers the floating gate transistor; the stretch layer is disposed between the floating gate and the self-aligned barrier layer, and completely surrounds the floating gate And a liner disposed between the stretch layer and the floating gate.

In an embodiment of the invention, the non-volatile memory further includes: a selection transistor disposed in the memory cell region, connected in series with the floating gate transistor; and a contact etching stop layer covering the transistor Select the transistor as a whole.

In an embodiment of the invention, the contact etch stop layer further covers the floating gate transistor; the stretch layer is disposed between the contact etch stop layer and the self-aligned barrier layer, and completely surrounds the floating gate .

In an embodiment of the invention, the stretch layer is disposed on the self-aligned barrier layer and partially surrounds the floating gate.

In an embodiment of the invention, the contact etch stop layer further covers the floating gate transistor; the stretch layer is disposed between the floating gate and the self-aligned barrier layer, and completely surrounds the floating gate And a liner disposed between the stretch layer and the floating gate.

In an embodiment of the invention, the transistor is a core metal MOS transistor or an input/output metal oxide semiconductor (I/O MOS) transistor.

In an embodiment of the invention, the material of the stretched layer is nitrogen rich silicon nitride.

In an embodiment of the invention, the material of the self-aligned barrier layer is yttrium oxide.

The non-volatile memory of the present invention is disposed on a substrate including a peripheral circuit region and a memory cell region. The non-volatile memory includes a floating gate transistor, a transistor, a self-aligned barrier layer, and a contact etch stop layer. The floating gate transistor is disposed in the memory cell region. The transistor is disposed in the peripheral circuit area. A self-aligned barrier layer is disposed on the floating gate of the floating gate transistor; and a contact etch stop layer covers the entire transistor and exposes the self-aligned barrier layer on the floating gate.

In an embodiment of the invention, the non-volatile memory further includes: a selection transistor disposed in the memory cell region, connected in series with the floating gate transistor; and a contact etch stop layer covering the entire selection transistor.

In an embodiment of the invention, the material of the self-aligned barrier layer is yttrium oxide.

In an embodiment of the invention, the transistor is a core MOS transistor or an input/output metal oxide semiconductor (I/O MOS) transistor.

In the non-volatile memory of the present invention, a self-aligned barrier layer and a contact etch stop layer are provided, and a stretch layer is disposed on the floating gate or a contact etch stop layer on the floating gate is removed, thereby The maintenance performance of the floating gate transistor is improved without affecting the performance of the transistor of the peripheral circuit region and the selection transistor of the memory cell region. The stretched layer (the layer in which less electrons are trapped) can function as a barrier layer to isolate the floating gate from the effects of low turn-on current caused by contact with the etch stop layer. Removing the contact etch stop layer on the floating gate can reduce Charge loss. And the performance of the transistor of the peripheral circuit region and the selected transistor of the memory cell region can be maintained.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Base

102‧‧‧ memory area

104‧‧‧ peripheral circuit area

106‧‧‧Floating gate transistor

108‧‧‧Selecting a crystal

110‧‧‧Optoelectronics

112‧‧‧Self-aligned barrier layer

114, 114a, 114b‧‧‧ tensile layer

116, 116a, 116b‧‧‧ contact etch stop layer

118‧‧‧Floating gate

120‧‧‧Tunnel dielectric layer

122, 124, 132, 140, 142‧‧‧ doped areas

126, 134, 144‧‧ ‧ spacers

128‧‧‧Select gate

130‧‧‧Selecting the gate dielectric layer

136‧‧‧ gate

138‧‧‧ gate dielectric layer

1 is a cross-sectional view of a non-volatile memory in accordance with a preferred embodiment of the present invention.

2 is a cross-sectional view of a non-volatile memory in accordance with a preferred embodiment of the present invention.

3 is a cross-sectional view of a non-volatile memory in accordance with a preferred embodiment of the present invention.

4 is a cross-sectional view of a non-volatile memory in accordance with a preferred embodiment of the present invention.

1 is a cross-sectional view of a non-volatile memory in accordance with a preferred embodiment of the present invention. Referring to FIG. 1, the non-volatile memory of the present invention is disposed on a substrate 100. The substrate 100 is, for example, a crucible substrate. The substrate 100 has a memory cell region 102 and a peripheral circuit region 104.

Non-volatile memory includes floating gate transistor 106, selective transistor 108. The transistor 110, the self-aligned barrier layer 112, the stretched layer 114, and the contact etch stop layer 116.

The floating gate transistor 106 is disposed in the memory cell region 102. The floating gate transistor 106 includes a floating gate 118, a tunneling dielectric layer 120, a doping region 122, and a doping region 124. The floating gate 118 is disposed, for example, on the substrate 100. The material of the floating gate 118 is, for example, polysilicon. The tunneling dielectric layer 120 is disposed, for example, between the floating gate 118 and the substrate 100. The material of the tunneling dielectric layer 120 is, for example, yttrium oxide. The doped region 122 and the doped region 124 are respectively disposed in the substrate 100 on both sides of the floating gate 118. A spacer 126 may also be disposed on the sidewall of the floating gate 118. The spacer 126 is made of, for example, tantalum oxide or tantalum nitride.

The selection transistor 108 is disposed in the memory cell region 102 and is connected in series with the floating gate transistor 106. The select transistor 108 includes a select gate 128, a select gate dielectric layer 130, a doped region 124, and a doped region 132. The selection gate 128 is disposed, for example, on the substrate 100. The gate dielectric layer 130 is selected, for example, between the select gate 128 and the substrate 100. The material of the gate dielectric layer 130 is selected, for example, from yttrium oxide or other insulating layer which can form a gate oxide layer (such as a high dielectric value oxide layer such as HfO ₂ , Al ₂ O _{3 ,} etc.). The thickness of the tunneling dielectric layer 120 and the selective gate dielectric layer 130 are, for example, the same or different. The doped region 124 and the doped region 132 are respectively disposed in the substrate 100 on both sides of the selection gate 128, wherein the floating gate transistor 106 and the selective transistor 108 share the doping region 124. A spacer 134 may also be disposed on the sidewall of the selection gate 128. The spacer 134 is made of, for example, tantalum oxide or tantalum nitride.

The transistor 110 is disposed in the peripheral circuit region 104. The transistor 110 includes a gate 136, a gate dielectric layer 138, a doped region 140, and a doped region 142. The gate 136 is disposed, for example, on the substrate 100. The gate dielectric layer 138 is disposed, for example, between the gate 136 and the substrate 100. The material of the gate dielectric layer 138 is, for example, yttrium oxide or other insulating layer (such as a high dielectric value oxide layer such as HfO ₂ , Al ₂ O _{3 ,} etc.) which can form a gate oxide layer. The doped region 140 and the doped region 142 are respectively disposed in the substrate 100 on both sides of the gate 136. A spacer 144 may also be disposed on the sidewall of the gate 136. The spacer 144 is made of, for example, tantalum oxide or tantalum nitride.

The transistor 110 is, for example, an input/output metal oxide semiconductor (I/O MOS) transistor or a core MOS transistor. Taking the 40 nm process as an example, when the transistor 110 is a core MOS transistor, the thickness of the gate dielectric layer 138 is, for example, 20 Å to 30 Å. When the transistor 110 is an input/output metal oxide semiconductor (I/O MOS) transistor, the thickness of the gate dielectric layer 138 is, for example, 50 Å to 70 Å.

The floating gate transistor 106, the selection transistor 108, and the transistor 110 may be one of an N-type transistor or a P-type transistor.

The self-aligned barrier layer 112 is disposed on the floating gate 118 of the floating gate transistor 106. The material of the self-aligned barrier layer 112 is, for example, yttrium oxide. The self-aligned barrier layer 112 encapsulates the floating gate 118.

The contact etch stop layer 116 covers the entire transistor 110 and the entire select transistor 108, and the contact etch stop layer 116 covers the floating gate transistor 106. The material of the contact etch stop layer 116 is, for example, tantalum nitride.

A tensile layer 114 is disposed only on the floating gate 118. In this In the invention, the stretched layer 114 refers to a film layer in which less electrons are trapped. That is, the material of the tensile layer 114 is a material that is less likely to trap electrons therein, such as nitrogen rich silicon nitride, wherein the tensile layer has a refractive index of less than 2 (Refractive index<2). .

The stretch layer 114 is disposed between the contact etch stop layer 116 and the self-aligned barrier layer 112 and completely surrounds the floating gate 118. This tensile layer 114 can function as a barrier layer to isolate the floating gate 118 from the effects of low on current caused by contact with the etch stop layer 116.

In the non-volatile memory of the present invention, the stretched layer 114 is disposed between the contact etch stop layer 116 and the floating gate 118. The stretching layer 114 is not disposed on the transistor 110 and the selective transistor 108, so that the floating can be improved without affecting the performance of the transistor 110 of the peripheral circuit region 104 and the selective transistor 108 of the memory cell region 102. The retention performance of the gate transistor 106. Moreover, by providing the stretched layer 114, the thickness of the self-aligned barrier layer 112 can also be reduced.

The non-volatile memory shown in FIG. 1 is fabricated as follows: After the floating gate transistor 106, the selective transistor 108, and the transistor 110 are completed, a layer of dielectric material is formed on the substrate 100. Next, the layer of dielectric material is patterned leaving only the layer of dielectric material on the floating gate transistor 106 to form the self-aligned barrier layer 112. A layer of stretched material is then formed on the substrate 100 to form a layer of stretched material for forming the mask of the self-aligned barrier layer 112 to form the stretched layer 114. Thereafter, a contact etch stop layer 116 is formed on the substrate 100. Since no additional mask is needed to form the pull The layer 114 is stretched so that it can be integrated with existing processes without affecting the performance of the surrounding components.

In the above embodiment, the description is made by taking the floating cell transistor 106 and the selection transistor 108 in the memory cell region 102 as an example. Of course, the present invention is also applicable to an example in which the memory cell region 102 is provided with only the floating gate transistor 106.

2 is a cross-sectional view of a non-volatile memory in accordance with a preferred embodiment of the present invention. In the present embodiment, members are denoted by the same reference numerals as those of the non-volatile memory shown in Fig. 1, and the description thereof will be omitted.

The non-volatile memory shown in FIG. 2 differs from the non-volatile memory shown in FIG. 1 in that the stretched layer and the contact etch stop layer are disposed at different positions.

As shown in FIG. 2, the contact etch stop layer 116a covers only the entire transistor 110 and the entire selection transistor 108. However, the contact etch stop layer 116a does not cover the floating gate 118, but exposes the self-aligned barrier layer 112. The material of the contact etch stop layer 116a is, for example, tantalum nitride.

The tensile layer 114a is disposed on the self-aligned barrier layer 112 and partially surrounds the floating gate 118. The stretched layer 114a refers to a film layer in which less electrons are trapped. That is, the material of the stretched layer 114a is a material that is less likely to trap electrons therein, such as nitrogen rich silicon nitride, wherein the tensile layer has a refractive index of less than 2 (Refractive index<2). .

In the non-volatile memory of the present invention, the floating gate 118 is not covered with the contact etch stop layer 116a and covered with the stretched layer 114a, and the low turn-on current caused by the contact etch stop layer 116a can be avoided (Low On Current) )Impact. Electron crystal The stretched layer 114a is not disposed on the body 110 and the selective transistor 108, so that the floating gate can be improved without affecting the performance of the transistor 110 of the peripheral circuit region 104 and the selected transistor 108 of the memory cell region 102. The retention performance of the transistor 106. Moreover, if the stretched layer 114a is provided, the thickness of the self-aligned barrier layer 112 can also be reduced.

The non-volatile memory shown in FIG. 2 is fabricated as follows: After the floating gate transistor 106, the selective transistor 108, and the transistor 110 are completed, a layer of dielectric material is formed on the substrate 100. Next, the layer of dielectric material is patterned leaving only the layer of dielectric material on the floating gate transistor 106 to form the self-aligned barrier layer 112. A layer of contact etch stop material is formed on the substrate 100. The contact etch stop material layer (only the contact etch stop material layer on the self-aligned barrier layer 112 is removed) is patterned with a reticle for forming the self-aligned barrier layer 112 to form a contact etch stop layer 116a. Forming a layer of stretched material on the substrate 100 to form a mask of the self-aligned barrier layer 112 to pattern the layer of stretched material (using different photoresist characteristics, leaving only the self-aligned barrier layer The layer of stretched material on 112) forms a stretched layer 114a. Since an additional mask is not required to form the contact etch stop layer 116a, the stretch layer 114a, it can be integrated with existing processes without affecting the performance of the peripheral components.

3 is a cross-sectional view of a non-volatile memory in accordance with a preferred embodiment of the present invention. In the present embodiment, members are denoted by the same reference numerals as those of the non-volatile memory shown in Fig. 1, and the description thereof will be omitted.

The non-volatile memory shown in FIG. 3 differs from the non-volatile memory shown in FIG. 1 in the position of the self-aligned barrier layer, the stretched layer, and the contact etch stop layer. different.

As shown in FIG. 3, the sidewalls of the floating gate 118 are not provided with spacers.

A Self Alignment Barrier (SAB) 112 is disposed on the floating gate 118 of the floating gate transistor 106. The material of the self-aligned barrier layer 112 is, for example, yttrium oxide. The self-aligned barrier layer 112 encapsulates the floating gate 118.

The contact etch stop layer 116 covers the entire transistor 110 and the entire select transistor 108, and the contact etch stop layer 116 covers the floating gate transistor 106. The material of the contact etch stop layer 116 is, for example, tantalum nitride.

A tensile layer 114b is disposed only on the floating gate 118. In the present invention, the stretched layer 114b refers to a film layer in which less electrons are trapped. That is, the material of the stretched layer 114b is a material that is less likely to trap electrons therein, such as nitrogen rich silicon nitride, wherein the tensile layer has a refractive index of less than 2 (Refractive index<2). .

The tensile layer 114b is disposed between the floating gate 118 and the self-aligned barrier layer 112 and completely surrounds the floating gate 118. A liner layer 146 is further disposed between the stretched layer 114b and the floating gate 118. The stretch layer 114b can function as a barrier layer to isolate the floating gate 118 from the effects of low on current caused by contact with the etch stop layer 116.

In the non-volatile memory of the present invention, the stretched layer 114b is disposed between the floating gate 118 and the self-aligned barrier layer 112. The stretched layer 114b is not disposed on the transistor 110 and the selective transistor 108, so that the performance of the transistor 110 of the peripheral circuit region 104 and the selected transistor 108 of the memory cell region 102 can be affected. In this case, the retention performance of the floating gate transistor 106 is improved. Moreover, by providing the stretched layer 114b, the thickness of the self-aligned barrier layer 112 can also be reduced.

The non-volatile memory shown in FIG. 3 is prepared as follows: after the floating gate 118, the selection gate 128, and the gate 136 are completed, a layer of a liner material and a layer of tensile material are sequentially formed on the substrate 100. Floor. Next, the liner material layer and the stretch material layer are patterned with a reticle for forming a floating gate leaving only the liner layer 146 and the stretch layer 114b on the floating gate 118. A layer of dielectric material is formed on the substrate 100. Next, the layer of dielectric material is patterned leaving only the layer of dielectric material on the floating gate transistor 106 to form the self-aligned barrier layer 112. A contact etch stop layer 116 is then formed over the substrate 100. The same can be integrated with existing processes without affecting the performance of the surrounding components.

4 is a cross-sectional view of a non-volatile memory in accordance with a preferred embodiment of the present invention. In the present embodiment, members are denoted by the same reference numerals as those of the non-volatile memory shown in Fig. 1, and the description thereof will be omitted.

The non-volatile memory shown in FIG. 4 is different from the non-volatile memory shown in FIG. 1 in that no stretched layer is provided and the set positions of the etch stop layer are different.

As shown in FIG. 4, contact etch stop layer 116 covers the entire transistor 110 and the entire select transistor 108. However, the contact etch stop layer 116b does not overlie the floating gate 118 and exposes the self-aligned barrier layer 112 on the floating gate 118.

In the non-volatile memory of the present invention, the floating gate 118 is not covered with the contact etch stop layer 116b, which can reduce charge loss and avoid contact etching. The effect of the low on current caused by the stop layer 116b increases the retention performance of the floating gate transistor 106.

The non-volatile memory shown in FIG. 4 is fabricated as follows: After the floating gate transistor 106, the selective transistor 108, and the transistor 110 are completed, a layer of dielectric material is formed on the substrate 100. Next, the layer of dielectric material is patterned leaving only the layer of dielectric material on the floating gate transistor 106 to form the self-aligned barrier layer 112. A layer of contact etch stop material is formed on the substrate 100. Contact etch stop material layer patterned with a reticle for forming self-aligned barrier layer 112 (using different photoresist characteristics, only the contact etch stop material layer on self-aligned barrier layer 112 is removed), A contact etch stop layer 116b is formed. Since an additional mask is not required to form the contact etch stop layer 116b, it can be integrated with existing processes without affecting the performance of the peripheral components.

In summary, in the non-volatile memory of the present invention, the self-aligned barrier layer and the contact etch stop layer are provided, and the stretch etch layer is disposed on the floating gate or the contact etch stop on the floating gate is removed. The layer can thereby improve the maintenance performance of the floating gate transistor without affecting the transistor of the peripheral circuit region and the performance of the selected transistor of the memory cell region. The stretched layer (the layer in which less electrons are trapped) can function as a barrier layer to isolate the floating gate from the effects of low turn-on current caused by contact with the etch stop layer. Removing the contact etch stop layer on the floating gate reduces charge loss. And the performance of the transistor of the peripheral circuit region and the selected transistor of the memory cell region can be maintained.

Although the present invention has been disclosed above by way of example, it is not intended to limit the present invention. The scope of the present invention is defined by the scope of the appended claims, which are defined by the scope of the appended claims. quasi.

100‧‧‧Base

102‧‧‧ memory area

104‧‧‧ peripheral circuit area

106‧‧‧Floating gate transistor

108‧‧‧Selecting a crystal

110‧‧‧Optoelectronics

112‧‧‧Self-aligned barrier layer

114‧‧‧Stretching layer

116‧‧‧Contact etch stop layer

118‧‧‧Floating gate

120‧‧‧Tunnel dielectric layer

122, 124, 132, 140, 142‧‧‧ doped areas

126, 134, 144‧‧ ‧ spacers

128‧‧‧Select gate

130‧‧‧Selecting the gate dielectric layer

136‧‧‧ gate

138‧‧‧ gate dielectric layer

Claims (15)

A non-volatile memory is disposed on a substrate including a peripheral circuit region and a memory cell region, and includes: a floating gate transistor disposed in the memory cell region; and a transistor disposed on the peripheral circuit a self-aligned barrier layer disposed on a floating gate of the floating gate transistor; a stretched layer disposed only on the floating gate; and a contact etch stop layer covering the entire The transistor. The non-volatile memory of claim 1, wherein the contact etch stop layer covers the floating gate transistor; the stretch layer is disposed on the contact etch stop layer and the self-alignment Between the barrier layers, and completely surrounding the floating gate. The non-volatile memory of claim 1, wherein the tensile layer is disposed on the self-aligned barrier layer and partially surrounds the floating gate. The non-volatile memory of claim 1, wherein the contact etch stop layer further covers the floating gate transistor; the stretch layer is disposed on the floating gate and the self-aligned resistor Between the barrier layers, and completely surrounding the floating gate; and a liner disposed between the tensile layer and the floating gate. The non-volatile memory of claim 1, further comprising: a selection transistor disposed in the memory cell region and connected in series with the floating gate transistor; The contact etch stop layer covers the entire selected transistor. The non-volatile memory of claim 5, wherein the contact etch stop layer further covers the floating gate transistor; the stretch layer is disposed on the contact etch stop layer and the self-aligned resistor Between the barrier layers, and completely surrounding the floating gate. The non-volatile memory of claim 5, wherein the stretch layer is disposed on the self-aligned barrier layer and partially surrounds the floating gate. The non-volatile memory of claim 5, wherein the contact etch stop layer further covers the floating gate transistor; the stretch layer is disposed on the floating gate and the self-aligned resistor Between the barrier layers, and completely surrounding the floating gate; and a liner disposed between the tensile layer and the floating gate. The non-volatile memory of claim 1, wherein the transistor is a core MOS transistor or an input/output MOS transistor. The non-volatile memory of claim 1, wherein the tensile layer is made of nitrogen-rich cerium nitride. The non-volatile memory of claim 1, wherein the self-aligned barrier layer is made of yttrium oxide. A non-volatile memory is disposed on a substrate including a peripheral circuit region and a memory cell region, and includes: a floating gate transistor disposed in the memory cell region; and a transistor disposed on the peripheral circuit Area; a self-aligned barrier layer disposed on a floating gate of the floating gate transistor; and a contact etch stop layer covering the entire transistor and exposing the self-pair on the floating gate Quasi-barrier layer. The non-volatile memory of claim 12, further comprising: a selection transistor disposed in the memory cell region, connected in series with the floating gate transistor; and the contact etch stop layer covering The entire selection of the transistor. The non-volatile memory of claim 1, wherein the self-aligned barrier layer is made of yttrium oxide. The non-volatile memory of claim 1, wherein the transistor is a core MOS transistor or an input/output MOS transistor.