TWI500087B - Semiconductor process - Google Patents

Description

Semiconductor process

This invention relates to a semiconductor process and, more particularly, to a damascene process.

As the degree of integration of semiconductor components increases, the use of multiple metal interconnects becomes more widespread. Generally, the lower the resistance of the metal layer of the multiple metal interconnect, the higher the reliability and the better the performance of the component. Among metal materials, copper metal has a low resistance and is very suitable for use as a multi-metal interconnect, but since copper metal is difficult to be patterned by conventional lithography, a dual damascene process has been developed.

The dual damascene process is a technique in which trenches and via openings (or contact openings) are formed in the dielectric layer and metal is backfilled to form metal and vias (or contact windows). Generally, a plurality of material layers such as a liner layer, a dielectric layer, and a metal hard mask layer are sequentially formed on the substrate on which the patterned conductor layer has been formed, and then a portion of the dielectric layer is removed to be dielectrically A dual damascene opening exposing the patterned conductor layer is formed in the layer. However, due to stress variation and stress imbalance between a plurality of different material layers such as a metal hard mask layer, a dielectric layer, and a liner layer, the double damascene opening is reduced or deformed by the above stress after formation. , making its key size smaller than expected. In other words, the double damascene opening formed by the metal hard mask layer encounters the problem of line distortion, which leads to the subsequent metal backfilling step being difficult to perform, and the formed double damascene structure may have a via window open circuit. (via open) or a defect with too high resistance.

The present invention provides a semiconductor process that uses a metal hard mask layer to form a damascene opening and to have the damascene opening have the desired critical dimensions.

The present invention proposes a semiconductor process. First, a substrate is provided on which a patterned conductor layer, a first dielectric layer, and a patterned metal hard mask layer are sequentially formed. Next, a portion of the first dielectric layer is removed to form a damascene opening exposing the patterned conductor layer. Then, a heating step is performed to heat the first dielectric layer to greater than 200 °C. Next, the metal damascene opening is subjected to a plasma treatment step, wherein the plasma generating gas includes hydrogen gas and blunt gas. A conductor layer is then formed in the damascene opening to fill the damascene opening.

In an embodiment of the invention, the embossed opening is a double damascene opening.

In one embodiment of the invention, the tessellation opening has a first critical dimension prior to performing the plasma processing step and a second critical dimension greater than the first critical dimension after the plasma processing step.

In one embodiment of the invention, the molecular size of the ablative gas described above is similar to the molecular size of hydrogen.

In an embodiment of the invention, the ablative gas described above comprises helium.

In an embodiment of the invention, the heating step comprises heating the first dielectric layer to between 200 ° C and 350 ° C.

In an embodiment of the invention, in the plasma processing step, the microwave power source is used as the power source.

In an embodiment of the invention, the first dielectric layer and the patterned metal hard mask layer further comprise a second dielectric layer.

In an embodiment of the invention, the patterned conductor layer and the first dielectric layer further comprise a liner layer.

In an embodiment of the invention, the step of removing a portion of the first dielectric layer further includes removing a portion of the liner.

In an embodiment of the invention, the ratio of hydrogen to blunt gas in the gas produced is from 1:25 to 1:10.

In an embodiment of the invention, the flow rate of the generated gas is from 5000 sccm to 10000 sccm.

In an embodiment of the invention, the power used in the plasma processing step is 1000 to 2000 W.

In an embodiment of the invention, the pressure used in the plasma treatment step is from 500 mTorr to 1 Torr.

In an embodiment of the invention, the method for removing a portion of the first dielectric layer includes a dry etching process.

In an embodiment of the invention, the method for removing a portion of the first dielectric layer includes using a fluorine-containing mixed gas as an etching gas.

In an embodiment of the invention, before the heating step, the cleaning process of the damascene opening is further included.

In one embodiment of the invention, the cleaning process described above includes the use of a cleaning fluid comprising hydrofluoric acid.

In an embodiment of the invention, the cleaning solution comprises hydrofluoric acid in an amount of 25 to 1000 ppm, sulfuric acid in an amount of 3 to 10% by weight, and water.

In an embodiment of the present invention, after performing the cleaning process and before performing the heating step, the back cleaning process is further included.

In an embodiment of the invention, the back cleaning process is further performed prior to performing the heating step.

In an embodiment of the invention, after performing the plasma processing step, the back cleaning process is further included.

Based on the above, the semiconductor process of the present invention forms a damascene opening with a metal hard mask layer, and performs a heating step on the dielectric layer and a plasma processing step on the damascene opening to provide the metal damascene opening with the desired critical dimensions. In other words, the semiconductor process of the present invention can solve the problem of line width distortion encountered in forming a metal damascene opening with a metal hard mask layer, and avoiding defects such as subsequent metal backfilling, open window opening, and high resistance, thereby lifting the metal. Component characteristics and yield of the mosaic structure.

The above described features and advantages of the present invention will be more apparent from the following description.

1A through 1G are schematic cross-sectional views showing a semiconductor process in accordance with an embodiment of the present invention.

Referring to FIG. 1A, first, a substrate 100 is provided on which a patterned conductor layer 102 has been formed. The substrate 100 is, for example, a crucible substrate. The patterned conductor layer 102 is, for example, a wire in an interconnect process, such as a copper wire, which is formed in the dielectric layer 101. Next, a liner 104 is selectively formed on the substrate 100, and the material thereof is, for example, niobium oxynitride (SiCN).

A dielectric layer 106 is then formed over the substrate. The material of the dielectric layer 106 is, for example, a low dielectric constant material (dielectric constant k < 4), and the formation method of the dielectric layer 106 is, for example, a chemical vapor deposition method. Low dielectric constant materials include inorganic materials such as hydrogen silsesquioxane (HSQ), fluorinated silicate glass (FSG), etc., or organic materials such as polyarylene ethers. (fluorinated poly-(arylene ether), Flare), aromatic hydrocarbon (poly-(arylene ether), SILK), polyarylene ether (parylene), and the like. Next, a dielectric layer 108 is selectively formed on the dielectric layer 106. The material of the dielectric layer 108 is, for example, tetraethosiloxane (TEOS) cerium oxide.

A metal hard mask layer 110 is then formed over the dielectric layer 106. The material of the metal hard mask layer 110 is, for example, selected from the group consisting of titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, and combinations thereof, and is formed by, for example, chemical vapor deposition or sputtering. .

Referring to FIG. 1B, a patterned photoresist layer 112 having a trench pattern 112a is formed on the metal hard mask layer 110. Then, with the patterned photoresist layer 112 as a mask, a portion of the metal hard mask layer 110 is removed to form a patterned metal hard mask layer 110a.

Please refer to FIG. 1C, after which the patterned photoresist layer 112 is removed. Then, a patterned photoresist layer 116 having an opening pattern 116a is formed on the substrate 100. Then, with the patterned photoresist layer 116 as a mask, portions of the dielectric layers 106, 108 are removed to form openings 118. The method of removing portions of the dielectric layers 106, 108 is, for example, a dry etching process, such as using a fluorine-containing mixed gas as an etching gas.

Please refer to FIG. 1D, and then the patterned photoresist layer 116 is removed. Following The patterned hard mask layer 110a is used as a mask to remove portions of the dielectric layers 106, 108 and a portion of the liner 104 to form the trench 120 and the via opening 118a exposing the patterned conductor layer 102. . The via opening 118a and the trench 120 form a dual damascene opening 122, and the dual damascene opening 122 has a first critical dimension D1. The method of removing a portion of the dielectric layers 106, 108 and a portion of the liner 104 is, for example, a dry etching process, such as using a fluorine-containing mixed gas as an etching gas. In particular, the patterned metal hard mask layer 110a, the dielectric layer 108, the dielectric layer 106, and the liner layer 104 have stress variations and stress imbalances between the different material layers, so the double damascene The opening 122 is reduced or deformed by the influence of stress after formation, that is, the critical dimension D1 is smaller than the expected size. Furthermore, it should be noted that the method for forming the dual damascene opening described in this embodiment is only one of a plurality of methods for forming a double damascene opening using a metal hard mask layer, which is well known to those skilled in the art. The dual damascene openings are formed using a variety of known means. Moreover, in the present embodiment, a double damascene opening is taken as an example, but in other embodiments, the damascene opening may also be a single damascene opening, such as a contact window opening, a via opening or a trench.

Next, the dual damascene opening 122 is selectively subjected to a cleaning process to remove the polymer. In the present embodiment, the cleaning process is, for example, a wet etching process using a cleaning liquid containing hydrofluoric acid, wherein the cleaning liquid includes hydrofluoric acid in an amount of 25 to 1000 ppm, sulfuric acid in an amount of 3 to 10% by weight, and water.

Referring to FIG. 1E, a heating step 130 is then performed to heat the dielectric layer 106 to greater than 200 °C. In this embodiment, the heating step 130 is performed, for example, in a reaction chamber for performing a plasma etching process, so that the substrate 100, the patterned conductor layer 102, the dielectric layer 106, and the patterned metal hard mask layer 110a are both It is heated to 200 ° C ~ 350 ° C.

Referring to FIG. 1F, the dual damascene opening 122 is then subjected to a plasma processing step 140 such that the dual damascene opening 122 has a second critical dimension D2 that is greater than the first critical dimension D1, wherein the plasma generating gas includes hydrogen and blunt gas. In the present embodiment, the inert gas is, for example, helium gas, that is, a mixed gas including hydrogen gas and helium gas is used to generate the plasma. The ratio of hydrogen to light gas is, for example, 1:25 to 1:10, preferably 1:10. The flow rate of the generated gas is, for example, 5,000 sccm to 10,000 sccm, preferably 7,000 sccm. In the plasma treatment step, the pressure used is, for example, 500 mTorr to 1 Torr. Furthermore, in the plasma processing step, the microwave power source is used as the power source, and the power used is, for example, 1000 to 2000 W. In particular, in the present embodiment, since the molecular size of helium and hydrogen is close to each other and both are small molecular gases, the plasma generated by hydrogen and helium has the advantages of good conduction effect and high plasma temperature. , thereby improving the efficiency of the plasma processing step.

In this embodiment, after performing the cleaning process and before performing the heating step 130 or after the plasma processing step 140, the substrate may be selectively subjected to a backside clean process to remove residues remaining on the back surface of the substrate 100. Remaining. The backside cleaning process can be a conventional wafer backside cleaning process, such as a wafer backside cleaning process to remove residues such as copper.

Referring to FIG. 1G, a conductor layer 124 is then formed in the dual damascene opening 122 to fill the dual damascene opening 122. Conductor layer 124 typically includes a metal layer 126 and a barrier layer 128. Metal layer 126 is, for example, a copper metal layer. The material of the barrier layer 128 may be titanium nitride or tantalum nitride. In this embodiment, the method of forming the conductive layer 124 is, for example, first forming a barrier material layer (not shown) filled with the double damascene opening 122 and a metal material layer (not shown) on the substrate 100, and then A chemical mechanical polishing method or the like removes the barrier material layer, the metal material layer, the dielectric layer 108, and the patterned metal hard mask layer 110a outside the double damascene opening 122. The formed conductor layer 124 is a dual damascene structure including a wire 124a and a via 124b. Of course, those skilled in the art will appreciate that other known ways can be used to form the conductor layer.

In this embodiment, the semiconductor process includes forming a double damascene opening with a metal hard mask layer, performing a cleaning process on the double damascene opening, heating the dielectric layer, and performing a plasma processing step on the double damascene opening, The substrate is subjected to a backside cleaning process and a conductor layer is formed in the dual damascene opening. In general, in the process of forming a double damascene opening using a metal hard mask layer, there are stress variations and stress imbalances between a plurality of different material layers such as a metal hard mask layer, a dielectric layer, and a liner layer. As a result, the double damascene opening is reduced or deformed by stress after formation, making the critical dimension smaller than expected, and the problem of wide line distortion, and the subsequent metal backfilling is not easy, the via window is broken, and the resistance value is over. Higher defects. However, in this embodiment, after the double damascene opening is formed by the metal hard mask layer, the plasma generated by the hydrogen gas and the blunt gas is used to treat the double damascene opening, so that the double damascene opening can be enlarged, so that the double damascene opening can be opened. The critical dimensions are closer to the expected size to avoid these problems. In addition, the plasma treatment step also removes residues from the bottom of the double damascene opening to avoid possible defects caused by the residue. In other words, the semiconductor process of the present embodiment can solve the problems of line width distortion, via window breaking, and high resistance encountered in forming a double damascene opening by a metal hard mask layer, thereby greatly improving the component characteristics of the dual damascene structure. Yield.

In summary, the semiconductor process of the present invention forms a damascene opening with a metal hard mask layer, and performs a heating step on the dielectric layer and a plasma processing step on the damascene opening to make the metal damascene opening have the desired critical dimensions. . That is to say, when a metal hard mask layer is used to form a damascene opening, stress between a plurality of different material layers such as a metal hard mask layer, a dielectric layer, a liner layer, etc., may cause the damascene opening to shrink after being formed. Or deformed so that the critical dimensions are smaller than expected. The semiconductor process of the present invention can solve the above-mentioned line width distortion and the resulting open window and high resistance of the via to improve the component characteristics and yield of the damascene structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Base

101. . . Dielectric layer

102. . . Patterned conductor layer

104. . . lining

106. . . Dielectric layer

108. . . Dielectric layer

110. . . Metal hard mask

110a. . . Patterned metal hard mask

112. . . Patterned photoresist layer

112a. . . Ditch pattern

116. . . Patterned photoresist layer

116a. . . Opening pattern

118. . . Opening

118a. . . Via window opening

120. . . ditch

122. . . Double metal inlay opening

124. . . Conductor layer

124a. . . wire

124b. . . Via window

126. . . Metal layer

128. . . Barrier layer

130. . . Heating step

140. . . Plasma processing step

D1, D2. . . Key size

1A through 1G are schematic cross-sectional views showing a semiconductor process in accordance with an embodiment of the present invention.

100. . . Base

101. . . Dielectric layer

102. . . Patterned conductor layer

104. . . lining

106. . . Dielectric layer

108. . . Dielectric layer

110a. . . Patterned metal hard mask

118a. . . Via window opening

120. . . ditch

122. . . Double metal inlay opening

140. . . Plasma processing step

D2. . . Key size

Claims (22)

A semiconductor process includes: providing a substrate having a patterned conductor layer, a first dielectric layer, and a patterned metal hard mask layer sequentially formed on the substrate; removing a portion of the first dielectric layer Forming a damascene opening exposing the patterned conductor layer; performing a heating step to heat the first dielectric layer to greater than 200 ° C after forming the damascene opening; performing a plasma on the damascene opening a processing step, wherein the plasma generating gas comprises hydrogen gas and an inert gas; and forming a conductor layer in the damascene opening to fill the damascene opening. The semiconductor process of claim 1, wherein the damascene opening is a double damascene opening. The semiconductor process of claim 1, wherein the damascene opening has a first critical dimension prior to performing the plasma processing step, and having a greater than the first critical dimension after performing the plasma processing step A second key size. The semiconductor process of claim 1, wherein the molecular size of the blunt gas is similar to the molecular size of hydrogen. The semiconductor process of claim 1, wherein the blunt gas comprises helium. The semiconductor process of claim 1, wherein the heating step heats the first dielectric layer to between 200 ° C and 350 ° C. The semiconductor process of claim 1, wherein in the plasma processing step, the microwave power source is used as a power source. The semiconductor process of claim 1, wherein the second dielectric layer further comprises a second dielectric layer between the first dielectric layer and the patterned metal hard mask layer. The semiconductor process of claim 1, wherein the patterned conductor layer and the first dielectric layer further comprise a liner. The semiconductor process of claim 9, wherein the step of removing a portion of the first dielectric layer further comprises removing a portion of the liner. The semiconductor process of claim 1, wherein the ratio of hydrogen to blunt gas in the generated gas is from 1:25 to 1:10. The semiconductor process of claim 1, wherein the flow rate of the generated gas is from 5,000 sccm to 10,000 sccm. The semiconductor process of claim 1, wherein the power used in the plasma processing step is 1000 to 2000 W. The semiconductor process of claim 1, wherein in the plasma processing step, the pressure used is from 500 mTorr to 1 Torr. The semiconductor process of claim 1, wherein the method of removing a portion of the first dielectric layer comprises a dry etching process. The semiconductor process of claim 15, wherein the method of removing a portion of the first dielectric layer comprises using a fluorine-containing mixed gas as an etching gas. The semiconductor process of claim 1, further comprising: cleaning the damascene opening before performing the heating step Process. The semiconductor process of claim 17, wherein the cleaning process comprises using a cleaning solution comprising hydrofluoric acid. The semiconductor process of claim 18, wherein the cleaning solution comprises hydrofluoric acid in an amount of 25 to 1000 ppm, sulfuric acid in an amount of 3 to 10% by weight, and water. The semiconductor process of claim 17, wherein after performing the cleaning process and before performing the heating step, a back cleaning process is further included. The semiconductor process as described in claim 1 further includes performing a backside cleaning process prior to performing the heating step. For example, in the semiconductor process described in claim 1, after performing the plasma processing step, a back cleaning process is further included.