TWI599050B - Thin film transistor and method of manufacturing the same - Google Patents

Description

Thin film transistor and manufacturing method thereof

The invention relates to a thin film transistor and a method of fabricating the same.

Thin film transistors are used in active displays, typically as switches that charge or discharge storage capacitors. The thin film transistor is formed on a glass substrate and includes a gate, a gate insulating layer, a channel layer, a source, and a drain. The gate is used to open or close the electron channel in the channel layer. The gate insulating layer covers the gate to avoid electrical contact between the gate and the channel layer. The channel layer is located on the gate insulating layer and provides a channel for electron transport. The source and the drain are both disposed on the channel layer to be respectively connected to the data line and the pixel electrode of the display.

When a voltage is applied to the gate of the thin film transistor, an electron channel is formed at the bottom of the channel layer, and when a voltage is applied to the drain, electrons flow from the source through the electron channel of the channel layer to the drain, causing the source to A path is formed between the bungee poles. When the application of voltage to the gate is stopped, the thin film transistor is turned off, and the electron channel at the bottom of the channel layer disappears, causing an open circuit between the source and the drain.

However, current thin film transistors have a leakage current phenomenon. When a voltage is not applied to the gate or a negative voltage is applied, a leakage path is generated on the surface of the channel layer between the source and the drain, thereby forming a leakage current. The generation of leakage current will cause deterioration of the electrical characteristics of the thin film transistor, and ultimately affect the display quality of the liquid crystal display, which is a phenomenon to be overcome.

In view of the above, it is necessary to provide a thin film transistor for reducing leakage current, the thin film transistor including a gate, a gate insulating layer, an intrinsic amorphous germanium layer, an n-type amorphous germanium layer, Source and bungee. The gate insulating layer is disposed between the gate and the intrinsic amorphous germanium layer. The intrinsic amorphous germanium layer includes a doped region and a non-doped region. The n-type amorphous germanium layer is on the surface of the undoped region. The source and the drain are respectively located on both sides of the intrinsic amorphous germanium and are in contact with the n-type amorphous germanium layer and the doped region and are disposed apart from each other.

It is also necessary to provide a method of fabricating a thin film transistor by which a thin film transistor having a small leakage current can be manufactured.

The method includes the steps of: providing a substrate, and sequentially forming a gate and a gate insulating layer on the substrate, the gate insulating layer covering the gate; forming an intrinsic amorphous germanium layer on the gate insulating layer in turn An n-type amorphous germanium layer; doping treatment on opposite sides of the intrinsic amorphous germanium layer not covered by the n-type amorphous germanium layer to form a doped region; and in the n-type amorphous germanium layer And forming a source and a drain on the doped region, and removing the n-type amorphous germanium layer and a portion of the intrinsic amorphous germanium layer between the source and the drain.

Compared with the prior art, the thin film transistor provided by the present invention and the manufacturing method thereof can reduce the electron mobility due to the presence of the n-type amorphous germanium layer and the doped region, so that when the thin film transistor is in a closed state When it is possible, the leakage current can be effectively reduced, thereby improving electrical characteristics. In addition, since the doped region is formed by directly performing doping treatment on the opposite sides of the intrinsic amorphous germanium layer, the fabrication process is simple, and the process cost is saved.

100‧‧‧film transistor

110‧‧‧ gate

120‧‧‧ gate insulation

130‧‧‧ intrinsic amorphous layer

131‧‧‧Undoped areas

132‧‧‧Doped area

133‧‧‧First semiconductor layer

140‧‧‧n type amorphous layer

141‧‧‧Second semiconductor layer

150‧‧‧Second metal layer

151‧‧‧ source

152‧‧‧汲polar

161‧‧‧First photoresist layer pattern

170‧‧‧second photoresist layer

171‧‧‧Second photoresist layer pattern

200‧‧‧Base

1 is a cross-sectional view showing a structure of a thin film transistor manufactured by a method for fabricating a thin film transistor according to a first preferred embodiment of the present invention; FIG. 2 is a flow chart showing a method for fabricating a thin film transistor of FIG. 1; FIG. 11 is a cross-sectional view showing a method of fabricating a thin film transistor according to another preferred embodiment of the present invention; and FIGS. 12 to 19 are cross-sectional views showing the flow of each step in FIG.

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein the present invention is described by taking a bottom gate type thin film transistor as an example.

1 is a cross-sectional view showing the structure of a thin film transistor 100 manufactured by a method of fabricating a thin film transistor 100 according to a first preferred embodiment of the present invention. The thin film transistor 100 is formed on a substrate 200. The thin film transistor 100 includes a gate 110, a gate insulating layer 120, an intrinsic amorphous germanium layer 130, an n-type amorphous germanium layer 140, a source 151, and a drain 152. The gate 110 is located on the substrate 200. The gate insulating layer 120 is located on a side of the gate 110 away from the substrate 200 and covers the gate 110. The intrinsic amorphous germanium layer 130 is disposed on the gate insulating layer 120 and located at a position corresponding to the gate 110. The width of the intrinsic amorphous germanium layer 130 is less than or equal to the width of the gate. A gate insulating layer 120 is used to separate the gate 110 from the intrinsic amorphous germanium layer 130. The n-type amorphous germanium layer 140 is on the intrinsic amorphous germanium layer 130 and partially covers the intrinsic amorphous germanium layer 130. The source 151 and the drain 152 are formed on a side of the gate insulating layer 120, the intrinsic amorphous germanium layer 130, and the n-type amorphous germanium layer 140 away from the gate 110, and The source 151 and the drain 152 are disposed apart from each other. The intrinsic amorphous germanium layer 130 is partially exposed between the source 151 and the drain 152.

The intrinsic amorphous germanium layer 130 has a trapezoidal structure including an undoped region 131 and a doped region 132, wherein the doped region 132 is subjected to phosphorus doping treatment on two opposite sides of the intrinsic amorphous germanium layer 130. Or formed after the boron doping treatment, the thickness of the doped region 132 is equal to the thickness of the n-type amorphous germanium layer 140. The undoped region 131 is formed on a top surface of the intrinsic amorphous germanium layer 130. The n-type amorphous germanium layer 140 is disposed on the undoped region 131 and covers both ends of the undoped region 131. The n-type amorphous germanium layer 140 and the doped region 132 are respectively covered by the source electrode 151 and the drain electrode 152. The n-type amorphous germanium layer 140 and the doped region 132 function to reduce the contact resistance between the intrinsic amorphous germanium layer 130 and the source electrode 151 and the drain electrode 152. In the off state, that is, when no voltage is applied to the gate 110 or a negative voltage is applied, the leakage current can be effectively reduced.

Please refer to FIG. 2. FIG. 2 is a flow chart of a method for fabricating the thin film transistor 100 of FIG. The method comprises the following steps:

Step S201, referring to FIG. 3, the substrate 200 is provided, and the gate 110 and the gate insulating layer 120 are sequentially formed on the substrate 200, so that the gate insulating layer 120 covers the gate 110. on. Specifically, a first metal layer is first formed on the substrate 200, and then the first metal layer is patterned into the gate 110 by a dry etching process, and the gate insulation is formed by plasma chemical vapor deposition. Layer 120.

The material of the substrate 200 may be selected from glass, quartz, organic polymers or other suitable transparent materials. The material of the gate 110 is metal or other conductive material, such as an alloy, a metal oxide, a metal nitride or a metal oxynitride. The material of the gate insulating layer 120 may be selected from inorganic materials (such as yttria, lanthanum boride, lanthanum boride, etc.), organic materials or other applicable materials, and combinations thereof.

Step S202, referring to FIG. 4, after the gate insulating layer 120 is completed, the first semiconductor layer 133 and the second semiconductor layer 141 are sequentially formed on the gate insulating layer 120. The material of the first semiconductor layer 133 is an intrinsic amorphous germanium, and the material of the second semiconductor layer 141 is an n-type amorphous germanium.

Step S203, referring to FIG. 5, forming a first photoresist layer (not shown) on the second semiconductor layer 141, and patterning the first photoresist layer to form a first photoresist layer pattern 160, the first The photoresist layer pattern 160 is positioned opposite the gate 110. The second semiconductor layer 141 and the first semiconductor layer 133 not covered by the first photoresist layer pattern 160 are etched by a dry etching process to form the n-type amorphous germanium layer 140 on the second semiconductor layer 141. The intrinsic amorphous germanium layer 130 is formed on the first semiconductor layer 133, wherein the opposite sides of the intrinsic amorphous germanium layer 130 are not covered by the n-type amorphous germanium layer 140.

Step S204, referring to FIG. 6, the two opposite sides of the exposed intrinsic amorphous germanium layer 130 are doped to form the doped region 132. In this embodiment, phosphorus doping is performed by means of ion implantation, and the thickness of the doped phosphorus is equivalent to the thickness of the n-type amorphous germanium layer 140. Of course, it may be slightly thicker or slightly thinner than the n-type amorphous germanium layer 140. In other embodiments, the doped species is not limited to phosphorus, but may be boron or other materials. Regardless of which substance is doped, the doping method is not limited to the ion implantation method, and may be a plasma treatment method. And so on. Since the doped region 132 is formed by directly performing doping treatment on two opposite sides of the intrinsic amorphous germanium layer 130, the fabrication process is simple, and the process cost is saved.

Step S205, referring to FIG. 7, after the doping process is completed, the first photoresist layer pattern 160 is removed. Wherein, the first photoresist layer is a positive photoresist, and the portion irradiated with the light is soluble in the photoresist developer, and the portion not irradiated with the light is not dissolved in the photoresist developer. In other embodiments, The first photoresist layer may also use a negative photoresist having opposite characteristics.

Step S206, referring to FIG. 8, after the first photoresist layer pattern 160 is removed, a surface covering the gate insulating layer 120, the n-type amorphous germanium layer 140, and the doped region 132 is formed on the substrate 200. A second metal layer 150 is formed on the second metal layer 150 to form a second photoresist layer 170. The second metal layer 150 is in contact with the n-type amorphous germanium layer 140, the doped region 132, and the gate insulating layer 120 exposed on both sides of the intrinsic amorphous germanium layer 130. The material of the second metal layer 150 is metal or other conductive material, such as an alloy, a metal oxide, a metal nitride or a metal oxynitride. In the present embodiment, the second photoresist layer 170 is a positive photoresist, and a portion irradiated with the light can be dissolved in the photoresist developing solution, and a portion not irradiated with the light is not dissolved in the photoresist developing solution. In other embodiments, the second photoresist layer 170 may also use a negative photoresist having opposite characteristics.

Step S207, referring to FIG. 9, patterning the second photoresist layer 170 to form a second photoresist pattern 171, the second photoresist layer pattern 171 covering the two sides of the second metal layer 150, and The second metal layer 150 corresponding to the intermediate portion of the amorphous germanium layer 140 is exposed.

Step S208, referring to FIG. 10, etching the second metal layer 150 not covered by the second photoresist layer pattern 171 to form the source electrode 151 and the drain electrode 152 while etching away the source electrode 151 and The n-type amorphous germanium layer 140 and the partially intrinsic amorphous germanium layer 130 between the drain electrodes 152 finally remove the second photoresist layer pattern 171. Thus far, the thin film transistor substrate 100 is completed.

Please refer to FIG. 11. FIG. 11 is a flow chart of a method for fabricating a thin film transistor 100 according to another preferred embodiment of the present invention. The method comprises the following steps:

Step S1101, referring to FIG. 12, the substrate 200 is provided, and the gate 110 and the gate insulating layer 120 are sequentially formed on the substrate 200, so that the gate insulating layer 120 covers the gate 110. on. Specifically, a first metal layer is first formed on the substrate 200, The first metal layer is then patterned into the gate 110 by a dry etching process, and the gate insulating layer 120 is formed by plasma chemical vapor deposition.

The material of the substrate 200 may be selected from glass, quartz, organic polymers or other suitable transparent materials. The material of the gate 110 is metal or other conductive material, such as an alloy, a metal oxide, a metal nitride or a metal oxynitride. The material of the gate insulating layer 120 may be selected from inorganic materials (such as yttria, lanthanum boride, lanthanum boride, etc.), organic materials or other applicable materials, and combinations thereof.

Step S1102, referring to FIG. 13, after the gate insulating layer 120 is completed, the first semiconductor layer 133 and the second semiconductor layer 141 are sequentially formed on the gate insulating layer 120. The material of the first semiconductor layer 133 is an intrinsic amorphous germanium, and the material of the second semiconductor layer 141 is an n-type amorphous germanium.

Step S1103, referring to FIG. 14, forming a first photoresist layer (not shown) on the second semiconductor layer 141, and patterning the first photoresist layer to form a first photoresist layer pattern 160, the first The photoresist layer pattern 160 is positioned opposite the gate 110. The second semiconductor layer 141 and the first semiconductor layer 133 not covered by the first photoresist layer pattern 160 are etched by a dry etching process to form the n-type amorphous germanium layer 140 on the second semiconductor layer 141. The intrinsic amorphous germanium layer 130 is formed on the first semiconductor layer 133. The two opposite sides of the intrinsic amorphous germanium layer 130 are not covered by the n-type amorphous germanium layer 140. The first photoresist layer is a positive photoresist, and a portion irradiated with the light is soluble in the photoresist developer, and a portion not irradiated with the light is not dissolved in the photoresist developer. In other embodiments, the A negative photoresist having opposite characteristics can also be used for the first photoresist layer.

In step S1104, referring to FIG. 15, the first photoresist layer pattern 160 is removed, and the doped region 132 and the n-type amorphous germanium layer 140 are exposed.

Step S1105, referring to FIG. 16, doping the two opposite sides of the intrinsic amorphous germanium layer 130 and the n-type amorphous germanium layer 140, and the opposite sides of the intrinsic amorphous germanium layer 130. The doped region 132 is formed after the doping treatment. The n-type amorphous germanium layer 140 is also doped without the occlusion of the first photoresist layer pattern 160, and also helps to reduce the intrinsic amorphous germanium layer 130 and the source 151 and the germanium. The contact impedance between the poles 152, thereby reducing leakage current. In this embodiment, the phosphorus doping treatment is performed by means of ion implantation. In other embodiments, the doped material is not limited to phosphorus, and may be boron. Or other substances. Regardless of which substance is doped, the doping method is not limited to the ion implantation method, and may be a plasma treatment method or the like. Since the doped region 132 of the present invention is formed by directly performing doping treatment on the doped region 132 of the intrinsic amorphous germanium layer 130, the fabrication process is simple, and the process cost is saved.

Step S1106, referring to FIG. 17, after the first photoresist layer pattern 160 is removed, a surface covering the gate insulating layer 120, the n-type amorphous germanium layer 140, and the doped region 132 is formed on the substrate 200. A second metal layer 150 is formed on the second metal layer 150 to form a second photoresist layer 170. The second metal layer 150 is in contact with the n-type amorphous germanium layer 140, the doped region 132, and the gate insulating layer 120 exposed on both sides of the intrinsic amorphous germanium layer 130. The material of the second metal layer 150 is metal or other conductive material, such as an alloy, a metal oxide, a metal nitride or a metal oxynitride. In the present embodiment, the second photoresist layer 170 is a positive photoresist, and a portion irradiated with the light can be dissolved in the photoresist developing solution, and a portion not irradiated with the light is not dissolved in the photoresist developing solution. In other embodiments, the second photoresist layer 170 may also use a negative photoresist having opposite characteristics.

Step S1107, referring to FIG. 18, patterning the second photoresist layer 170 to form a second photoresist pattern 171, the second photoresist layer pattern 171 covering the two sides of the second metal layer 150, and The second metal layer 150 corresponding to the intermediate portion of the amorphous germanium layer 140 is exposed.

Step S1108, referring to FIG. 19, etching the second metal layer 150 not covered by the second photoresist layer pattern 171 to form the source electrode 151 and the drain electrode 152 while etching away the source electrode 151 and The n-type amorphous germanium layer 140 and the partially intrinsic amorphous germanium layer 130 between the drain electrodes 152 finally remove the second photoresist layer pattern 171. Thus far, the thin film transistor substrate 100 is completed.

In summary, the creation meets the requirements of the invention patent, and the patent application is filed according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiments, and those skilled in the art will be equivalently modified or changed according to the spirit of the present invention. It should be covered by the following patent application.

100‧‧‧film transistor

110‧‧‧ gate

120‧‧‧ gate insulation

130‧‧‧ intrinsic amorphous layer

131‧‧‧Undoped areas

132‧‧‧Doped area

140‧‧‧n type amorphous layer

151‧‧‧ source

152‧‧‧汲polar

Claims (11)

A thin film transistor comprising a gate, a gate insulating layer, an intrinsic amorphous germanium layer, an n-type amorphous germanium layer, a source and a drain; the gate insulating layer is disposed on the gate and the gate The intrinsic amorphous germanium layer has a trapezoidal structure; the intrinsic amorphous germanium layer includes a doped region and an undoped region; the n-type amorphous germanium layer is located on the surface of the undoped region The source and the drain are respectively located on both sides of the intrinsic amorphous germanium and are in contact with the n-type amorphous germanium layer and the doped region and are disposed apart from each other. The thin film transistor according to claim 1, wherein the gate insulating layer covers the gate, and the intrinsic amorphous germanium layer is disposed at a position corresponding to the gate, and the n-type amorphous germanium layer is located The non-doped region is away from one side of the gate and covers both ends of the undoped region, and the source and the drain are formed on the gate insulating layer, the intrinsic amorphous germanium layer and the n-type amorphous germanium layer And covering the gate insulating layer, the doped region and the n-type amorphous germanium layer. The thin film transistor according to claim 1, wherein the doped region is doped with phosphorus or boron. The thin film transistor according to claim 1, wherein the opposite sides of the intrinsic amorphous germanium layer are doped to form the doped region. The thin film transistor according to claim 1, wherein the doping treatment method comprises an ion implantation method or a plasma treatment method. The thin film transistor according to claim 1, wherein the thickness of the doped region is equivalent to the thickness of the n-type amorphous germanium layer. A method for fabricating a thin film transistor, the method comprising the steps of: providing a substrate, and sequentially forming a gate and a gate insulating layer on the substrate, the gate insulating layer covering the gate; and sequentially on the gate insulating layer Forming an intrinsic amorphous germanium layer and an n-type amorphous germanium layer; doping treatment on opposite sides of the intrinsic amorphous germanium layer not covered by the n-type amorphous germanium layer to form a doped region; Forming a source and a drain on the n-type amorphous germanium layer and the doped region, and removing the n-type amorphous germanium layer and a portion of the intrinsic amorphous germanium layer between the source and the drain . The method of fabricating a thin film transistor according to claim 7, wherein the method of forming the doped region comprises: sequentially forming a first semiconductor layer and a second semiconductor layer on the gate insulating layer; and forming the second conductive layer on the gate insulating layer Forming a first photoresist layer thereon and patterning the first photoresist layer to form a first photoresist layer pattern; etching the first semiconductor layer and the second semiconductor layer not covered by the first photoresist layer pattern Forming the intrinsic amorphous germanium layer and the n-type amorphous germanium layer, respectively; doping treatment on the opposite sides of the intrinsic amorphous germanium layer to form the doped region; and removing the first photoresist Layer pattern. The method of fabricating a thin film transistor according to claim 7, wherein the method of forming the doped region comprises: sequentially forming a first semiconductor layer and a second semiconductor layer on the gate insulating layer; and forming the second conductive layer on the gate insulating layer Forming and patterning the first photoresist layer to form a first photoresist layer pattern; etching the first semiconductor layer and the second semiconductor layer not covered by the first photoresist layer pattern to respectively form the An intrinsic amorphous germanium layer and the n-type amorphous germanium layer; removing the first photoresist layer pattern; and doping the opposite sides of the intrinsic amorphous germanium layer and the n-type amorphous germanium layer, The doped regions are formed on the opposite sides of the doped amorphous indium layer. The method of fabricating a thin film transistor according to any one of claims 8 to 9, wherein the doping treatment comprises a phosphorus doping treatment or a boron doping treatment. The method of fabricating a thin film transistor according to claim 7, wherein the doping treatment method comprises an ion implantation method or a plasma treatment method.