TWI588939B - A silicon through hole etching method - Google Patents

Description

Tantalum through hole etching method

The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a deep via etching method.

In recent years, computers, communications, automotive electronics, aerospace and other consumer products have placed higher demands on microelectronic packaging, namely smaller, thinner, lighter, more reliable, versatile, and low power. At low cost, many vertical interconnect vias are needed to realize electrical interconnection between different wafers. The via via etching process has gradually become an important technology in the field of micro-nano processing. With the increasing use of microelectromechanical systems and microelectromechanical systems (MEMS) in automotive and electricity electronics, TSV (Through Silicon Via) via etching technology is widely used in the future packaging field. In the future, the deep etching process has gradually become one of the most sought-after processes in the field of MEMS manufacturing and TSV technology.

The 矽 via etch process is a deep etch process using plasma etching. The main difference is that the etch depth is much larger than the general 矽 etch process compared to the general 矽 etch process. A typical tantalum etching process typically has an etch depth of less than 1 micrometer (μm), while a deep etch process has an etch depth of tens of microns or even hundreds of microns, with a large aspect ratio. Therefore, in order to obtain a good deep hole morphology, it is necessary to etch the removal depth to several tens or even hundreds of micrometers. Tantalum materials require a deep etch process with faster etch rates, higher selectivity ratios, and greater aspect ratios. The stencil etching process is also widely used in SOI (silicon on insulator) structures. The etch etch process requires etching down a certain depth from the mask layer, such as greater than 10 μm, or 40-100 μm until the bottom insulating layer is exposed. As shown in FIG. 2, a typical structural view formed when an SOI material layer is etched by a deep etch process is shown. The bottom of the material layer 1 to be etched in FIG. 2 comprises a layer 3 of insulating material, the top comprising a mask layer 2, which comprises a patterned opening. The material layer to be etched is a crystal ruthenium, and the mask layer may be ruthenium oxide or other material which can serve as a mask. The bottom insulating material layer 3 may be other insulating materials such as yttrium oxide or tantalum nitride or an organic polymer. During the plasma etching process, a large amount of electrons accumulate on the top of the mask layer to form a negatively charged sheath layer, and the incident part of the positively charged ions are also adsorbed on the sidewall of the etched via hole. Since the bottom layer is an insulating material layer, these charges cannot be effectively guided. Walking will gradually accumulate as the plasma treatment continues. In the case where the negative charge distribution on the surface of the mask layer is not uniform enough or the positive charge distribution on the sidewall of the etched via is not uniform, the positive ions incident from the upper plasma are affected by these asymmetric electric fields and deviate from the direction of the original normal incidence. The track will tilt. The inclination of this incident trajectory is most pronounced in the bottom region of the through hole. The obliquely incident ions will hit the bottom sidewall to form the notch 4. These notches need to be eliminated, otherwise the device performance will be seriously affected when the final processing is completed. . The prior art proposes a pulsed bias RF power supply as shown in FIG. 3, and the RF power applied to the lower electrode includes a high power phase A and a low power phase B, wherein the low power phase may be a zero power output or a turn off power. The output can also be a power output that is well below the high power output value. The application of this high-low switching pulse-shaped power output method can significantly reduce the occurrence of Notch phenomenon, but after this method, although the notch is significantly reduced, it still exists partially.

So the industry needs a new etching method that completely eliminates these via holes. The notch of the side wall ensures that the etching rate is not lowered.

The problem to be solved by the present invention is to provide a method for etching a via hole, comprising: placing a substrate to be processed onto a susceptor in a reaction chamber, the substrate to be processed comprising a layer of insulating material and a layer of germanium material above the layer of insulating material a patterned mask layer opening is further disposed above the germanium material layer; a reactive gas is introduced into the reaction chamber, and source RF power is applied into the reaction chamber to form a plasma, which is etched downward from the patterned mask layer opening. Forming a via hole; biasing RF power to the pedestal through a bias RF power source for adjusting energy incident on the substrate by ions in the plasma; wherein the bias RF power is included in at least one stage In pulsed mode, the output power is switched between a high power output step and a low power output step, the duty cycle of the biased RF power pulse being less than 10%. Preferably, the bias RF power pulse duty cycle is less than 5% to completely eliminate the recess of the sidewall of the etched via.

Wherein the substrate to be processed is etched down from the patterned mask layer opening to the bottom insulating material layer, wherein the through hole depth from the opening to the bottom insulating material layer is greater than 10 μm.

The via via etch includes a first etch phase, etched down from the mask layer opening to a first depth, the duty cycle of the biased RF power pulse is greater than 10%; and the second etch phase is entered after completing the first etch phase A downward etch, from the first depth etch to the bottom insulating material layer, biases the duty cycle of the RF power pulse to less than 10%. This avoids the occurrence of etched sidewall sidewall recesses while ensuring the etch rate of the first etch phase. Wherein the first depth is greater than 2/3 of the depth of the entire through hole.

High power output step in which the RF power pulse is biased during the first etch phase The first power is outputted, and the high power output step of biasing the RF power pulse in the second etching phase outputs a second power, the first power, the first power, and the second power. This ensures a sufficient etch rate even in the ultra-low duty cycle etch phase.

The method further includes a matching frequency obtaining step of setting an output power of the biased RF power source to switch between a high power output step and a low power output step, and adjusting an output frequency of the biased RF power source to obtain a matching Determining a plurality of matching frequencies of the high power output step and the first power output step, wherein an output frequency of the biased RF power source is between the plurality of matching frequencies during etching down from the patterned mask layer opening to form the through hole Switch. This ensures that impedance matching can be effectively achieved even at very low duty cycles, and RF power can be fed into the reaction chamber in a very short power output step to form a stable plasma.

The bias RF power source includes an RF power generator and a built-in pulse signal source, and further includes an external pulse signal source, and a switch switch selectively connects the output signal of the built-in pulse signal source or the external pulse signal source to The radio frequency power generator. The duty ratio of the built-in pulse signal source output pulse signal is between 10% and 100%, and the duty ratio of the output pulse signal of the external pulse signal source is between 0.1% and 10%. The present invention is specifically designed to optimize the pulse signal generating mechanism to meet special needs, and to more efficiently switch between the ultra-low duty cycle etching mode of the present invention and the normal duty cycle etching mode.

1‧‧‧ layer of material to be etched

2‧‧‧ mask layer

3‧‧‧Insulation layer

4‧‧‧ notch

100‧‧‧plasma reaction chamber

105‧‧‧Adjustment ring

110‧‧‧ gas source

120‧‧‧Base

121‧‧‧Electrostatic chuck

122‧‧‧Substrate

130‧‧‧Pneumatic valve

40‧‧‧Bad RF power supply

41‧‧‧ Output

42‧‧‧ Built-in pulse signal source

44‧‧‧External pulse signal source

46‧‧‧Selection switch

48‧‧‧Low frequency RF power supply

50‧‧‧Matching circuit

A‧‧‧High power output stage

B‧‧‧Low power output stage

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic view showing the structure of a plasma etching apparatus of the present invention.

2 is a structural view of a prior art stencil etching process for etching an SOI material layer.

3 is a schematic diagram of output power of a prior art bias RF power supply.

4 is a schematic diagram of the output power of the bias RF power supply of the present invention.

Figure 5 is a structural diagram of a bias RF power supply of the present invention.

Please refer to FIG. 1 for the structure of the plasma etching apparatus of the present invention. The plasma etching apparatus of the present invention includes a plasma reaction chamber 100. The reaction chamber 100 includes a susceptor 120 therein, and the susceptor 120 includes a lower electrode therein. An electrostatic chuck 121 is fixed on the top of the base 120. The electrostatic chuck 121 is provided with a substrate 122 to be processed. An adjusting ring 105 surrounds the electrostatic chuck 121 or the periphery of the substrate 122, and passes through the material, shape and size of the adjusting ring 105. The design can improve the electric field distribution in the edge region of the substrate 122 to achieve an improvement in etching uniformity. The top of the reaction chamber 100 includes an insulating window made of an insulating material to achieve a seal against the top of the reaction chamber 100. The insulating window includes at least one set of inductor coils connected to a high frequency RF power source for forming and maintaining a high concentration of plasma, and the high frequency power source outputs 13 Mhz of RF energy into the reaction chamber 100. The top of the reaction chamber 100 further includes a reaction gas nozzle connected to the gas source 110 through a pipe and a valve. In addition to the gas supply structure shown in FIG. 1, the actual etching may include a plurality of reaction gas sources (SF6, C4F8, Ar). The reaction gas is supplied to the reaction chamber 100 through the valve network, or the reaction gas is directly discharged through the valve network to the exhaust pipe downstream of the gas pressure valve 130 through the valve network when the reaction gas does not need to be introduced into the reaction chamber 100. A bias RF power source 40 is connected by wires to a matching circuit 50, within the matching circuit 50 With variable impedance, the RF energy adjusted by the matching circuit 50 is output to the lower electrode of the susceptor 120, and the amount of energy of the plasma incident on the surface of the substrate 122 is adjusted by adjusting the power of the bias RF power source 40. The present invention can be applied not only to the inductively coupled plasma reactor (ICP) shown in FIG. 1, but also to a capacitively coupled plasma reactor (CCP). The selection of these reactor types is well known in the art, and will not be described herein. .

The prior art shown in FIG. 3 uses a conventional pulse-type RF power supply to output to the lower electrode, and its duty ratio (English: Duty Ratio, in this embodiment, the A-stage duration accounts for the entire processing step A+B time length ratio Generally, 10-90% is selected, and some documents also record 5%-95%. However, in actual use, the duty cycle of the power output pulse of the bias RF power source is not less than 10%. Because the traditionally considered that the smaller the duty cycle, the lower the input power, the lower the etch rate, and because the time of the high power output phase A is very short, entering the low power output phase B immediately will cause the plasma to go out or turn to the low power output. The instability of the plasma state in segment B increases the difficulty of adjusting the plasma processing parameters. The output power of the RF power supply is adjusted to be relatively stable by adjusting the pulse. Therefore, the prior art generally selects the duty ratio in the range of 10%-90% when the Notch phenomenon is eliminated, and further improves by adjusting the output power or the pulse frequency. Due to this technical reason, the commercially available pulsed RF power supply available in the existing market has an optional duty cycle of 10% to 90%. To exceed this range, the plasma etching device manufacturer needs to modify it.

The inventors have found that the use of an ultra-low duty cycle, such as less than 5%, at other output powers or pulse frequencies, causes the Notch phenomenon that occurs in the prior art to substantially disappear. The sidewalls have substantially no significant recesses from the opening to the bottom insulating material layer 4. However, the original problem of ultra-low duty cycle cannot be quickly matched, causing plasma instability, and is also disclosed by other applicants in earlier applications: CN201210393470.x and CN201210458267.6. solved. In the patents filed by the applicant, a matching frequency acquisition step is set, in which a plurality of impedance states appearing in the matching frequency acquisition step analogously to the subsequent pulse switching, by adjusting the output frequency of the RF power source, The plurality of analog impedance states that are matched by the plurality of analog states are stored, and the adjusted impedance is quickly matched by the adjusted plurality of specific frequencies when the pulsed output power is subsequently switched. After adopting this method, since the frequency setting belongs to the parameter setting of the electric signal, it can be realized almost instantaneously, and no mechanical device is needed to adjust the variable capacitance or the variable inductance, so that the pulsed RF power supply can be matched at the duty ratio. Impedance at very low (less than 5% as selected by the present invention).

FIG. 4 is a schematic diagram of a pulsed RF power output of the bias RF power supply 40 of the present invention. Since a very low duty ratio is selected, the present invention is in an extinguishing process or a low power maintenance state during the etching process, that is, the B phase. The time is much longer than the A phase, in which the negative charge accumulated on the surface of the mask layer 2 is gradually extinguished or reduced, and other charges adsorbed on the inner sidewall of the etched via hole are gradually neutralized. Thus, when entering the A phase, the positively charged ions are not affected by the uneven electric field when they are incident, and can be vertically incident below, and the fluorocarbon protective layer of the sidewall is not damaged by bombardment, and the etching gas cannot be side. The etching is performed, so that the generation of the sidewall recess is prevented.

The invention can simultaneously increase the amplitude of the output power while selecting the ultra-low duty ratio. For example, the output power of the A-stage bias RF power supply in the prior art is 500W, the duty ratio is 50%, and the present invention selects 4%. The duty cycle and the output power reach 3000W, which can improve the etching rate and ensure the overall etching efficiency while eliminating Notch. At the same time, increasing the RF power can also increase the thickness of the sheath layer on the surface of the mask layer 2, and increase the acceleration of the ion downward. The faster the vertical incident velocity of the ion, the smaller the angle of deflection caused by the uneven electric field below, so the light can be alleviated. The etching of the sidewalls. This ultra-high power bias power output ensures that the incident ions are incident perpendicularly, but this power output cannot be maintained for a long time because the high-energy ions will also bombard the top mask material layer, and the mask layer will be destroyed to cause the etched pattern. Deformation. Therefore, the invention uses an ultra-low duty cycle with high power to ensure that no sidewall recesses are present, and that the mask pattern is completely accurate.

The invention can significantly improve the notch phenomenon at the bottom of the etched hole, and the sidewall recess is substantially not observed. Of course, except for the bottom of the etched hole (the portion below the etching hole depth of 2/3) can be reduced by the ultra-low duty ratio of the present invention. Lateral etching, the means of the invention can also be applied to other portions of the entire via etch. It can also be combined with the prior art in the first half with a conventional conventional duty cycle of 10-90% and conventional RF power, and an ultra-low duty cycle is used at the bottom. In order to improve the effect, higher RF power can be applied simultaneously at the bottom etching. .

Since the prior art does not select the pulse power supply of the ultra-low duty cycle required by the present invention, the inventors also need to modify the existing commercial RF power supply to obtain the RF power supply 40 having an ultra-low duty cycle RF pulse output. As shown in FIG. 5, the bias RF power source 40 of the present invention includes a built-in pulse signal source 42 that outputs a pulse signal of 20 Hz-200 Khz to a low frequency RF power source 48, and controls the output power of the low frequency RF power source 48 at a high power output of the pulse signal frequency. Switch between low power outputs. The duty cycle of the pulse signal output from the built-in pulse signal source 42 can only be adjusted between 10-90%. The output frequency of the low frequency RF power supply 48 can be a 2 Mhz bias RF power supply. The present invention also includes an external pulse signal source 44 that outputs a pulse signal of the same frequency as the built-in pulse signal, but the duty cycle of the output pulse can be precisely regulated in the range of 0.1-5% or 0.1-10%. Upon entering the conventional etch mode, the output of the built-in pulsed RF signal source 42 is coupled to the low frequency RF power source 48 via a select switch 46, which is selected when required to enter the ultra low duty cycle etch phase of the present invention. The output pulse signal of the external pulse signal source 44 is output to the low frequency RF power source 48, and finally the pulsed RF power is outputted through the output terminal 41 of the low frequency RF power source 48 to the lower electrode of the plasma reactor.

The invention can substantially eliminate the sidewall notch phenomenon by using the ultra-low duty ratio for deep hole etching of the SOI material, wherein the duty ratio is below 5%, especially 0.1%-4.5%, and the frequency range is 20hz-1Khz. When the notch is observed, the presence of a small number of notches can still be observed when the duty ratio is 5-10%, but it is also superior to the prior art. Only other parameters such as power, pulse frequency, etc. can be used to regulate. The technical effect achieved.

Although the present invention has been disclosed above, the present invention is not limited thereto. Any changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be determined by the scope defined by the appended claims.

100‧‧‧plasma reaction chamber

105‧‧‧Adjustment ring

110‧‧‧ gas source

120‧‧‧Base

121‧‧‧Electrostatic chuck

122‧‧‧Substrate

130‧‧‧Pneumatic valve

40‧‧‧Bad RF power supply

50‧‧‧Matching circuit

Claims (9)

A method for etching a via hole, comprising: placing a substrate to be processed onto a susceptor in a reaction chamber, wherein the substrate to be processed comprises an insulating material layer and a germanium material layer above the insulating material layer, and the germanium material layer further comprises Forming a mask layer opening; introducing a reaction gas into the reaction chamber, applying source RF power to the reaction chamber, forming a plasma, and etching downward from the opening of the patterned mask layer to form a through hole; Biasing the RF power output to bias the RF power to the pedestal to adjust the energy of ions in the plasma incident on the substrate; wherein at least one low duty cycle etch phase is included, at the low duty The biased RF power is pulsed in the etch phase, and its output power is switched between a high power output step and a low power output step, the duty cycle of the biased RF power pulse being between 0.1% and 4.5%. The 矽 via etching method of claim 1 wherein said biased RF power pulse frequency is between 20 hz and 1 Khz. A method of etching a via hole according to claim 1, wherein said substrate to be processed is etched down from the patterned mask layer opening to the bottom insulating material layer, wherein said opening to the bottom insulating material The layer has a through-hole depth greater than 10 μm. The 矽 via etching method of claim 3, wherein the 矽 via etch comprises a first etch phase, etching down from the mask layer opening to a first depth, biasing a duty cycle of the RF power pulse More than 10%; after the first etch phase is completed, the second etch phase is etched downward, and from the first deep etch to the bottom insulating material layer, the duty cycle of the biased RF power pulse is less than 10%. The 矽 via etching method according to claim 4, wherein the first depth is greater than or equal to 2/3 of the depth of the 矽 through hole. The 矽 via etching method of claim 4, wherein the high power output step of biasing the RF power pulse in the first etch phase outputs the first power, and the high power output step of biasing the RF power pulse in the second etch phase A second power is output, the first power being lower than the second power. The 矽 through hole etching method according to claim 1, further comprising a matching frequency obtaining step of setting an output power of the bias RF power source in the high frequency output step in the matching frequency obtaining step Switching between low power output steps, adjusting the output frequency of the biased RF power source or the source RF power source to obtain a plurality of matching frequencies matching the high power output step and the low power output step, in the slave mask layer During the downward etching of the opening to form the through hole, the output frequency of the biased RF power source or the source RF power source is switched between the plurality of matching frequencies. The 矽 through hole etching method according to claim 1, wherein said bias RF power source comprises an RF power generator and a built-in pulse signal source, and further comprises an external pulse signal source, and a switching switch selective communication station. An output signal of the built-in pulse signal source or the external pulse signal source to the RF power generator. A method of etching a via hole according to claim 8, wherein a duty ratio of the pulse signal source output pulse signal is between 10% and 100%, and an output pulse signal duty ratio of the external pulse signal source is Between 0.1% and 10%.