TWI588991B - Trench power semiconductor device - Google Patents

Description

Trenched power semiconductor component

The present invention relates to a power semiconductor component, and more particularly to a trench type power semiconductor device having a shield electrode.

Referring to FIG. 1, a cross-sectional view of a conventional trench power transistor is shown. In the structure of the trench power transistor 1, the two gates 130a, 130b and the shielding electrode 140 are juxtaposed in the same trench 100h, and are electrically insulated by the oxide layer 131. When the trench power transistor 1 is actually fabricated, the surface of the partial shielding electrode 140 and the sidewall surface of the trench 100h are oxidized by a thermal oxidation process to form an isolation between the shielding electrode 140 and the gate electrode 130a, respectively. An oxide layer 131 between 130b, and a gate oxide layer 132. However, the thickness of the oxide layer 131 prepared in this manner is low, resulting in a high capacitance between the gate electrodes 130a, 130b and the shield electrode 140.

In addition, due to limitations in process conditions, the further away from the surface of the trench 100h, the less likely the oxide layer is formed. Therefore, the bottom of the oxide layer 131 is thin. Thus, when the gate electrodes 130a and 130b are formed, the tip end portion 130s is formed on the side closer to the shield electrode 140 at the bottom end. This causes a tip effect, causing the withstand voltage of the gate electrodes 130a, 130b to drop. Moreover, it is easier to deteriorate the components at high temperatures, which reduces reliability and affects the device life of the trench power transistor.

The present invention provides a trench type power semiconductor device which can prevent a tip portion from being generated on a side of a gate electrode near a shield electrode when a gate electrode is formed.

One embodiment of the present invention provides a trench power semiconductor device including a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is on the substrate and has at least one component trench formed therein. The trench gate structure is located in the trench of the element, and the trench gate structure comprises a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding electrode. The first dielectric layer is disposed in the trench of the element and has a contour conforming to an inner wall surface of the trench of the component, wherein the first dielectric layer has a first upper inner wall surface and a lower inner wall surface connected to the first upper inner wall surface . The second dielectric layer covers at least the lower inner wall surface, wherein the material constituting the second dielectric layer is different from the material constituting the first dielectric layer. The gate electrode is disposed in the trench of the device, wherein the gate electrode includes a first conductive layer covering the first upper inner wall surface, and one end surface of the first conductive layer is connected to the first end surface of the second dielectric layer. The third dielectric layer covers the second dielectric layer and the inner surface of the first conductive layer. The shielding electrode is disposed in the trench of the component, wherein the third dielectric layer surrounds the shielding electrode to isolate the shielding electrode from the gate electrode.

Another embodiment of the present invention provides a trench type power semiconductor device including a substrate, an epitaxial layer, and a terminal electrode structure. The epitaxial layer is on the substrate and has at least one termination trench formed therein. The terminal electrode structure is located in the terminal trench, and the terminal electrode structure comprises a terminal dielectric layer, a conductive layer and a terminal electrode. The terminal dielectric layer has a contour substantially conforming to an inner wall surface of the terminal trench, wherein the terminal dielectric layer has a first insulating layer, a second insulating layer and a third insulating layer which are sequentially stacked on the inner wall surface, wherein the first dielectric layer The material of the second insulating layer is different from the material constituting the first insulating layer, and one end surface of the second insulating layer is lower than the top surfaces of the first insulating layer and the third insulating layer to be in the first insulating layer and the second insulating layer A recessed area is defined between the third insulating layers. The conductive layer is located in the recessed area. The terminal electrode is located in the terminal trench and is isolated from the conductive layer by the third insulating layer.

In summary, in the trench type power semiconductor device of the present invention, the first, second and third dielectric layers composed of different materials in the insulating layer surrounding the gate electrode and the shielding electrode can avoid forming a gate In the process of the electrode, a tip portion is formed on the side close to the shield electrode, thereby preventing the withstand voltage of the gate electrode from being lowered due to the tip effect.

The above described features and advantages of the present invention will be more apparent from the following description.

1‧‧‧Scheduled trench power transistors

110‧‧‧ epitaxial layer

120‧‧‧ drift zone

130a, 130b‧‧‧ gate

130s‧‧‧ tip

140‧‧‧shading electrode

100h‧‧‧ trench

131‧‧‧Oxide layer

132‧‧‧ gate oxide layer

2, 2', 3, 3', 4, 4', 5, 5'‧‧‧ trench power semiconductor components

20, 30, 40, 50‧‧‧ substrates

21, 31, 41, 51‧‧‧ buffer layer

22, 32, 42, 52‧‧‧ epitaxial layer

AR‧‧‧active area

TR‧‧‧ terminal area

220, 320, 420, 520‧‧‧ drift zone

221, 321, 421, 521‧‧‧ base area

222, 322, 422, 522‧‧ ‧ source area

220a, 320a, 420a, 520a‧‧‧ component trench

23, 33, 43, 53‧‧‧ trench gate structure

235, 335, 435, 535 ‧ ‧ shielding electrodes

231, 331, 431, 531‧‧‧ first dielectric layer

231a‧‧‧First upper inner wall

231c‧‧‧Second upper inner wall

231b‧‧‧ lower inner wall

232, 332, 432, 532‧‧‧ second dielectric layer

232a, 332a, 432a, 532a‧‧‧ first end

232b, 332b, 432b, 532b‧‧‧ second end face

233, 333, 433, 533‧‧‧ third dielectric layer

234, 334, 434, 534‧‧ ‧ gate electrodes

234a, 334a, 434a, 534a‧‧‧ first conductive layer

234b, 334b, 434b, 534b‧‧‧ second conductive layer

434c, 534c‧‧‧ third conductive layer

220b, 320b, 420b, 520b‧‧‧ terminal trench

24, 34, 44, 54‧‧‧ terminal electrode structure

245, 345, 445, 545‧‧‧ terminal electrodes

240, 340, 440, 540‧‧‧ terminal dielectric layer

244, 344‧‧‧ conductive layer

241, 341, 441, 541‧‧‧ first insulation layer

242, 342, 442, 542‧‧‧ second insulation

243, 343, 443, 543‧‧‧ third insulation

242e‧‧‧ end face

25, 25', 35, 35', 45, 45', 55, 55' ‧ ‧ interlayer dielectric layers

250, 350, 450, 550‧‧‧ source contact windows

251, 351, 451, 551‧‧ ‧ protective layer

252, 352, 452, 552‧‧ ‧ flat layer

26, 36, 46, 56‧‧‧ source conductive plug

27, 37, 47, 57‧‧‧ source pads

27', 37', 47', 57' ‧ ‧ contact pads

223, 323, 423, 523‧‧‧ contact doping

253, 353, 453, 553 ‧ ‧ Schottky contact window

29, 39, 49, 59‧‧‧ conductive plugs

232', 432', 532'‧‧‧ second dielectric material layer

433'‧‧‧ Third dielectric material layer

435'‧‧‧ Polycrystalline structure

242'‧‧‧Second layer of insulating material

28, 48a, 48b, 58‧‧‧ photoresist layer

280, 480, 580 ‧ ‧ openings

246, 346‧‧‧ recessed area

236‧‧‧First recessed area

436, 536‧‧‧Interpolar dielectric layer

436', 536'‧‧‧Interlayer of dielectric material

432s, 532s‧‧‧ hard film

437‧‧‧ Groove

438, 537‧‧ ‧ gate preset space

1 is a schematic cross-sectional view of a conventional power MOS field effect transistor.

2 is a partial cross-sectional view showing a trench type power semiconductor device according to an embodiment of the present invention.

2A is a partial cross-sectional enlarged view of the trench gate structure of FIG. 2.

2B is a partial cross-sectional view showing a trench power semiconductor device according to another embodiment of the present invention.

3A-3E are partial cross-sectional views showing the trench power semiconductor device in each process step, in accordance with an embodiment of the present invention.

4 is a partial cross-sectional view showing a trench power semiconductor device according to another embodiment of the present invention.

4A is a partial cross-sectional view showing a trench power semiconductor device according to another embodiment of the present invention.

FIG. 5 is a partial cross-sectional view showing a trench power semiconductor device according to another embodiment of the present invention.

5A is a partial cross-sectional view showing a trench power semiconductor device according to another embodiment of the present invention.

6A to 6E are respectively partial cross-sectional views showing the trench power semiconductor device in each process step according to an embodiment of the present invention.

FIG. 7 is a partial cross-sectional view showing a trench power semiconductor device according to another embodiment of the present invention.

7A is a partial cross-sectional view showing a trench power semiconductor device according to another embodiment of the present invention.

8A to 8C are respectively partial cross-sectional views showing the trench power semiconductor device in each process step according to an embodiment of the present invention.

Please refer to Figure 2. The trench power semiconductor device 2 includes a substrate 20, an epitaxial layer 22, a trench gate structure 23, and a termination electrode structure 24.

The trench power semiconductor component 2 can be a trench power transistor or a power semiconductor component having a Schottky diode. In FIG. 2, the structure of the trench type power transistor will be described as an example.

In FIG. 1, the substrate 20 has a high concentration of first type conductivity impurities to serve as a drain of the trench power semiconductor device. The aforementioned first type conductive impurities may be N-type or P-type conductive impurities. It is assumed that the substrate 20 is a ruthenium substrate, the N-type conductivity impurity is a pentavalent element ion such as a phosphorus ion or an arsenic ion, and the P-type conductivity impurity is a trivalent element ion such as a boron ion, an aluminum ion or a gallium ion.

If the trench power semiconductor device is N-type, the substrate 20 is doped with N-type conductive impurities. On the other hand, in the case of a P-type trench type power semiconductor device, the substrate 20 is doped with a P-type conductive impurity. In the embodiment of the present invention, an N-type trench power semiconductor device is taken as an example for description.

An epitaxial layer 22 is on the substrate 20 and has the same conductivity type as the substrate 20, but the doping concentration of the epitaxial layer 22 is lower than the doping concentration of the substrate 20. Taking an NMOS transistor as an example, the substrate 20 has a high concentration of N-type doping (N ⁺ ), and the epitaxial layer 22 has a low concentration of N-type doping (N ^- ). In PMOS transistor as an example, the substrate 20 and the P-type epitaxial layer 22 are doped with a high concentration (P ⁺ doping), and a low concentration of P-type dopant (P ^- doping).

In the present embodiment, the trench power semiconductor device 2 further includes a buffer layer 21 disposed between the epitaxial layer 22 and the substrate 20. The buffer layer 21 has the same conductivity type as the substrate 20 and the epitaxial layer 22. It is to be particularly noted that the doping concentration of the buffer layer 21 is between the doping concentration of the substrate 20 and the doping concentration of the epitaxial layer 22. The buffer layer 21 can reduce the on-state source/drain resistance (Rdson), thereby reducing the power consumption of the trench power semiconductor device 2.

In addition, in the embodiment of FIG. 2, by doping different concentrations in different regions and Different types of conductive impurities, the epitaxial layer 22 can be divided into a drift region 220, a body region 221, and a source region 222. The base region 221 and the source region 222 are formed in the epitaxial layer 22 on the side of the trench gate structure 23, and the drift region 220 is located on the side of the epitaxial layer 22 adjacent to the substrate 20. That is, the base region 221 and the source region 222 are formed in the upper half of the epitaxial layer 22, and the drift region 220 is formed in the lower half of the epitaxial layer 22.

In detail, the base region 221 is formed by doping the epitaxial layer 22 with a second type of conductive impurity, and the source region 222 is doped with a high concentration of the first conductivity in the base region 221 An impurity is formed, and the source region 222 is formed in the upper half of the base region 221. For example, for an NMOS transistor, the base region 221 is P-type doped (eg, P-well, P-well) and the source region 222 is N-doped. Further, the doping concentration of the base region 221 is smaller than the doping concentration of the source region 222.

In addition, in the embodiment, the epitaxial layer 22 defines an active area AR and at least one terminal area TR adjacent to the active area AR. The aforementioned base region 221 and source region 222 are both located in the active region AR. The epitaxial layer 22 has at least one element trench 220a in the active region AR and at least one terminal trench 220b in the termination region TR.

It is to be particularly noted that the element trench 220a has a deep trench structure. That is, the element trench 220a extends downward from the surface of the epitaxial layer 22 into the drift region 220, and the bottom of the element trench 220a is closer to the substrate 20. It should be noted that, in the embodiment of the present invention, the element trench 220a is roughly divided into an upper half and a lower half with the lower edge of the base region 221 as a reference surface.

In the embodiment of the present invention, at least one trench gate structure 23 is disposed in the corresponding element trench 220a. Referring to FIG. 2A, a partial cross-sectional enlarged view of the trench gate structure 23 of FIG. 2 is illustrated. As shown in FIG. 2A, the trench gate structure 23 has a shielding electrode 235, a first dielectric layer 231, a second dielectric layer 232, a third dielectric layer 233, and a gate electrode 234, wherein the first dielectric layer 231 The second dielectric layer 232 and the third dielectric layer 233 are sequentially stacked on the inner wall surface of the element trench 220a, and are used to make the gate electrically The pole 234 and the shield electrode 235 are isolated from the epitaxial layer 22. The aforementioned inner wall surface includes both side wall surfaces and a bottom surface of the element groove 220a.

Specifically, the first dielectric layer 231 conforms to the inner wall surface of the element trench 220a and has a contour substantially conforming to the inner wall surface of the element trench 220a. In addition, the first dielectric layer 231 has a first upper inner wall surface 231a, a second upper inner wall surface 231c opposite to the first upper inner wall surface 231a, and a first upper inner wall surface 231a and a second upper inner wall surface 231c. Lower inner wall surface 231b. The second dielectric layer 232 covers at least the lower inner wall surface 231b of the first dielectric layer 231.

The thickness of the first dielectric layer 231 and the thickness of the second dielectric layer 232 can be determined according to the voltage to which the gate electrode 234 is to be subjected and the width of the gate electrode 234. For example, if the voltage to be withstood by the gate electrode 234 is between 20 and 25 V, the thickness of the first dielectric layer 231 is between 25 and 60 nm, and the thickness of the second dielectric layer 232 is between 200 and 250 nm. between.

The gate electrode 234 is disposed in the element trench 220a and includes at least a first conductive layer 234a and a second conductive layer 234b disposed to face the first conductive layer 234a. In other embodiments, the gate electrode 234 may also include only the first conductive layer 234a or the second conductive layer 234b.

The first conductive layer 234a and the second conductive layer 234b cover the first upper inner wall surface 231a and the second upper inner wall surface 231c, respectively. Moreover, the bottom end of the first conductive layer 234a is connected to the first end surface 232a of the second dielectric layer 232, and the bottom end of the second conductive layer 234b is connected to the second end surface of the second dielectric layer 232. In addition, the first conductive layer 234a and the second conductive layer 234b are electrically insulated by the first dielectric layer 231 and the epitaxial layer 22.

In this embodiment, the first end surface 232a and the second end surface 232b may be equal to or lower than a plane in which the lower edge of the base region 221 is located. That is, the planes at which the bottom ends of the first conductive layer 234a and the second conductive layer 234b are located may be lower than the plane in which the lower edge of the base region 221 is located. Thus, when the gate electrode 234 is biased, an inversion channel can be formed in the body region 221 near the side walls of the element trench 220a. (inversion channel). In addition, in an embodiment, the thickness of the first conductive layer 234a and the thickness of the second conductive layer 234b may be substantially the same as the thickness of the second dielectric layer 232.

The third dielectric layer 233 is disposed to cover the inner surfaces of the first conductive layer 234a, the second dielectric layer 232, and the second conductive layer 234b. That is, the first conductive layer 234a, the second conductive layer 234b, and the second dielectric layer 232 are commonly sandwiched between the first dielectric layer 231 and the third dielectric layer 233.

In this embodiment, the material of the second dielectric layer 232 is different from the materials of the first dielectric layer 231 and the third dielectric layer 233. As such, when the second dielectric layer 232 is removed by the selective etching step, both the first dielectric layer 231 and the third dielectric layer 233 can be retained. However, the materials constituting the first dielectric layer 231 and the third dielectric layer 233 are not necessarily the same.

For example, the first dielectric layer 231 and the third dielectric layer 233 may be an oxide layer, and the second dielectric layer 232 may be a nitride layer, wherein the oxide layer may be selected from cerium oxide or aluminum oxide or zirconium oxide. A material having a high dielectric constant such as cerium oxide or cerium oxide, and the nitride layer is, for example, tantalum nitride. However, as long as the above effects can be achieved, the materials selected for the first to third dielectric layers 231 to 233 are not limited. In the present embodiment, the thickness of the third dielectric layer 233 is between 100 and 300 nm.

The shielding electrode 235 is located in the element trench 220a and is electrically insulated from the first conductive layer 234a and the second conductive layer 234b.

In detail, the shielding electrode 235 is extended from the upper half of the element trench 220a to the lower half of the element trench 220a, and the first conductive layer 234a and the second conductive layer 234b are respectively located on opposite sides of the shielding electrode 235. As shown in FIG. 2A, a portion of the shielding electrode 235 is disposed to overlap the first conductive layer 234a and the second conductive layer 234b, and passes through both ends of the third dielectric layer 233 and the first conductive layer 234a and the second, respectively. The conductive layer 234b is electrically insulated.

It should be noted that the device trench 220a has a deep trench structure, which helps to increase the breakdown voltage of the trench power semiconductor device 2, but increases the gate/drain capacitance. (Cgd) and source/drain conduction resistance (Rdson). Accordingly, in the embodiment of the present invention, providing the shielding electrode 235 in the element trench 220a can reduce the gate/drain capacitance (Cgd) to reduce the operation loss. In addition, the shielding electrode 235 can be electrically connected to the source to bring the drift region 220 to charge balance, and further increase the breakdown voltage. Therefore, the impurity doping concentration of the drift region 220 can be relatively increased to lower the on-resistance in the drift region 220.

The terminal electrode structure 24 is located in the terminal trench 220b and includes a terminal electrode 245, a termination dielectric layer 240, and a conductive layer 244. The terminal electrode 245 is electrically connected to each other through the termination dielectric layer 240 and the conductive layer 244 and the epitaxial layer 22. insulation.

Specifically, the terminal electrode 245 extends from the upper half of the terminal trench 220b to the lower half. The termination dielectric layer 240 is conformed to an inner wall surface of the terminal trench 220b and has a contour substantially conforming to the inner wall surface of the terminal trench 220b. The terminal dielectric layer 240 includes at least a first insulating layer 241, a second insulating layer 242, and a third insulating layer 243.

The first to third insulating layers 241 to 243 are sequentially stacked on the inner wall surface of the terminal trench 220b. That is, the second insulating layer 242 is interposed between the first and third insulating layers 241, 243. In the present embodiment, the material constituting the second insulating layer 242 is different from the material constituting the first insulating layer 241. For example, the material constituting the first insulating layer 241 is, for example, yttrium oxide, and the material constituting the second insulating layer 242 is, for example, tantalum nitride.

In the present embodiment, the second insulating layer 242 has an end surface 242e, and the end surface 242e is lower than the top surface of the first insulating layer 241 and the top surface of the third insulating layer 243 to the first to third insulating layers 241. A recessed area 246 is defined between ~243. Since the material constituting the second insulating layer 242 is different from the first and third insulating layers 241, 243, the recessed region 246 can be formed by performing selective etching. In addition, in this embodiment, the end surface 242e of the second insulating layer 242 is lower than the plane of the top end of the terminal electrode 245.

The conductive layer 244 is located in the recessed region 246, and the bottom end of the conductive layer 244 is The end faces 242e of the two insulating layers 242 are connected. In general, the conductive layer 244 is disposed side by side with the terminal electrode 245 in the terminal trench 220b, and the conductive layer 244 overlaps with a portion of the terminal electrode 245. In addition, the conductive layer 244 and the terminal electrode 245 are separated from each other by the third insulating layer 243. In an embodiment, the conductive layer 244 will have substantially the same thickness as the second insulating layer 242. The conductive layer 244 may be electrically connected to the source or the gate and may cooperate with the terminal electrode 245 to increase the breakdown voltage of the trench power semiconductor device 2.

It should be noted that the first to third insulating layers 241-243 may be the same as the materials of the first to third dielectric layers 231 to 233, respectively, and formed in the same deposition process, and thus the first to third insulating layers 241 The thickness of ~243 may be the same as the thickness of the first to third dielectric layers 231 to 233, respectively.

Referring to FIG. 2 , the trench power semiconductor device 2 of the embodiment of the present invention further includes an interlayer dielectric layer 25 , at least one source conductive plug 26 , and a source pad 27 .

The interlayer dielectric layer 25 is formed on the epitaxial layer 22 and has a protective layer 251 and a flat layer 252. In the present embodiment, the protective layer 251 is directly formed on the surface of the epitaxial layer 22, and the material of the protective layer 251 may be the same as the first dielectric layer 231 in the element trench 220a. That is, when the first dielectric layer 231 is an oxide layer, the protective layer 251 is also an oxide layer. In this case, the protective layer 251 and the first dielectric layer 231 can be formed in the same deposition process. The detailed process steps will be described later and will not be described here.

In other embodiments, the material constituting the protective layer 251 may also be different from the first dielectric layer 231, and the present invention is not limited thereto. The flat layer 252 is formed on the protective layer 251, and the material constituting the flat layer 252 may be borophosphon glass (BPSG), phosphorous glass (PSG), oxide, nitride, or a combination thereof.

Additionally, the interlayer dielectric layer 25 has at least one source contact window 250. In the present embodiment, the source contact window 250 extends from the upper surface of the interlayer dielectric layer 25 to a portion of the epitaxial layer 22 and is formed on one side of the source region 222. Moreover, the epitaxial layer 22 further includes a contact doping region 223, and the contact doping region 223 is located directly below the bottom of the source contact window 250. In one embodiment, boron fluoride ions (BF ²⁺ ) are implanted in the epitaxial layer 22 through the source contact window 250 to form a contact doped region 223.

However, the position of the source contact window 250 may vary depending on the design of the element, and is not limited to the embodiment of the present invention. In other embodiments, the source contact window 250 may also directly correspond to the location of the source region 222 and be formed directly above the source region 222.

A source conductive plug 26 is formed in the source contact window 250 to be electrically connected to the source region 222. Specifically, the source conductive plug 26 is formed in the source contact window 250 and directly contacts the source region 222 and the contact doping region 223 located in the epitaxial layer 22, whereby the source conductive plug 26 is An ohmic contact is formed between the source regions 222. The material constituting the source conductive plug 26 may be a metal such as, but not limited to, tungsten, copper, nickel or aluminum.

The source pad 27 covers the planar layer 252 and is electrically connected to the source region 222 through a source conductive plug 26 that is disposed through the interlayer dielectric layer 25. That is, the source pad 27 can serve as the source electrode of the trench power semiconductor device 2 and is electrically connected to an external control circuit. The material of the source pad 27 may be titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum-bismuth alloy (Al-Si) or aluminum beryllium copper alloy (Al-Si-Cu), etc., but The invention is not limited thereto.

The trench gate structure 23 and the terminal electrode structure 24 shown in the embodiment of Fig. 2 are also applicable to the trench type power semiconductor element 2' having a Schottky diode.

Referring to Fig. 2B, in detail, in the trench type power semiconductor device 2', the base region and the source region are not formed in the epitaxial layer 22. Further, the trench power semiconductor device 2' has an interlayer dielectric layer 25' on the epitaxial layer 22, a conductive plug 29, and a contact pad 27' on the interlayer dielectric layer 25'.

The contact pad 27' is electrically connected to the epitaxial layer 22 through a conductive plug 29 to form a Schottky diode. In detail, the interlayer dielectric layer 25' has at least one Schottky contact window 253 (a plurality of which are illustrated in FIG. 2B), and the conductive plug 29 penetrates the interlayer dielectric layer 25' through the Schottky contact window 253. And extending into the epitaxial layer 22, and located in the trench The epitaxial layer 22 between 220a is in electrical contact.

Therefore, the trench gate structure 23 and the terminal electrode structure 24 provided by the embodiments of the present invention are not limited to application in a power transistor element.

The method of manufacturing the trench power semiconductor device 2 of the present embodiment will be further described below.

As shown in FIG. 3A, a buffer layer 21 and an epitaxial layer 22 have been formed on the substrate 20.

The epitaxial layer 22 defines an active area AR and a termination area TR. Further, at least one of the element trenches 220a located in the active region AR and at least one of the terminal trenches 220b located in the termination region have been formed in the epitaxial layer 22. In an embodiment, the depth of the element trench 220a and the termination trench 220b is between about 2 and 6 μm.

Further, on the inner wall surface of the element trench 220a, the first dielectric layer 231, the second dielectric material layer 232', and the third dielectric layer 233 are sequentially formed. On the inner wall surface of the terminal trench 220b, the first insulating layer 241, the second insulating material layer 242', and the third insulating layer 243 are formed.

In this embodiment, the material constituting the second dielectric material layer 232' may be different from the first and third dielectric layers 231, 233, but the materials of the first dielectric layer 231 and the third dielectric layer 233 are selected. There are no special restrictions. In detail, as long as the first dielectric layer 231 and the third dielectric layer 233 are left in the subsequent selective etching step, the second dielectric material layer 232' is removed. Similarly, the material constituting the second insulating material layer 242' may be different from the first dielectric layer 231 and the third dielectric layer 233.

A protective layer 251 has been formed on the surface of the epitaxial layer 22. The protective layer 215, the first dielectric layer 231 and the first insulating layer 241 can be formed synchronously by physical vapor deposition or chemical vapor deposition processes. For example, the first dielectric layer 231 and the first insulating layer 241 may both be yttrium oxide (SiOx) and formed by a thermal oxidation process.

Similarly, the second dielectric material layer 232' and the second insulating material layer 242' may also be formed in the same process. When the first dielectric layer 231 and the first insulating layer 241 are yttrium oxide, the second dielectric material layer 232' and the second insulating material layer 242' may be selected from a nitride such as tantalum nitride. The third dielectric layer 233 and the third insulating layer 243 may be yttrium oxide (SiO ₂ ).

In FIG. 3A, the shield electrode 235 and the terminal electrode 245 are also formed in the element trench 220a and the termination trench 220b, respectively. In detail, a polysilicon layer is formed on the epitaxial layer 22 in a blanket manner and filled in the element trench 220a and the terminal trench 220b. The polysilicon layer may be a doped poly-Si containing conductive impurities. Next, the polysilicon layer covered on the surface of the epitaxial layer 22 is removed by etch back, leaving the terminal electrode 245 located in the shield electrode 235 of the element trench 220a and the termination trench 220b, respectively.

Next, referring to FIG. 3B, a photoresist layer 28 is formed on the epitaxial layer 22 and covers the termination region TR. The photoresist layer 28 has an opening 280 to expose the active region AR and a portion of the second insulating material layer 242' located within the terminal trench 220b and closest to the active region AR side. In addition, in the present embodiment, the photoresist layer 28 covers the terminal electrode 245 in the termination trench 220b.

Next, referring to FIG. 3C, a selective etching step is performed through the opening 280 of the photoresist layer 28 to remove the second dielectric material layer 232' partially located in the upper half of the element trench 220a and partially located in the termination trench 220b. The second insulating material layer 242' of the upper half forms a second dielectric layer 232 and a second insulating layer 242 as shown in FIG.

The selective etching step may be wet etching, and may be selective to the second dielectric material layer 232' and the second insulating material layer 242', but to the first and third dielectric layers 231, 233 and the first insulating layer. 241 is selectively etched with a low selectivity chemical solution. Therefore, the first and third dielectric layers 231, 233 and the first insulating layer 241 may be left when a portion of the second dielectric material layer 232' and a portion of the second insulating material layer 242' are removed.

As shown in FIG. 3C, after the selective etching step is completed, at least one first recessed region 236 is formed in the element trench 220a, and a recessed region 246 is formed in the terminal trench 220b. In other words, the first and third dielectric layers 231, 233 formed in the device trench 220a, and the first insulating layer 241 in the termination trench 220b can be used as an etch mask power to respectively be in the device trench The first recessed region 236 is defined in 220a and the location and shape of the recessed region 246 is defined in the terminal trench 220b.

Referring to FIG. 3D, after the photoresist layer 28 is removed, the first conductive layer 234a and the second conductive layer 234b are formed in the element trench 220a, and the conductive layer 244 is formed in the termination trench 220b. In one embodiment, a polysilicon layer is formed on the surface of the epitaxial layer 22 and filled in the first recessed region 236 and the recessed region 246, and then etched back to remove the polycrystalline germanium layer on the surface of the epitaxial layer 22. The polysilicon layer in the first recessed region 236 and the recessed region 246 is left, and the first conductive layer 234a and the second conductive layer 234b are formed in the element trench 220a, respectively, and the conductive layer 244 is formed in the terminal trench 220b. The first conductive layer 234a and the second conductive layer 234b are the gate electrodes 234 of the trench power semiconductor device 2 shown in FIG.

In FIG. 3C, the first recess region 236 and the recess region 246 are formed through a selective etching step, and the gate electrode 234 (including the first conductive layer 234a and the second layer) may be defined in the element trench 220a and the termination trench 220b in advance. Conductive layer 234b) and the location and shape of conductive layer 244.

It should be noted that, in the embodiment of the present invention, the third dielectric layer 233 or the third insulating layer 243 is not formed by oxidizing the surface of the shielding electrode 235 or the terminal electrode 245 by a thermal oxidation process, and thus is compared with Conventionally, the thickness uniformity of the third dielectric layer 233 and the third insulating layer 243 is preferred.

In addition, the width of the element trench 220a is generally narrow. If the second dielectric material layer 232' is not formed, it is difficult to accurately define the positions of the two first recess regions 236 in the same element trench 220a even if photoresist is used. And shape.

In contrast, the process method provided by the embodiment of the present invention can define two first recess regions 236 in the same component trench 220a without covering the photoresist on the component trench 220a. Moreover, during the selective etching process, the first and third dielectric layers 231, 233 are not laterally etched, so the first conductive layer 234a (or the second conductive) subsequently formed in the first recessed region 236 is formed. The layer 234 b ) can be electrically insulated from the shielding electrode 235 through the third dielectric layer 233 , and can also be electrically insulated by the first dielectric layer 231 and the epitaxial layer 22 .

Therefore, the conductive layer 244, the first conductive layer 234a and the second conductive layer are formed In the process of 234b, the side of the first conductive layer 234a and the bottom end of the second conductive layer 234b adjacent to the shielding electrode 235 does not generate a tip end portion, which can prevent the tip effect from affecting the electrical properties of the device and improve the withstand voltage of the gate electrode 234. . In addition, the thickness of the third dielectric layer 233 is also relatively thick, about 100 to 300 nm, which can reduce the capacitance between the gate and the shielding electrode (electrically connected to the source), thereby improving the trench. Switching rate of slotted power semiconductor components.

Referring to FIG. 3E, a substrate doping process and a source doping process are performed to form a source region 222 and a base region 221 on a side of the epitaxial layer 22 away from the substrate 20, wherein the source region 222 is located in the base region. Above the 221. It should be noted that the source doping process may include performing a thermal diffusion process after ion implantation. In addition, as can be seen from FIG. 3E, the plane of the lowest edge of the base region 221 in this embodiment is higher than the first end surface 232a and the second end surface 232b of the second dielectric layer 232.

Next, a line redistribution layer is formed on the epitaxial layer 22 to electrically connect the source region 222, the gate electrode 234 and the shielding electrode 235 to an external control circuit. The specific steps of the circuit redistribution layer will be described below by taking the source contact plug shown in FIG. 2 as an example. First, a planar layer 252 that completely covers the protective layer 251, the trench gate structure 23, and the terminal electrode structure 24 can be formed. The material constituting the flat layer 252 may be selected from the group consisting of borophosphoquinone glass (BPSG), phosphorous bismuth glass (PSG), oxide, nitride, or a combination thereof.

Subsequently, corresponding to the position of the source region 222, at least one source contact window 250 is formed (three are illustrated in FIG. 3E as an example). In this embodiment. The technical means for forming the source contact window 250 can be implemented by conventional steps such as coating photoresist, lithography, etching, and the like. Next, a source conductive plug 26 is formed within the corresponding source contact window 250. The source conductive plug 26 extends through the flat layer 252 and the protective layer 251 , extends into the epitaxial layer 22 , and is located on one side of the source region 222 to be electrically connected to the source region 222 . Before the source conductive plug 26 is formed on the corresponding source contact window 250, the epitaxial layer 22 may be subjected to a doping process through the source contact window 250 to form the epitaxial layer 22 under the source contact window 250. A contact doping region 223 is formed in the middle. In an embodiment, the impurity doped by the contact doping region 223 is boron difluoride ion (BF2 ⁺ ).

In addition, after the source conductive plug 26 is formed on the corresponding source contact window 250, a source pad 27 may be formed to cover the flat layer 252 and electrically connected to the source conductive plug 26. The source pad 27 can be electrically connected to an external control circuit. The material of the source pad 27 may be titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum-bismuth alloy (Al-Si) or aluminum beryllium copper alloy (Al-Si-Cu), etc., but The invention is not limited thereto.

Accordingly, the source pad 27 can be electrically connected to the source region 222 and the contact doping region 223 through the source conductive plug 26 . In addition, the shielding electrode 235 and the terminal electrode 245 can also be electrically connected to the source pad 27 through another conductive plug, and the process of electrically connecting the shielding electrode 235 and the terminal electrode 245 to the source pad 27 can be The process of forming the source contact window 250 and the source conductive plug 26 is completed in one piece. Through the description of the above embodiments, those skilled in the art should be able to easily infer other implementation details, which are not described herein.

Referring to FIG. 4, in the trench type power semiconductor device 3 of the present embodiment, the shielding electrode 335 and the first conductive layer 334a and the second conductive layer 334b do not overlap. That is, the shield electrode 335 is located only in the lower half of the element trench 220a. In the present embodiment, the plane at which the tip end of the shielding electrode 335 is located may be lower than the plane in which the lower edge of the base region 221 is located. In addition, the third dielectric layer 333 completely surrounds the shielding electrode 335 and separates the first conductive layer 234a from the second conductive layer 234b.

In the present embodiment, since the gate electrode 234 and the shielding electrode 235 do not overlap each other, a capacitance is not formed between the gate electrode 234 and the shielding electrode 235, and the trench power semiconductor device 3 has a faster speed. Switch speed.

In addition, the terminal electrode 345 of the terminal electrode structure 34 and the conductive layer 344 do not overlap. In detail, the terminal electrode 345 is also located in the lower half of the terminal trench 320b and is completely surrounded by the third insulating layer 343.

Next, referring to FIG. 4A, the trench gate structure 33 and the terminal electrode structure 34 shown in the embodiment of FIG. 4 are also applicable to the trench power semiconductor device 3' having a Schottky diode. Schottky diode of trench power semiconductor component 3' The structure of the embodiment is similar to that of the embodiment of FIG. 2B, and details are not described herein again.

In addition, the process of fabricating the trench power semiconductor device 3 of FIG. 4 is similar to the embodiment of FIGS. 3A to 3E, that is, in performing the selective etching step, the first dielectric layer 331 and the third dielectric layer 333 are used. The position and shape of the gate electrode 334 and the conductive layer 344 are defined as an etch mask power.

Next, referring to FIG. 5, the gate electrode 434 of the trench gate structure 43 of the trench power semiconductor device 4 further includes a third conductive layer 434c connected between the first conductive layer 434a and the second conductive layer 434b. . The third conductive layer 434c is disposed above the shielding electrode 435 and electrically insulated from the shielding electrode 435.

In the present embodiment, the shielding electrode 435 is located in the lower half of the element trench 420a, and the shielding electrode 435 and the first conductive layer 434a and the second conductive layer 434b do not overlap. That is, the plane at which the tip end of the shield electrode 435 is located is a plane lower than the lower edge of the base region 421.

In addition, the trench gate structure 43 may further include an inter-electrode dielectric layer 436 disposed between the shielding electrode 235 and the third conductive layer 434c to isolate the shielding electrode 235 and the third conductive layer 434c from each other. The material constituting the inter-electrode dielectric layer 436 may be an oxide (e.g., hafnium oxide), a nitride (e.g., nitride), or other insulating material, which is not limited in the present invention.

In this embodiment, the bottom ends of the first conductive layer 434a and the second conductive layer 434b are also respectively connected to the first end surface 432a and the second end surface 432b of the second dielectric layer 432. In addition, the first conductive layer 434a and the second conductive layer 434b are interposed between the inter-electrode dielectric layer 436 and the first dielectric layer 431. Therefore, the material of the second dielectric layer 432 may be different from the material of the inter-electrode dielectric layer 436 to facilitate defining the positions of the first conductive layer 434a and the second conductive layer 434b by a selective etching step.

In a preferred embodiment, the material of the second dielectric layer 432 is also different from the material of the third dielectric layer 433. However, it should be noted that the material of the second dielectric layer 432 is the same as the material of the third dielectric layer 433, and is not particularly limited.

Different from the terminal electrode structures 24 and 34 of FIGS. 2 and 3, the embodiment of the present invention Terminal electrode structure 44 does not have a conductive layer. In detail, in the embodiment, the terminal electrode structure 44 includes the terminal electrode 445 and the termination dielectric layer 440 , and the terminal electrode 445 is electrically insulated from the epitaxial layer 42 by the termination dielectric layer 440 . The terminal dielectric layer 440 has first to third insulating layers 441 to 443 sequentially stacked on the inner wall surface of the terminal trench 420b, wherein the second insulating layer 442 completely covers the inner sidewall surface of the first insulating layer 441. In addition, the terminal electrode 445 extends from the upper half of the terminal trench 420b to the lower half of the terminal trench 420b.

Next, referring to FIG. 5A, the trench gate structure 43 and the terminal electrode structure 44 shown in the embodiment of FIG. 6 are also applicable to the trench power semiconductor device 4' having a Schottky diode. The structure of the Schottky diode of the trench power semiconductor device 4' is similar to that of the embodiment of Fig. 2B and will not be described herein.

Next, please refer to FIG. 6A to FIG. 6E. Specifically, the processes of FIGS. 6A through 6E can be used to prepare the trench power semiconductor device 4 shown in FIG.

As shown in FIG. 6A, a buffer layer 41 and an epitaxial layer 42 have been formed on the substrate 40, and at least one element trench 420a has been formed in the active region AR of the epitaxial layer 42, and at least one is formed in the termination region TR. Terminal trench 420b.

A first dielectric layer 431, a second dielectric material layer 432', a third dielectric material layer 433', and a polysilicon structure 435' have been formed in the trench 420a, and in the termination trench 420b, a first An insulating layer 441, a second insulating layer 442, a third insulating layer 443, and a terminal electrode 445. In the present embodiment, the terminal electrode 445 extends from the upper half of the terminal trench 420b to the lower half.

It should be noted that in FIG. 6A, a protective layer 451 and a hard film layer 432s overlying the protective layer 451 have been formed on the surface of the epitaxial layer 22. The protective layer 451 is made of the same material as the first dielectric layer 431 and the first insulating layer 441 and can be formed in the same deposition process. The hard film layer 432s, the second dielectric material layer 232', and the second insulating layer 242 are made of the same material and can be formed in the same deposition process.

Next, as shown in FIG. 6B, the third dielectric material layer 433' and the polysilicon structure 435' partially located in the upper half of the element trench 420a are removed to be in the element trench 420a. A third dielectric layer 433 and a shielding electrode 435 are formed.

In detail, a photoresist layer 48a is formed on the termination trench 420b to cover the terminal electrode 445 and the third insulating layer 443. The photoresist layer 48a has at least one opening 480 to expose the element trench 420a. Next, an etching step is performed to remove a portion of the third dielectric material layer 433' and the polysilicon structure 435', thereby defining a recess 437 in the element trench 220a. In an embodiment, the depth of the recess 437 is approximately between 1 and 1.3 [mu]m.

Specifically, when a portion of the third dielectric material layer 433 ′ and the polysilicon structure 435 ′ are removed, the hard film layer 432 s and the second dielectric material layer 432 ′ may serve as an etch power to protect the first dielectric layer. 431. First insulating layer 441 and protective layer 451. After removing a portion of the third dielectric material layer 433' and the polysilicon structure 435', the photoresist layer 48a is removed.

Referring to FIG. 6C, an inter-electrode dielectric layer 436 is formed over the device trench 420a to cover the third dielectric layer 433 and the shielding electrode 435. It should be noted that the recess 437a is not completely filled by the inter-electrode dielectric layer 436. As previously mentioned, the depth of the recess 437 is approximately between 1 and 1.3 μm, and the thickness of the inter-electrode dielectric layer 436 is approximately between 200 nm and 300 nm.

Referring to FIG. 6D, a portion of the second dielectric material layer 232' located on the upper half of the element trench 420a and a hard film layer 432s overlying the protective layer 451 are removed to define a gate preset space 438. It should be noted that the gate preset space 438 includes two recessed regions between the two sides of the inter-electrode dielectric layer 436 and the first dielectric layer 431.

Next, referring to FIG. 6E, a gate electrode 434 is formed in the gate preset space 438, and the gate electrode 434 includes a first conductive layer 434a connected to the first end surface 432a of the second dielectric layer 432, and is connected to the first The second conductive layer 434b of the second end surface 432b of the second dielectric layer 432 and the third conductive layer 434c connected between the first conductive layer 434a and the second conductive layer 434b. The third conductive layer 434c is located on the inter-electrode dielectric layer 436 and is electrically insulated by the inter-electrode dielectric layer 436 and the shield electrode 435.

Next, referring to the previously described steps, the base region 421, the source region 422, and the line redistribution layer are sequentially formed.

Referring to FIG. 7, the terminal electrode 545 of the trench power semiconductor device 5 of the present embodiment is located only in the lower half of the terminal trench 520b. That is, the plane at which the tip end of the terminal electrode 545 is located is lower than one end surface of the second insulating layer 542.

Next, referring to FIG. 7A, the trench gate structure 53 and the terminal electrode structure 54 shown in FIG. 7 are also applicable to the trench power semiconductor device 5' having a Schottky diode. The structure of the Schottky diode of the trench power semiconductor device 5' is similar to that of the embodiment of Fig. 2B and will not be described again.

It should be noted that the terminal electrode structures 24, 34, 44, 54 of the embodiments provided in the present invention can be replaced with each other as long as the trench power semiconductor device can have a high breakdown voltage, which is not in the present invention. The manner in which the trench gate structures 23, 33, 43, 53 are in contact with the terminal electrode structures 24, 34, 44, 54 is specifically limited.

Next, please refer to FIGS. 8A to 8C. Specifically, the flow steps of FIGS. 8A through 8C can be used to prepare the trench power semiconductor device 5 shown in FIG.

Referring first to FIG. 8A, a buffer layer 51 and an epitaxial layer 52 have been formed on the substrate 50, and at least one element trench 520a has been formed in the active region AR of the epitaxial layer 52, and at least a terminal region TR is formed. A terminal trench 520b.

A first dielectric layer 531, a second dielectric material layer 532', a third dielectric layer 533, a shielding electrode 535, and an inter-electrode dielectric material layer 536' overlying the shielding electrode 535 have been formed in the element trench 520a. . In the terminal trench 520b, a first insulating layer 541, a second insulating layer 542, a third insulating layer 543, and a terminal electrode 545 have been formed in the terminal trench 520b.

In the present embodiment, the shielding electrode 535 and the terminal electrode 545 are located in the lower half of the element trench 520a and the terminal trench 520b, respectively. In the present embodiment, the third insulating layer 543 covers the terminal electrode 545 and completely covers the terminal electrode 545.

It should be noted that in FIG. 8A, a protective layer 551 and a hard film layer 532s overlying the protective layer 551 have been formed on the surface of the epitaxial layer 22. The protective layer The material of the first dielectric layer 531 and the first insulating layer 541 is the same and can be formed in the same deposition process. The hard film layer 532s and the second dielectric material layer 532' and the second insulating layer 542 are made of the same material, and the hard film layer 532s and the second dielectric material layer 532' and the second insulating layer 542 may be in the same deposition process. form.

Next, as shown in FIG. 8B, a selective etching step is performed to remove a portion of the second dielectric material layer 532' located in the element trench 520a and the hard film layer 532s on the protective layer 551 to be in the element trench 520a. A gate preset space 537 is defined therein.

Specifically, before the selective etching step is performed, the photoresist layer 58 is formed to cover the terminal electrode structure 54 in the termination region TR. The photoresist layer 58 also has an opening 580 to expose the element trench 520a of the active region AR.

Next, a two-stage selective etching step is performed. It should be noted that, in this embodiment, the materials of the first dielectric layer 531, the inter-electrode dielectric layer 536, and the third dielectric layer 533 are different from the second dielectric material layer 532', and thus The mask power is etched to define a gate preset space 537.

In detail, in the selective etching step of the first stage, the second dielectric material layer 532' and the hard film layer 532s are used as an etching power to remove a portion of the inter-electrode dielectric material layer located on the shielding electrode 535. 536', and an inter-electrode dielectric layer 536 having a thickness of about 200 to 300 nm is formed in the element trench 520a.

In performing the second-stage selective etching step, the first dielectric layer 531, the inter-electrode dielectric layer 536, and the third dielectric layer 533 are used as an etch mask power to remove a portion of the second portion located in the element trench 520a. A dielectric material layer 532' and a hard film layer 532s on the protective layer 551. Thereby, a gate preset space 537 can be defined in the element trench 520a.

In addition, it is specifically noted that after removing a portion of the second dielectric material layer 532' located in the device trench 520a, respectively, between the opposite sidewall faces of the first dielectric layer 531 and the inter-electrode dielectric layer 536. Two recessed areas are formed.

Next, as shown in FIG. 8C, a polysilicon structure is filled in the gate pre-set space 438 to form a gate electrode 534. Then, the base region 521 and the source region are sequentially formed. 522 and the line redistribution layer. For detailed steps of forming the base region 521, the source region 522, and the line redistribution layer, refer to the description of the previous embodiment, and details are not described herein again.

In summary, in the trench power semiconductor device of the present invention, the insulating layer surrounding the shielding electrode has first, second, and third dielectric layers made of different materials, and the gate electrode is sandwiched between 1. Between the second and third dielectric layers.

In the process of the trench gate structure, the shape and position of the gate electrode in the trench of the device can be predefined by a selective etching step, thereby avoiding the proximity of the first conductive layer and the second conductive layer to the shielding electrode. The side forms a tip end. Therefore, the trench power semiconductor device provided by the embodiment of the present invention can avoid reducing the withstand voltage of the gate electrode due to the tip effect.

In addition, the gate electrode and the shielding electrode are separated from each other by a third dielectric layer. Compared with the prior art, in the present invention, a thick third dielectric layer can be formed between the gate electrode and the shielding electrode to reduce the capacitance between the gate and the source.

Although the embodiments of the present invention have been disclosed as above, the present invention is not limited to the above-described embodiments, and those skilled in the art can make some modifications without departing from the scope of the present invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

220‧‧‧ drift zone

221‧‧‧basal area

222‧‧‧ source area

220a‧‧‧Component trench

23‧‧‧ Trench gate structure

235‧‧‧shading electrode

231‧‧‧First dielectric layer

231a‧‧‧First upper inner wall

231c‧‧‧Second upper inner wall

231b‧‧‧ lower inner wall

232‧‧‧Second dielectric layer

232a‧‧‧ first end

232b‧‧‧second end face

233‧‧‧ Third dielectric layer

234‧‧‧gate electrode

234a‧‧‧First conductive layer

234b‧‧‧Second conductive layer

251‧‧‧Protective layer

Claims (16)

A trench type power semiconductor device comprising: a substrate; an epitaxial layer on the substrate, wherein the epitaxial layer has at least one component trench formed therein; and a trench gate structure, Located in the trench of the device, wherein the trench gate structure comprises: a shielding electrode disposed in the trench of the component; a first dielectric layer disposed in the trench of the component and having a contour of the inner wall of the component trench, wherein the first dielectric layer has a first upper inner wall surface and a lower inner wall surface connected to the first upper inner wall surface; a second dielectric layer Covering at least the lower inner wall surface, wherein a material constituting the second dielectric layer is different from a material constituting the first dielectric layer; a gate electrode disposed in the trench of the element, wherein The gate electrode includes a first conductive layer, the first conductive layer covers the first upper inner wall surface, the first conductive layer has a thickness substantially the same as a thickness of the second dielectric layer, and the first a bottom end of a conductive layer is connected to the second dielectric layer a first end surface; and a third dielectric layer that covers the second dielectric layer and the inner surface of the first conductive layer, wherein the third dielectric layer surrounds the shielding electrode The shield electrode and the gate electrode are isolated from each other. The trench power semiconductor device of claim 1, further comprising a substrate region formed in the epitaxial layer and a source region formed over the substrate region, wherein the substrate region surrounds Said component trench. The trench power semiconductor device of claim 2, wherein the first end surface is equal to or lower than a plane of a lower edge of the base region. The trench power semiconductor device of claim 1, wherein the first dielectric layer has a second upper inner wall surface opposite to the first upper inner wall surface and connected to the lower inner wall surface, The gate electrode further includes a second conductive layer, wherein the second conductive layer and the first conductive layer are disposed face to face in the element trench and cover the second upper inner wall surface, and the second A bottom end of the conductive layer is connected to a second end surface of the second dielectric layer. The trench power semiconductor device of claim 4, wherein a portion of the shielding electrode overlaps the first conductive layer and the second conductive layer. The trench power semiconductor device of claim 4, wherein none of the shielding electrodes overlap the first conductive layer and the second conductive layer. The trench power semiconductor device of claim 4, wherein the gate electrode further comprises a third conductive layer connected between the first conductive layer and the second conductive layer, and the The three conductive layers are located on the shielding electrode and are electrically insulated from the shielding electrode. The trench power semiconductor device of claim 1, further comprising a terminal electrode structure, wherein the epitaxial layer further comprises at least one terminal trench formed in the epitaxial layer, the terminal electrode structure is located The terminal electrode structure includes: a terminal electrode disposed in the terminal trench; and a terminal dielectric layer disposed on an inner wall surface of the terminal trench and having the a substantially uniform contour of the inner wall surface, wherein the terminal dielectric layer comprises at least a first insulating layer, a second insulating layer and a third insulating layer stacked on the inner wall surface in sequence, wherein the second layer is formed The material of the insulating layer is different from the material constituting the first insulating layer, and the terminal electrode is electrically insulated from the epitaxial layer by the terminal dielectric layer. The trench power semiconductor device of claim 8, wherein the terminal electrode Extending from an upper half of the terminal trench to a lower half of the terminal trench. The trench type power semiconductor device according to claim 8, wherein a plane at which a tip end of the terminal electrode is located is lower than or equal to an end surface of the second insulating layer. The trench power semiconductor device of claim 8, further comprising a conductive layer, wherein an end surface of the second insulating layer is lower than a top surface of the first insulating layer and the third insulating layer, Forming a recessed region between the first insulating layer, the second insulating layer and the third insulating layer, the conductive layer is located in the recessed region, and the conductive layer and the first layer The two insulating layers have substantially the same thickness. The trench power semiconductor device of claim 1, further comprising: an interlayer dielectric layer on a surface of the epitaxial layer and covering the trench of the component, wherein the interlayer dielectric layer has at least one Xiao a conductive contact plug; and a conductive plug disposed through the interlayer dielectric layer, the conductive plug electrically contacting the epitaxial layer through the Schottky contact window to form a Schottky II Polar body. A trench type power semiconductor device comprising: a substrate; an epitaxial layer on the substrate, wherein the epitaxial layer has at least one terminal trench formed therein; and a terminal electrode structure located at the In the terminal trench, wherein the terminal electrode structure comprises: a terminal dielectric layer having a contour substantially conforming to an inner wall surface of the terminal trench, wherein the terminal dielectric layer is sequentially stacked on the a first insulating layer, a second insulating layer and a third insulating layer on the inner wall surface, wherein a material constituting the second insulating layer is different from a material constituting the first insulating layer, and the second insulating layer One end of the layer is lower than the first An insulating layer and a top surface of the third insulating layer to define a recessed region between the first insulating layer, the second insulating layer and the third insulating layer; a conductive layer located at the a recessed region; and a terminal electrode located in the terminal trench and isolated from the conductive layer by the third insulating layer. The trench power semiconductor device of claim 13, wherein a plane at which a tip end of the terminal electrode is located is equal to or lower than the end surface of the second insulating layer. The trench power semiconductor device of claim 13, wherein a portion of the terminal electrode overlaps the conductive layer. The trench power semiconductor device of claim 13, wherein the terminal electrode and the conductive layer do not overlap.