TWI587453B - Semiconductor structure and method of manufacturing the same - Google Patents

Description

Semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a semiconductor structure in which different types of isolation modes are provided for a channel layer, and a method of fabricating the same.

Semiconductor components are gradually becoming denser and smaller. With this trend, three-dimensional memory has been developed. In a typical three-dimensional memory semiconductor structure, the structure as a memory layer may also be used to provide a gate dielectric layer to the string select line. Therefore, during the writing/erasing of the memory cells, the gate dielectric layer for the series selection lines may also carry a charge. As such, additional circuitry is required to control the writing/erasing of the gate dielectric layer for the string select lines.

In the present invention, two isolation modes are provided. Therefore, the above problems can be avoided.

According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a stack formed on the substrate. The stack includes a plurality of first conductive layers and a plurality of first dielectric layers, and the first conductive layers and the first dielectric layers are alternately stacked with each other. The semiconductor structure further includes a second guide formed on the stack Electrical layer. The semiconductor structure also includes a plurality of openings through the second conductive layer and the stack. The semiconductor structure also includes a plurality of through structures formed in the openings, respectively. The through structures respectively include a memory layer, a gate dielectric layer, a channel layer, a dielectric material, and a pad. A memory layer and a gate dielectric layer are formed on the sidewalls of each of the openings. A channel layer is formed on the memory layer and the gate dielectric layer. The channel layer defines a space. The dielectric material and the pads are formed in a space defined by the channel layer, wherein the pads are positioned higher than the dielectric material. The channel layer and the stack are separated by a memory layer, and the channel layer and the second conductive layer are separated by a gate dielectric layer, and the memory layer and the gate dielectric layer have different compositions.

In accordance with some embodiments, a method of fabricating a semiconductor structure is provided. The method of fabricating such a semiconductor structure includes the following steps. A stack is formed on a substrate, wherein the stack includes a plurality of first layers and a plurality of second layers, the first layers and the second layers being alternately stacked with each other. A hard mask is formed on the stack. A plurality of openings are formed through the hard mask and the stack. A plurality of memory layers are formed on the sidewalls of the openings, respectively. A plurality of channel layers are formed on the memory layer, respectively. A dielectric material is filled in the opening. Forming a plurality of pads respectively on the open dielectric material. Remove the hard mask. Remove the memory layer beyond the complex portion of the stack. A plurality of gate dielectric layers respectively on the channel layer are formed. A second conductive layer is formed on the stack. The channel layer and the stack are separated by a memory layer, and the channel layer and the second conductive layer are separated by a gate dielectric layer, and the memory layer and the gate dielectric layer have different compositions.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

102‧‧‧Substrate

104‧‧‧Stacking

106, 106 (B) ‧ ‧ first conductive layer

108, 108 (B) ‧ ‧ first dielectric layer

110‧‧‧Second conductive layer

112‧‧‧ openings

114‧‧‧through structure

116‧‧‧ memory layer

122‧‧‧gate dielectric layer

124‧‧‧Channel layer

126‧‧‧ dielectric materials

128‧‧‧ pads

130‧‧‧Second dielectric layer

132‧‧‧ Third conductive layer

134‧‧‧Connecting parts

136‧‧‧ lining

216‧‧‧ memory layer

224‧‧‧channel layer

302‧‧‧Substrate

304‧‧‧Stacking

306‧‧‧ first floor

308, 308 (T) ‧ ‧ second floor

310‧‧‧hard mask

312‧‧‧ openings

314‧‧‧ memory layer

320‧‧‧channel layer

322‧‧‧ dielectric materials

324‧‧‧ pads

326‧‧‧gate dielectric layer

328‧‧‧Second conductive layer

330‧‧‧Second dielectric layer

332‧‧‧through holes

334‧‧‧ lining

336‧‧‧Electrical materials

338‧‧‧Connecting parts

340‧‧‧ Third conductive layer

402‧‧‧Substrate

404‧‧‧Stacking

406‧‧‧ first floor

408‧‧‧ second floor

410‧‧‧Second conductive layer

412‧‧‧hard mask

414‧‧‧ openings

416‧‧‧ memory layer

422‧‧‧channel layer

424‧‧‧ dielectric materials

426‧‧‧ pads

428‧‧‧gate dielectric layer

430‧‧‧Second dielectric layer

432‧‧‧through holes

434‧‧‧ lining

436‧‧‧Electrical materials

438‧‧‧Connecting parts

440‧‧‧ Third conductive layer

2101‧‧‧Sequence selection line

2102‧‧‧ Grounding selection line

1181~1184‧‧‧Oxide layer

1201~1203‧‧‧ nitride layer

3140‧‧‧ memory layer

3161~3164‧‧‧Oxide layer

3181~3183‧‧‧ nitride layer

3200‧‧‧ channel layer

3220‧‧‧ dielectric materials

3240‧‧‧Electrical materials

3260‧‧‧Oxide layer

4160‧‧‧ memory layer

4181~4184‧‧‧Oxide layer

4201~4203‧‧‧ nitride layer

4220‧‧‧Channel layer

4240‧‧‧ dielectric materials

4260‧‧‧Electrical materials

4280‧‧‧Oxide layer

S‧‧‧ Space

FIG. 1 illustrates a semiconductor structure in accordance with an embodiment.

FIG. 2 illustrates another semiconductor structure in accordance with an embodiment.

3A-3P illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.

4A to 4O illustrate another method of fabricating a semiconductor structure in accordance with an embodiment.

Various embodiments will be described in more detail below with reference to the drawings. For the sake of clarity, a three-dimensional vertical gate reverse (NAND) memory structure is exemplarily described. However, the semiconductor structure according to the embodiment is not limited thereto.

It should be noted that, for the sake of clarity, the elements in the drawings may not reflect their actual dimensions. Moreover, in some of the figures, elements that are not discussed in detail may be omitted.

It is to be understood that the expressions are used herein to describe the exemplary embodiments and are not intended to limit the invention. For example, the singular forms "a" and "the" are intended to include the plural. Moreover, the steps involved in one method need not be performed in a particular order. Where possible, one step can be performed before, after, or simultaneously with another step.

It is contemplated that elements and features of an embodiment may also be present in other embodiments for the preferred embodiments, and the same description is omitted.

Please refer to FIG. 1, which provides a semiconductor structure in accordance with an embodiment. The semiconductor structure includes a substrate 102 and a stack 104 formed on the substrate 102. The stack 104 includes a plurality of first conductive layers 106 and a plurality of first dielectric layers 108, and the first conductive layer 106 and the first dielectric layer 108 are alternately stacked with each other. The first conductive layer 106 may be formed of a material such as a p-type heavily doped polysilicon or a metal. The first dielectric layer 108 can be formed of an oxide. The semiconductor structure also includes a second conductive layer 110 formed on the stack 104. The second conductive layer 110 may be formed of a p-type or n-type heavily doped polysilicon, typically formed of an n-type heavily doped polysilicon. The semiconductor structure also includes a plurality of openings 112 that pass through the second conductive layer 110 and the stack 104. The semiconductor structure also includes a plurality of through structures 114 formed in openings 112, respectively.

The through structure 114 includes a memory layer 116, a gate dielectric layer 122, a channel layer 124, a dielectric material 126, and a pad 128. A memory layer 116 and a gate dielectric layer 122 are formed on sidewalls of each of the openings 112. In some embodiments, the gate dielectric layer 122 is positioned higher than the memory layer 116. The memory layer 116 and the gate dielectric layer 122 have different compositions. For example, memory layer 116 can have an oxide/nitride/oxide (ONO) structure, an oxide/nitride/oxide/nitride/oxide (ONONO) structure, an oxide/nitride/oxide/ Nitride/oxide/nitride/oxide (ONONONO) structure, yttrium oxynitride (SiON)/yttrium nitride (SiN)/oxide structure, or any other suitable tunneling/capturing/blocking structure. In FIG. 1, the memory layer 116 is depicted as having an ONONONO structure. That is, the memory layer 116 includes oxide layers 1181 to 1184 and nitride layers 1201 to 1203, wherein the oxide layer 1181, the nitride layer 1201 and the oxide layer 1182 constitute a tunneling structure, and the nitride layer 1202 constitutes a trapping structure and oxidizes. The material layer 1183, the nitride layer 1203, and the oxide layer 1184 constitute a barrier structure. The gate dielectric layer 122 can be a layer formed of an oxide. through The via layer 124 is formed on the memory layer 116 and the gate dielectric layer 122. Channel layer 124 may be formed of undoped polysilicon. The channel layer 124 defines a space S, that is, a residual space of the opening 112. Dielectric material 126 and pads 128 are formed in space S defined by channel layer 124, with pads 128 being positioned higher than dielectric material 126. In some embodiments, the level of the upper surface of the dielectric material 126 is higher than the upper surface of the stack 104. Dielectric material 126 can be an oxide. The pad 128 may be formed of an n-type heavily doped polysilicon. The channel layer 124 and the stack 104 are isolated (whether in space or electrically) by the memory layer 116, and the channel layer 124 and the second conductive layer 110 are isolated by the gate dielectric layer 122. In some embodiments, channel layer 124 and second conductive layer 110 are only isolated by gate dielectric layer 122.

According to some embodiments, the bottom first dielectric layer 108 (B) may be an oxide buried layer, the bottom first conductive layer 106 (B) may include a ground select line, and the other first conductive layers 106 may include words Yuan line. For memory structures, the memory cell system is defined at the intersection of the word line and the channel layer. Moreover, the second conductive layer 110 can include a tandem select line, and the via layer 124 and the tandem select line of at least one of the through structures 114 are isolated by the gate dielectric layer 122 of the at least one of the through structures 114.

In some embodiments, such as in an embodiment applied to a gate all-around (GAA) type of memory structure, the opening 112 is a hole. In this case, the entire first conductive layer 106 (B) can serve as a ground selection line, the other first conductive layers 106 can serve as a word line, and the entire second conductive layer 110 can serve as a string. Column selection line.

In some embodiments, such as in an embodiment applied to a single gate vertical channel (SGVC) type memory structure, the opening 112 is a trench. The stack 104 and the second conductive layer 110 may both be divided by trenches In the plural parallel part. In such a case, the bottom first conductive layer 106 (B) includes a plurality of ground select lines, the other first conductive layers 106 respectively comprise complex digital line lines, and the second conductive layer 110 includes a plurality of series select lines.

The semiconductor structure can also include a second dielectric layer 130, a third conductive layer 132, a plurality of connectors 134, and other typical components (not shown). The second dielectric layer 130 is formed on the second conductive layer 110. The second dielectric layer 130 may be formed of an oxide. The third conductive layer 132 is formed on the second dielectric layer 130. The third conductive layer 132 may be formed of a metal. The third conductive layer 132 can include a plurality of bit lines. Each of the connectors 134 connects the individual wires to the corresponding pads 128. The connectors 134 can each include a liner 136 to compensate for overlay shifts in the process.

Please refer to FIG. 2, which provides another semiconductor structure in accordance with an embodiment. In the semiconductor structure shown in FIG. 2, the opening 112 is a trench, and both the stack 104 and the second conductive layer 110 are divided into a plurality of parallel portions by the trench. In the semiconductor structure shown in FIG. 2, the memory layer 216 and the channel layer 224 located in one trench are formed in a U shape, and the second conductive layer 110 includes a series of select lines located on two sides of the trench. 2101 and a ground selection line 2102. The channel layer 224 and the string select line 2101 of at least one of the through structures 114 are isolated by the gate dielectric layer 122 of the at least one of the through structures 114. The channel layer 224 and the ground selection line 2102 of at least one of the through structures 114 are isolated by the gate dielectric layer 122 of the at least one of the structures 114. Other aspects, features, and details of the semiconductor structure shown in FIG. 2 are similar to those described with reference to the semiconductor structure shown in FIG. 1.

Next, a method of manufacturing the semiconductor structure will be explained. 3A-3P illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.

Referring to FIG. 3A, a substrate 302 is provided. A stack 304 is formed on the substrate 302. The stack 304 includes a plurality of first layers 306 and a plurality of second layers 308, and the first layer 306 and the second layer 308 are alternately stacked with each other. In some embodiments, the first layer 306 is a first conductive layer and the second layer 308 is a first dielectric layer. The first conductive layer may be formed of a p-type heavily doped polysilicon, and the first dielectric layer may be formed of an oxide. In some embodiments, the first layer 306 is a sacrificial layer and the second layer 308 is a first dielectric layer. The sacrificial layer may be formed of a nitride and the first dielectric layer may be formed of an oxide. Furthermore, in the next step, in particular after forming the through structure, the sacrificial layer will be replaced by a conductive material. Therefore, a plurality of first conductive layers can be formed, wherein the first conductive layer and the first dielectric layer are alternately stacked with each other. In the present method, in the case where the second layer 308 is formed of an oxide, the thickness of the top second layer 308 (T) is greater than the other second layers 308.

A hard mask 310 is formed on the stack 304. The hard mask 310 can serve as a stop layer in the next chemical mechanical planarization (CMP) process. The hard mask 310 may be a layer formed of tantalum nitride. Alternatively, the hard mask 310 can include a tantalum nitride layer and an oxide layer. The tantalum nitride layer can avoid collapse or bending of a linear stack having a high aspect ratio. In the method, after the hard mask 310 is removed, a second conductive layer, which may include at least one series of select lines, may be formed at the same location as the hard mask 310. Thus, the thickness of the hard mask 310 can depend on the desired string selection line characteristics.

Referring to FIG. 3B, a plurality of openings 312 are formed through which the openings 312 pass through the hard mask 310 and the stack 304. More specifically, the substrate 302 can be exposed by the opening 312. The opening 312 can be a hole or a groove or the like. In the case where the opening 312 is a hole, the method can be applied to a memory structure of a wraparound gate type. And in Where the opening 312 is a trench, the method can be applied to a single gate vertical channel type memory structure. Furthermore, the method can be applied to a source structure of a source of a bottom source.

Thereafter, a plurality of memory layers 314 are formed on the sidewalls of the openings 312, respectively. A plurality of channel layers 320 are formed on the memory layer 314, respectively. A dielectric material 322 is filled in the opening 312. A plurality of pads 324 are formed on the dielectric material 322 of the openings 312, respectively.

Referring to FIG. 3C, a memory layer 3140 is conformally formed on the hard mask 310 and in the opening 312. This can be done by a deposition process. The memory layer 3140 can have an ONO structure, an ONONO structure, an ONONONO structure, a hafnium oxynitride/tantalum nitride/oxide structure, or any other suitable tunneling/capturing/blocking structure. In FIG. 3C, the memory layer 3140 is depicted as having an ONONONO structure. That is, the memory layer 3140 includes oxide layers 3161 to 3164 and nitride layers 3181 to 3183, wherein the oxide layer 3161, the nitride layer 3181, and the oxide layer 3162 constitute a tunneling structure, and the nitride layer 3182 constitutes a trapping structure and oxidizes. The material layer 3163, the nitride layer 3183, and the oxide layer 3164 constitute a barrier structure. A channel layer 3200 is formed on the memory layer 3140. The channel layer 3200 can be formed by deposition of undoped polysilicon. Next, a dielectric material 3220 is formed over the channel layer 3200 and filled into the residual space of the opening 312. This can be done by a deposition process. Dielectric material 3220 can be an oxide. In some embodiments, voids or gaps may be formed within the dielectric material 3220 and facilitate reducing the coupling rate of two adjacent channel layers.

Referring to FIG. 3D, a planarization process, such as a CMP process, is performed to remove portions of dielectric material 3220 on channel layer 3200. Next, the dielectric material The top portion of 3220 in opening 312 is also removed, as shown in Figure 3E. This can be done by a dip process using dilute hydrofluoric acid (DHF) or BOE etchant. The dielectric material 322 remaining in each of the openings 312 has a higher level than the upper surface of the upper surface of the stack 304. Further, the level of the upper surface of the dielectric material 322 may be lower than the upper surface of the hard mask 310.

Referring to FIG. 3F, a conductive material 3240 is formed on the channel layer 3200 and filled into the residual space of the opening 312, for example, by deposition. Conductive material 3240 can be an n-type heavily doped polysilicon. Next, as shown in FIG. 3G, a planarization process such as a CMP process is performed and stopped on the hard mask 310. As such, the memory layer 3140 is divided into a plurality of memory layers 314 formed on the sidewalls of the openings 312, respectively. The channel layer 3200 is divided into a plurality of channel layers 320 formed on the memory layer 314, respectively. In addition, a plurality of pads 324 are formed in the openings 312, respectively, on the dielectric material 322.

Thereafter, the hard mask 310 and memory layer 314 are removed to extend beyond the plurality of portions of the stack 304. More specifically, the step of removing the portion of the memory layer 314 that extends beyond the stack 304 can include a nitride removal step and an oxide removal step, and the step of removing the hard mask 310 and the nitride removal step Can be carried out simultaneously. However, the method is not limited to this.

Referring to FIG. 3H, a nitride removal step is performed, for example, by an immersion process using phosphoric acid (H ₃ PO ₄ ). Thereby, the nitride layers 3181 to 3183 of the memory layer 314 can be removed to extend beyond the portion of the stack 304. Further, the hard mask 310 formed of tantalum nitride can also be removed.

Please refer to Figure 3I for the oxide removal step, which is for example borrowed It is carried out by an dipping process using DHF. Thus, the oxide layer 3161~3164 of the memory layer 314 can be removed to extend beyond the portion of the stack 304. In the case where the memory layer 314 includes a hafnium oxynitride layer, portions of the hafnium oxynitride layer extending beyond the stack 304 can be partially removed during both the nitride removal step and the oxide removal step, and After these two steps are completed, they are completely removed. According to some embodiments, in order to completely destroy the portion of the memory layer 314 that extends beyond the stack 304, the nitride removal step and the oxide removal step may be repeated several times. In some embodiments, the fully removed memory layer 314 extends beyond the portion of the stack 304. Alternatively, the remaining nitride layer of the memory layer 314 extending beyond the portion of the stack 304 has a thickness of less than 30 Å, preferably less than or equal to 25 Å. For example, the remaining portion may not capture the charged oxide layer 3161, the nitride layer 3181, and the oxide layer 3162 without departing from the scope of the embodiments.

Thereafter, a plurality of gate dielectric layers 326 are formed, and gate dielectric layers 326 are respectively disposed on the channel layer 320. The gate dielectric layer can be formed by an oxidation process. For example, as shown in FIG. 3J, an oxidation process of the tantalum material, such as a thermal oxidation process or an in situ steam generation (ISSG) oxidation process, can be performed. Thus, the oxide layer 3260 is conformally formed in portions of the channel layer 320 and the pads 324 that are exposed outside of the stack 304. According to some embodiments, the oxide layer 3260 may have a thickness of about 70 Å to 100 Å. Alternatively, a deposition process can be performed while an oxide layer is conformally formed over the entire structure. A portion of oxide layer 3260 on channel layer 320 acts as gate dielectric layer 326. In some embodiments, other portions of oxide layer 3260, such as portions formed on pads 324, may be removed.

Referring to FIG. 3K, after forming the gate dielectric layer 326, a second conductive layer 328 is formed on the stack 304. As a result, the channel layer 320 and the stack The 304 is isolated by the memory layer 314, and the channel layer 320 and the second conductive layer 328 are isolated by a gate dielectric layer 326 having a composition different from that of the memory layer 314. According to some embodiments, the second conductive layer 328 may be formed of a p-type or n-type heavily doped polysilicon, preferably an n-type heavily doped polysilicon. This can be done, for example, by a deposition process and a subsequent CMP process. Alternatively, metal can be used to form the second conductive layer 328. For example, the second conductive layer 328 can have a titanium/titanium nitride (TiN)/tungsten structure. Moreover, in some embodiments, the second conductive layer 328 and the pads 324 can be self-aligned to reduce electrical resistance. The second conductive layer 328 can include a string selection line. The second conductive layer 328 can also include a ground selection line.

Thereafter, other typical processes for the fabrication of semiconductor structures can be performed. For example, referring to FIG. 3L, a second dielectric layer 330 can be formed on the second conductive layer 328 and the pad 324 as an interlayer dielectric. This can be done by a deposition process and a subsequent CMP process. The second dielectric layer 330 may be formed of an oxide. Next, as shown in FIG. 3M, a plurality of through holes 332 corresponding to the pads 324 are formed. Referring to FIG. 3N, a plurality of liners 334 are formed on the sidewalls of the through holes 332, respectively. This can be done by a deposition process and a subsequent etching process. The liner 334 may be formed of a material such as an oxide or tantalum nitride. Next, as shown in FIG. 3O, a conductive material 336 is filled in the through hole 332. This can be done by a chemical vapor deposition (CVD) process and a subsequent CMP process. Conductive material 336 can include titanium, titanium nitride, and tungsten. As such, a plurality of connectors 338 including a liner 334 and a conductive material 336 are formed. They are used to provide an electrical connection between the pads 324 and a third conductive layer 340 formed in the next step. Referring to FIG. 3P, a third conductive layer 340 is formed on the second dielectric layer 330. The third conductive layer 340 may be formed of a metal. The third conductive layer 340 can include a complex Digital line. In such a case, the pads 324 can be bit line pads and connected to the bit lines by connectors 338.

4A to 4O illustrate another method of fabricating a semiconductor structure in accordance with an embodiment.

Referring to FIG. 4A, a substrate 402 is provided. A stack 404 is formed on the substrate 402. The stack 404 includes a plurality of first layers 406 and a plurality of second layers 408, and the first layer 406 and the second layer 408 are alternately stacked with each other. In some embodiments, the first layer 406 is a first conductive layer and the second layer 408 is a first dielectric layer. The first conductive layer may be formed of a p-type heavily doped polysilicon, and the first dielectric layer may be formed of an oxide. In some embodiments, the first layer 406 is a sacrificial layer and the second layer 408 is a first dielectric layer. The sacrificial layer may be formed of a nitride and the first dielectric layer may be formed of an oxide. Furthermore, in the next step, in particular after forming the through structure, the sacrificial layer will be replaced by a conductive material. Therefore, a plurality of first conductive layers can be formed, wherein the first conductive layer and the first dielectric layer are alternately stacked with each other.

Next, a second conductive layer 410 is formed on the stack 404. The second conductive layer 410 may be formed of a p-type or n-type heavily doped polysilicon, preferably formed of an n-type heavily doped polysilicon. The second conductive layer 410 can be used to provide a string select line and a ground select line (the ground select line is selectively provided).

After the second conductive layer 410 is formed, a hard mask 412 is formed on the second conductive layer 410. The hard mask 412 can serve as a stop layer in the next CMP process. The hard mask 412 can be a layer formed of tantalum nitride. Alternatively, the hard mask 412 can include a tantalum nitride layer and an oxide layer. The tantalum nitride layer can avoid collapse or bending of a linear stack having a high aspect ratio.

Referring to FIG. 4B, a plurality of openings 414 are formed through which the openings 414 pass through the hard mask 412, the second conductive layer 410, and the stack 404. More specifically, the substrate 402 can be exposed by the opening 414. Opening 414 can be a pattern of holes or grooves. Where the opening 414 is a hole, the method can be applied to a wraparound gate type memory structure. Where the opening 414 is a trench, the method can be applied to a single gate vertical channel type memory structure. Furthermore, the method can be applied to a memory structure of a source type at the bottom.

Thereafter, a plurality of memory layers 416 are formed on the sidewalls of the openings 414, respectively. A plurality of channel layers 422 are formed on the memory layer 416, respectively. A dielectric material 424 is filled in the opening 414. A plurality of pads 426 are formed on the dielectric material 424 of the openings 414, respectively.

Referring to FIG. 4C, a memory layer 4160 is conformally formed on the hard mask 412 and in the opening 414. This can be done by a deposition process. The memory layer 4160 can have an ONO structure, an ONONO structure, an ONONONO structure, a hafnium oxynitride/tantalum nitride/oxide structure, or any other suitable tunneling/capturing/blocking structure. In FIG. 4C, the memory layer 4160 is depicted as having an ONONONO structure. That is, the memory layer 4160 includes oxide layers 4181 to 4184 and nitride layers 4201 to 4203, wherein the oxide layer 4181, the nitride layer 4201 and the oxide layer 4182 constitute a tunneling structure, and the nitride layer 4202 constitutes a trapping structure and oxidizes. The object layer 4183, the nitride layer 4203, and the oxide layer 4184 constitute a barrier structure. In some embodiments, such as in an embodiment where the source is in a bottom type memory structure, the removed memory layer 4160 is formed at a portion of the bottom of the opening 414 and exposes the substrate 402. Next, a channel layer 4220 is formed on the memory layer 4160. Channel layer 4220 can be formed by deposition of undoped polysilicon. Next, formed on the channel layer 4220 A dielectric material 4240 is filled into the residual space of the opening 414. This can be done by a deposition process. Dielectric material 4240 can be an oxide. In some embodiments, voids or gaps may be formed in the dielectric material 4240 and facilitate reducing the coupling ratio of two adjacent channel layers.

Referring to FIG. 4D, a planarization process, such as a CMP process, is performed to remove portions of dielectric material 4240 on channel layer 4220. Next, the top portion of the dielectric material 4240 in the opening 414 is also removed, as shown in FIG. 4E. This can be done by an dipping process using a DHF or BOE etchant. The dielectric material 424 remaining in each of the openings 414 has an upper surface that is higher in level than the upper surface of the stack 404. Further, the level of the upper surface of the dielectric material 424 may be lower than the upper surface of the second conductive layer 410.

Referring to FIG. 4F, a conductive material 4260 is formed on the channel layer 4220 and filled into the residual space of the opening 414, for example, by deposition. Conductive material 4260 can be an n-type heavily doped polysilicon. Next, as shown in FIG. 4G, a planarization process such as a CMP process is performed and stopped on the hard mask 412. As such, the memory layer 4160 is divided into a plurality of memory layers 416 formed on the sidewalls of the openings 414, respectively. The channel layer 4220 is divided into a plurality of channel layers 422 formed on the memory layer 416, respectively. In addition, a plurality of pads 426 are formed in openings 414, respectively, over dielectric material 424.

Thereafter, the hard mask 412 and the memory layer 416 are removed to extend beyond the plurality of portions of the stack 404. More specifically, the step of removing the portion of the memory layer 416 that extends beyond the stack 404 can include a nitride removal step and an oxide removal step, and the step of removing the hard mask 412 and the nitride removal step Can be carried out simultaneously. However, the method is not limited to this.

Referring to FIG. 4H, a nitride removal step is performed, which is performed, for example, by an impregnation process using phosphoric acid. Thus, the nitride layers 4201 - 4203 of the memory layer 416 can be removed to extend beyond the portion of the stack 404. In addition, the hard mask 412 formed of tantalum nitride can also be removed.

Referring to FIG. 4I, an oxide removal step is performed, for example, by an dipping process using DHF. Thus, the oxide layers 4181 - 4184 of the memory layer 416 can be removed to extend beyond the portion of the stack 404. Where the memory layer 416 includes a hafnium oxynitride layer, portions of the hafnium oxynitride layer extending beyond the stack 404 can be partially removed during both the nitride removal step and the oxide removal step, and After these two steps are completed, they are completely removed. According to some embodiments, in order to completely destroy the portion of the memory layer 416 that extends beyond the stack 404, the nitride removal step and the oxide removal step may be repeated several times. In some embodiments, the fully removed memory layer 416 extends beyond the portion of the stack 404. Alternatively, the nitride layer remaining in the portion of the memory layer 416 that extends beyond the stack 404 has a thickness of less than 30 Å, preferably less than or equal to 25 Å. For example, the remaining portion may not capture the charged oxide layer 4181, nitride layer 4201, and oxide layer 4182 without departing from the scope of the embodiments.

Thereafter, a plurality of gate dielectric layers 428 are formed, and gate dielectric layers 428 are respectively disposed on the channel layer 422. This can be done by an oxidation process such as a thermal oxidation process or an ISSG oxidation process followed by a deposition process. Thus, the oxide layer 4280 is conformally formed over the entire structure as shown in FIG. 4J. The oxide layer formed by the oxidation process can have a thickness of about 70 Å and provides a better quality to the gate dielectric layer 428. However, the oxide layer 4280 can be formed only by a deposition process. A portion of oxide layer 4280 over channel layer 422 acts as gate dielectric layer 428. In some embodiments, The other portions of the oxide layer 4280 are removed.

Since memory layer 416 and gate dielectric layer 428 have different compositions, channel layer 422 can be isolated from stack 404 and second conductive layer 410 by different means.

Thereafter, other typical processes for the fabrication of semiconductor structures can be performed. For example, referring to FIG. 4K, a second dielectric layer 430 can be formed on the second conductive layer 410 and the pads 426 as an interlayer dielectric. This can be done by a deposition process and a subsequent CMP process. The second dielectric layer 430 may be formed of an oxide. Next, as shown in FIG. 4L, a plurality of through holes 432 corresponding to the pads 426 are formed. Referring to FIG. 4M, a plurality of liners 434 are formed on the sidewalls of the through holes 432, respectively. This can be done by a deposition process and a subsequent etching process. The liner 434 may be formed of a material such as an oxide or tantalum nitride. Next, as shown in FIG. 4N, a conductive material 436 is filled in the through hole 432. This can be done by a CVD process and a subsequent CMP process. Conductive material 436 can include titanium, titanium nitride, and tungsten. As such, a plurality of connectors 438 including a liner 434 and a conductive material 436 are formed. They are used to provide an electrical connection between the pads 426 and a third conductive layer 440 formed in the next step. Referring to FIG. 4O, a third conductive layer 440 is formed on the second dielectric layer 430. The third conductive layer 440 may be formed of a metal. The third conductive layer 440 can include a plurality of bit lines. In such a case, the pads 426 can be bit line pads and connected to the bit lines by connectors 438.

In summary, according to an embodiment, two ways can be provided to separate the channel layer and the word line, and the separation channel layer and the string selection line. Therefore, the control of the serial selection line will not be adversely affected by, for example, the control of the memory cells. Therefore, no additional circuitry is needed to control the write/erase of the gate dielectric layer for the series select lines.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102‧‧‧Substrate

104‧‧‧Stacking

106, 106 (B) ‧ ‧ first conductive layer

108, 108 (B) ‧ ‧ first dielectric layer

110‧‧‧Second conductive layer

112‧‧‧ openings

114‧‧‧through structure

116‧‧‧ memory layer

122‧‧‧gate dielectric layer

124‧‧‧Channel layer

126‧‧‧ dielectric materials

128‧‧‧ pads

130‧‧‧Second dielectric layer

132‧‧‧ Third conductive layer

134‧‧‧Connecting parts

136‧‧‧ lining

1181~1184‧‧‧Oxide layer

1201~1203‧‧‧ nitride layer

S‧‧‧ Space

Claims (10)

A semiconductor structure comprising: a substrate; a stack formed on the substrate, wherein the stack includes a plurality of first conductive layers and a plurality of first dielectric layers, the first conductive layers and the first dielectric layers being mutually Alternatingly stacking; a second conductive layer formed on the stack; a plurality of openings passing through the second conductive layer and the stack; and a plurality of through structures respectively formed in the openings, wherein the through structures respectively comprise: a memory layer and a gate dielectric layer are formed on sidewalls of each of the openings; a channel layer is formed on the memory layer and the gate dielectric layer, and defines a space; and a dielectric material and a a pad formed in the space defined by the channel layer, wherein the pad is positioned higher than the dielectric material; wherein the channel layer and the stack are separated by the memory layer, the channel layer and the second conductive The layer is isolated by the gate dielectric layer, and the memory layer and the gate dielectric layer have different compositions; wherein the semiconductor structure does not include a nitride layer between the channel layer and the second conductive layer, or only includes small A nitride layer of a thickness of 30Å. The semiconductor structure of claim 1, wherein the upper surface of the dielectric material of each of the through structures has a higher level than the upper surface of the stack. The semiconductor structure of claim 1, wherein the through structures The channel layer and the second conductive layer of each are isolated by the gate dielectric layer of each of the through structures. The semiconductor structure of claim 1, wherein the second conductive layer comprises a series of select lines, and the channel layer and the string select line of at least one of the through structures are The gate dielectric layer of the at least one of the structures is isolated. The semiconductor structure of claim 1, wherein the memory layer of each of the through structures has an ONO structure, an ONONO structure, an ONONONO structure, or a hafnium oxynitride/tantalum nitride/oxide structure. The gate dielectric layer of each of the structures is a layer formed of an oxide, and wherein the gate dielectric layer of each of the through structures is positioned higher than the memory layer of each of the through structures. A method of fabricating a semiconductor structure, comprising: forming a stack on a substrate, wherein the stack comprises a plurality of first layers and a plurality of second layers, the first layers and the second layers being alternately stacked on each other; on the stack Forming a hard mask; forming a plurality of openings through the hard mask and the stack; forming a plurality of memory layers respectively on sidewalls of the openings; forming a plurality of channel layers respectively on the memory layers; Filling a dielectric material in the opening; forming a plurality of pads respectively on the dielectric material in the openings; removing the hard mask; removing the memory layers beyond a plurality of portions of the stack; forming respectively a plurality of gate dielectric layers on the channel layers; and forming a second conductive layer on the stack; wherein the channel layers and the stack are isolated by the memory layers, the channels The layer and the second conductive layer are isolated by the gate dielectric layers, and the memory layers and the gate dielectric layers have different compositions. The method of fabricating a semiconductor structure according to claim 6, wherein in the step of forming the stack, a thickness of a second layer of the second layer is greater than a thickness of the second layer of the second layer And wherein the step of forming the second conductive layer is performed after the step of forming the gate dielectric layers. The method of fabricating a semiconductor structure according to claim 7, wherein in the step of forming the gate dielectric layers, the gate dielectric layers are formed by an oxidation process. The method of fabricating a semiconductor structure according to claim 6, wherein the step of forming the second conductive layer is performed before the step of forming the hard mask, and the hard mask is formed on the second conductive layer And wherein in the step of forming the openings, the openings pass through the hard mask, the second conductive layer, and the stack. The method of fabricating a semiconductor structure according to claim 9, wherein in the step of forming the gate dielectric layers, the gate dielectric layers are formed by an oxidation process and a subsequent deposition process.