TWI581685B - Circuit structure and manufacturing method thereof - Google Patents

Description

Line structure and manufacturing method thereof

The present invention relates to a circuit structure and a method of fabricating the same, and more particularly to a circuit structure for a Flip Chip Chip Scale Package (FCCSP) and a method of fabricating the same.

Compared to the Fan Out Wafer Level Package (FOWLP), the wafer size flip chip package (FCCSP) requires higher fabrication costs because the floating wafer level package (FOWLP) does not need to be used. The use of the carrier plate can effectively and significantly reduce the production cost. Therefore, based on the trend of low cost and high added value, how to effectively simplify the manufacturing process and reduce the production cost has become an urgent problem to be overcome in the wafer size flip chip package (FCCSP).

The invention provides a circuit structure and a manufacturing method thereof, which can simplify the process flow of the circuit structure and have a lower process cost.

A method of fabricating a wiring structure of the present invention includes the following fabrication steps. A two patterned circuit layer is formed on a core layer. The patterned circuit layers are respectively located on opposite surfaces of the core layer. A patterned insulating layer is formed on each of the patterned circuit layers. The patterned insulating layer exposes a portion of the patterned wiring layer, respectively. The core layer is removed to expose an upper surface of each patterned wiring layer and a top surface of each patterned insulating layer. The upper surface of each patterned wiring layer is aligned with the top surface of each patterned insulating layer.

In an embodiment of the invention, the core layer includes a core dielectric layer, two first copper foil layers, and two second copper foil layers. The first copper foil layers are respectively located on opposite side surfaces of the core dielectric layer, and the second copper foil layers are respectively located on the first copper foil layer, and each first copper foil layer has a thickness greater than each second copper foil The thickness of the layer.

In an embodiment of the present invention, the method for fabricating the circuit structure further includes: after forming a patterned insulating layer on each patterned circuit layer, and providing two supporting plates before removing the core layer, respectively Pressed onto the patterned insulating layer.

In an embodiment of the invention, the method for fabricating the circuit structure further includes: after each of the patterned circuit layers is formed with a patterned insulating layer, and before each of the patterned layers is removed, each patterned insulating layer is removed. A sub-layer is formed on the layer, and the seed layer covers the patterned insulating layer and the patterned circuit layer exposed by the patterned insulating layer. A patterning process is performed for each seed layer to form a patterned seed layer, respectively. A patterned build-up layer is formed on each of the patterned seed layers, and the patterned build-up layer is respectively disposed on the patterned seed layer, and is connected to the patterned circuit layer through the patterned seed layer. Formed on each patterned layered layer A patterned build-up insulating layer, the patterned build-up insulating layer exposes a portion of the patterned build-up wiring layer, respectively.

In an embodiment of the present invention, the method for fabricating the circuit structure further includes: after forming a patterned build-up insulating layer on each patterned build-up layer, and providing two before removing the core layer The support plates are respectively pressed onto the patterned build-up insulating layer.

The wiring structure of the present invention includes a patterned wiring layer and a patterned insulating layer. The patterned insulating layer covers a portion of the patterned wiring layer, wherein an upper surface of the patterned wiring layer is aligned with a top surface of the patterned insulating layer.

In an embodiment of the invention, the circuit structure further includes: a support plate disposed on a bottom surface of the patterned insulating layer.

In an embodiment of the invention, the circuit structure further includes: a patterned seed layer covering the patterned insulating layer and the partially patterned circuit layer; and a patterned build-up circuit layer disposed on the patterned seed layer Wherein the patterned build-up wiring layer is connected to the patterned wiring layer through the patterned seed layer; and a patterned build-up insulating layer exposes a portion of the patterned build-up wiring layer.

In an embodiment of the invention, the circuit structure further includes: a support plate disposed on a bottom surface of the patterned build-up insulating layer.

In an embodiment of the invention, the patterned seed layer is an electroplated copper layer.

Based on the above, the method for fabricating the wiring structure of the present invention can produce a wiring structure having only a single layer of wiring layers, thereby greatly reducing the manufacturing process of the wiring structure. And can effectively reduce the cost of the process.

The above described features and advantages of the invention will be apparent from the following description.

100a‧‧‧Line structure

110‧‧‧ core layer

111, 113‧‧‧ surface

112‧‧‧ core dielectric layer

114a, 114b‧‧‧ first copper foil layer

116a, 116b‧‧‧ second copper foil layer

120a, 120b‧‧‧ patterned circuit layer

122‧‧‧ upper surface

130‧‧‧layer of insulating material

130a, 130b, 130c, 130d‧‧‧ patterned insulation

132, 132'‧‧‧ top surface

134‧‧‧ bottom surface

140a, 140b, 140c, 140d‧‧‧ support plates

142a, 142b, 142c, 142d‧‧‧B-level insulation

144a, 144b, 144c, 144d, 146a, 146b, 146c, 146d‧‧‧ copper foil layer

150‧‧‧ seed layer

150a, 150b‧‧‧ patterned seed layer

160a, 160b‧‧‧ patterned layered circuit layer

162a, 162b‧‧‧ patterned circuit layer

164a, 164b‧‧‧ conductive through holes

170a, 170b‧‧‧ patterned patterned insulation

172‧‧‧ bottom surface

T1, T2‧‧‧ thickness

1A-1G are schematic cross-sectional views showing a method of fabricating a line structure according to an embodiment of the invention.

2A-2F are schematic cross-sectional views showing a partial step of a method for fabricating a line structure according to another embodiment of the present invention.

1A-1G are schematic cross-sectional views showing a method of fabricating a line structure according to an embodiment of the invention. Referring to FIG. 1B, with respect to the method for fabricating the circuit structure of the present embodiment, first, two patterned circuit layers 120a and 120b are formed on a core layer 110, wherein the patterned circuit layers 120a and 120b are respectively located at the core layer 110. On the two surfaces 111, 113.

In detail, referring to FIG. 1A, the core layer 110 includes a core dielectric layer 112, two first copper foil layers 114a, 114b, and two second copper foil layers 116a, 116b. The first copper foil layers 114a, 114b are respectively located on opposite side surfaces 112a, 112b of the core dielectric layer 112, and the second copper foil layers 116a, 116b are respectively located on the first copper foil layers 114a, 114b, and each A copper foil layer 114a (or 114b) has a large thickness T1 The thickness T2 of each of the second copper foil layers 116a (or 116b). Here, the thickness T1 of the first copper foil layer 114a (or 114b) is, for example, 18 micrometers, and the thickness T2 of the second copper foil layer 116a (or 116b) is, for example, 3 micrometers, but is not limited thereto.

Referring again to FIG. 1B, patterned circuit layers 120a, 120b are respectively located on opposite surfaces 111, 113 of core layer 110, wherein patterned circuit layers 120a, 120b expose portions 111, 113 of portions of core layer 110, respectively. Here, the method of forming the patterned wiring layers 120a, 120b is, for example, by providing a plating mask (not shown) on the surfaces 111, 113 of the core layer 110, with the second copper foil layers 116a, 116b of the core layer 110 being The plating seed layer is formed by patterning the patterned wiring layers 120a and 120b, and then the plating mask is removed to complete the fabrication of the patterned wiring layers 120a and 120b, but is not limited thereto.

Next, referring to FIG. 1C, a patterned insulating layer 130a, 130b is formed on each of the patterned wiring layers 120a, 120b, wherein the patterned insulating layers 130a, 130b expose portions of the patterned wiring layers 120a, 120b, respectively. Here, the patterned insulating layer 130a, 130b is coated with an insulating material layer (not shown), for example, before the patterned circuit layer 120a, 120b, and a photoresist is applied to the insulating material layer (not shown). The fabrication of the patterned insulating layers 130a, 130b is completed by exposure, development, and development steps, but is not limited in this manner.

Next, referring to FIG. 1D and FIG. 1E, two support plates 140a, 140b are respectively pressed onto the patterned insulating layers 130a, 130b, wherein each support plate 140a (or 140b) includes a B-stage insulating layer 142a ( Or 142b) and two copper foil layers 144a, 146a (or 144b, 146b), copper foil layers 144a, 146a (or 144b, 146b) The opposite side surfaces of the B-stage insulating layer 142a (or 142b) are respectively located, and the copper foil layer 1406 (or 146b) of each of the support plates 140a (or 140b) directly contacts the corresponding patterned insulating layers 130a, 130b. At this time, as shown in FIG. 1E, a plurality of air gaps are composed of each of the support plates 140a (or 140b), each of the patterned insulating layers 130a (or 130b), and each of the patterned circuit layers 120a (or 120b).

It is worth mentioning that the core layer of the support plate 140a (or 140b) here is embodied as a B-stage insulating layer 142a (or 142b), that is, it is a semi-cured insulating layer, so it will be supported by thermal compression. When the plates 140a, 140b are pressed against the patterned insulating layers 130a, 130b, they may have a better bonding force, and the copper foil layers 144a, 146a, 144b, 146b of the support plates 140a, 140b may also be improved and avoided with respect to B. The warpage phenomenon occurs in the step insulating layers 142a, 142b.

Thereafter, referring to FIG. 1F and FIG. 1G simultaneously, the core layer 110 is removed to expose an upper surface 122 of each patterned wiring layer 120a and a top surface 132 of each patterned insulating layer 130a. The upper surface 122 of each patterned wiring layer 120a is aligned with the top surface 132 of each patterned insulating layer 130a. It should be noted that, for convenience of description, after removing the core layer 110, FIG. 1G only schematically illustrates a circuit structure 100a.

In detail, please refer to FIG. 1E and FIG. 1F simultaneously, and the core dielectric layer of the core layer 110 is separated from the first copper foil layers 114a and 114b and the second copper foil layers 116a and 116b by means of detachment, but In this way, it is limited.

At this time, as shown in FIG. 1F, only the second copper foil layers 116a, 116b are left in direct contact with the patterned insulating layers 130a, 130b and the patterned wiring layers 120a, 120b. Next, referring to FIG. 1F and FIG. 1G, the second copper foil layers 116a, 116b of the core layer 110 are removed by etching to expose the upper surface 122 of the patterned wiring layer 120a and the patterned insulating layer 130a. Top surface 132. So far, the core layer 110 has been removed and the fabrication of the line structure 100a has been completed.

Structurally, referring again to FIG. 1F, the wiring structure 100a of the present embodiment includes a patterned wiring layer 120a and a patterned insulating layer 130a. The patterned insulating layer 130a covers a portion of the patterned wiring layer 120a, wherein the upper surface 122 of the patterned wiring layer 120a is aligned with the top surface 132 of the patterned insulating layer 130a. Here, the upper surface 122 of the patterned wiring layer 120a and the top surface 132 of the patterned insulating layer 130a can serve as a wafer bonding surface, and a wafer (not shown) can be bonded to the wafer bonding surface in a subsequent process.

Furthermore, the circuit structure 100a of the present embodiment may further include a support plate 140a disposed on the bottom surface 134 of the patterned insulating layer 130a, wherein the support plate 140a includes a B-stage insulating layer 142a and two copper foil layers 144a, 146a, copper. The foil layers 144a, 146a are respectively located on opposite side surfaces of the B-stage insulating layer 142a, and the copper foil layer 146a directly contacts the bottom surface 134 of the patterned insulating layer 130a. Here, the purpose of the support plate 140a is to support the patterned wiring layer 120a and the patterned insulating layer 130a, so that the wiring structure 100a of the present embodiment has better structural reliability. It should be noted that after the subsequent packaging process, it is intended to remove the support plate 140a to obtain a product having a thin package thickness. At this time, the bottom surface 134 of the patterned insulating layer 130a exposed by removing the support plate 140a can be used as a Ball Grid Array (BGA) bonding surface, and is suitable for bonding a plurality of solder balls (not drawn) Show).

Since the circuit structure of the present embodiment can fabricate the circuit structure 100a having only a single layer circuit layer, the process time of the circuit structure 100a can be greatly reduced, and the process cost is low.

In order to increase the wiring density of the line structure 100a, FIGS. 2A to 2F are schematic cross-sectional views showing partial steps of a method of fabricating another line line structure. The fabrication method of the circuit structure of this embodiment is similar to the fabrication method of the circuit structure in FIGS. 1A to 1G, but the main difference between the two is that after the step of FIG. 1B, the patterned circuit is formed on the core layer 110. After the layers 120a, 120b, please refer to FIG. 2A, coating the insulating material layer 130 on the patterned circuit layers 120a, 120b, wherein the insulating material layer 130 completely covers the patterned wiring layers 120a, 120b and the patterned wiring layers 120a, 120b exposed. The surfaces 111, 113 of the core layer 110 are formed.

Next, referring to FIG. 2B, the insulating material layer 130 is coated with a photoresist (not shown), exposed, and developed to complete the fabrication of the patterned insulating layers 130c and 130d.

Next, referring to FIG. 2B, a sub-layer 150 is formed on each of the patterned insulating layers 130c and 130d. The seed layer 150 covers the patterns exposed by the patterned insulating layers 130c and 130d and the patterned insulating layers 130c and 130d. The circuit layers 120a, 120b are formed. Here, the method of forming the seed layer 150 is, for example, an electroplating method.

Next, referring to FIG. 2C, a seeding process is performed on the seed layer 150 to form a patterned seed layer 150a and a patterned seed layer 150b. Here, the patterned seed layer 150a, 150b is, for example, an electroplated copper layer. Next, a patterned build-up layer layer 160a, 160b is formed on each of the patterned seed layers 150a, 150b, The patterned build-up wiring layers 160a and 160b are disposed on the patterned seed layers 150a and 150b, respectively, and are connected to the patterned wiring layers 120a and 120b through the patterned seed layers 150a and 150b. As shown in FIG. 2C, the patterned build-up wiring layers 160a, 160b are composed of patterned wiring layers 162a, 162b and conductive vias 164a, 164b connecting the patterned wiring layers 162a, 162b and the patterned wiring layers 120a, 120b. . Here, the method of forming the patterned build-up wiring layers 160a, 160b is, for example, by patterning the seed layers 150a, 150b as a plating seed layer, and forming a wiring layer (not shown) by electroplating. Next, referring to FIG. 2D, a patterned build-up insulating layer 170a, 170b is formed on each of the patterned build-up wiring layers 160a, 160b, wherein the patterned build-up insulating layers 170a, 170b respectively expose partial patterning Layer circuit layers 160a, 160b. Here, the method of forming the patterned build-up insulating layers 170a, 170b is, for example, applying an insulating material layer (not shown) before the patterned build-up wiring layers 160a, 160b, and coating the insulating material layer once. The fabrication of the patterned build-up insulating layers 170a, 170b is accomplished by a resist (not shown), exposure, and development steps, but is not limited in this manner.

Next, with the steps of FIG. 1D and FIG. 1E, two support plates 140c, 140d are provided, wherein the support plates 140c, 140d are respectively pressed onto the patterned build-up insulating layers 170a, 170b, and the support plate 140c (or 140d) The copper foil layers 144c, 146c (or 144d, 146d) are respectively located on opposite side surfaces of the B-stage insulating layer 142c (or 142d), and the copper foil layer 146c (or 146d) of the support plate 140c (or 140d) is directly in contact with the corresponding Please refer to FIG. 2E for the patterned build-up insulating layers 170a, 170b. At this time, as shown in FIG. 2E, a plurality of air gaps are provided by each of the support plates 140c (or 140d), each of the patterned build-up insulating layers 170a (or 170b), and each of the patterned build-up wiring layers 160a (or 160b).

It is worth mentioning that the core layer of the support plate 140c (or 140d) here is embodied as a B-stage insulating layer 142c (or 142d), that is, it is a semi-cured insulating layer, so it will be supported by thermal compression. When the plates 140c, 140d are pressed against the patterned build-up insulating layers 170a, 170b, they may have a better bonding force, and the copper foil layers 144c, 146c, 144d, 146d of the support plates 140c, 140d may also be improved and avoided. A warpage phenomenon occurs in the B-stage insulating layers 142c, 142d.

Thereafter, with the implementation steps of FIGS. 1F and 1G, the core layer 110 is removed to expose an upper surface 122 of each patterned wiring layer 120a and a top surface 132' of each patterned insulating layer 130c, wherein each The upper surface 122 of a patterned wiring layer 120a is aligned with the top surface 132' of each patterned insulating layer 130c, please refer to both FIG. 2E and FIG. 2F. It should be noted that, for convenience of description, after removing the core layer 110, FIG. 2F only schematically illustrates a circuit structure 100b. So far, the production of the line structure 100b has been completed.

Structurally, referring again to FIG. 2F, the wiring structure 100b of the present embodiment is composed of a patterned wiring layer 120a, a patterned insulating layer 130c, a patterned seed layer 150a, a patterned build-up wiring layer 160a, and a patterned build-up insulating layer. Layer 170a is composed of. The patterned insulating layer 130c covers a portion of the patterned wiring layer 120a, wherein the upper surface 122 of the patterned wiring layer 120a is aligned with the top surface 132' of the patterned insulating layer 130c. Here, the upper surface 122 of the patterned wiring layer 120a and the top surface 132' of the patterned insulating layer 130c can be used as a wafer bonding surface, and a wafer (not shown) can be bonded to the wafer bonding surface in a subsequent process. . Patterned seed layer 150a covers the patterned insulating layer 130c and a partially patterned circuit layer 120a. The patterned build-up wiring layer 160a is disposed on the patterned seed layer 150a, wherein the patterned build-up wiring layer 160a is connected to the patterned wiring layer 120a through the patterned seed layer 150a. The patterned build-up insulating layer 170a exposes a portion of the patterned build-up wiring layer 160a.

Furthermore, the circuit structure 100b of the present embodiment may further include a support plate 140c disposed on the bottom surface 172 of the patterned build-up insulating layer 170a, wherein the support plate 140c includes a B-stage insulating layer 142c and two copper foil layers 144c, 146c. The copper foil layers 144c, 146c are respectively located on opposite side surfaces of the B-stage insulating layer 142c, and the copper foil layer 146c directly contacts the bottom surface 172 of the patterned build-up insulating layer 170a. It should be noted that after the subsequent packaging process, the support plate 140c is intended to be removed, and a product having a thin package thickness can be obtained.

In summary, since the circuit structure of the present invention can produce a circuit structure having only a single layer of circuit layers, the process time of the line structure can be greatly reduced, and the process cost is low. In addition, in order to increase the wiring density of the line structure, the patterned build-up layer layer and the patterned build-up layer insulating layer may be formed on the line structure of the single-layer circuit layer, thereby improving the applicability of the line structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100a: wiring structure 120a: patterned wiring layer 122: upper surface 130a: patterned insulating layer 132: top surface 134: bottom surface 140a: support plate 142a: B-stage insulating layer 144a, 146a: copper foil layer

Claims (7)

A method for fabricating a circuit structure, comprising: forming a two patterned circuit layer on a core layer, wherein the patterned circuit layers are respectively located on opposite surfaces of the core layer, wherein each of the patterned circuit layers is a single layer a circuit layer; a patterned insulating layer is formed on each of the patterned circuit layers, wherein the patterned insulating layers respectively expose a portion of the patterned circuit layers; and two supporting plates are provided, respectively pressed to the patterned layers On the insulating layer, wherein a plurality of air gaps are composed of the support plates, each of the patterned insulating layers, and each of the patterned circuit layers; and after the support plates are provided, the core layer is removed to expose each An upper surface of the patterned wiring layer and a top surface of each of the patterned insulating layers, wherein the upper surface of each of the patterned wiring layers is aligned with the top surface of each of the patterned insulating layers. The method for fabricating a line structure according to claim 1, wherein the core layer comprises a core dielectric layer, two first copper foil layers and two second copper foil layers, wherein the first copper foil layers are respectively located. On the opposite side surfaces of the core dielectric layer, the second copper foil layers are respectively located on the first copper foil layers, and the thickness of each of the first copper foil layers is greater than that of each of the second copper foil layers. thickness. A method for fabricating a circuit structure, comprising: forming a two patterned circuit layer on a core layer, wherein the patterned circuit layers are respectively located on opposite surfaces of the core layer, wherein each of the patterned circuit layers is a single layer Line layer Forming a patterned insulating layer on each of the patterned circuit layers, wherein the patterned insulating layers respectively expose a portion of the patterned circuit layers; and forming a sub-layer on each of the patterned insulating layers, The seed layer covers the patterned insulating layer and the patterned circuit layers exposed by the patterned insulating layers; performing a patterning process on each of the seed layers to form a patterned seed layer; A patterned layered wiring layer is formed on the patterned seed layer, and the patterned layered wiring layers are respectively disposed on the patterned seed layers, and the patterned seed layer is transmitted through the patterned circuit layers. Connecting, forming a patterned build-up insulating layer on each of the patterned build-up circuit layers, the patterned build-up insulating layers respectively exposing a portion of the patterned build-up circuit layers; providing two support plates, respectively pressing Cooperating with the patterned build-up insulating layers, wherein a plurality of air gaps are formed by each of the support plates, each of the patterned build-up insulating layers, and each of the patterned build-up circuit layers; After the gusset is removed, the core layer is removed to expose an upper surface of each of the patterned circuit layers and a top surface of each of the patterned insulating layers, wherein the upper surface of each of the patterned circuit layers is aligned with each The top surface of the patterned insulating layer. The method for fabricating a line structure according to claim 3, wherein the core layer comprises a core dielectric layer, two first copper foil layers and two second copper foil layers, wherein the first copper foil layers are respectively located. On the opposite side surfaces of the core dielectric layer, The second copper foil layers are respectively located on the first copper foil layers, and the thickness of each of the first copper foil layers is greater than the thickness of each of the second copper foil layers. A circuit structure comprising: a patterned circuit layer, wherein the patterned circuit layer is a single circuit layer; a patterned insulating layer covering a portion of the patterned circuit layer, wherein an upper surface of the patterned circuit layer is cut a top surface of the patterned insulating layer; and a support plate disposed on a bottom surface of the patterned insulating layer, wherein the plurality of air gaps are supported by the support plate, the patterned circuit layer, and the patterned insulating layer The composition of the layers. A circuit structure comprising: a patterned circuit layer, wherein the patterned circuit layer is a single circuit layer; a patterned insulating layer covering a portion of the patterned circuit layer, wherein an upper surface of the patterned circuit layer is cut a top surface of the patterned insulating layer; a patterned seed layer covering the patterned insulating layer and a portion of the patterned wiring layer; and a patterned build-up wiring layer disposed on the patterned seed layer, wherein The patterned build-up wiring layer is connected to the patterned circuit layer through the patterned seed layer; a patterned build-up insulating layer exposing a portion of the patterned build-up wiring layer; and a support plate disposed on the pattern A bottom surface of the build-up insulating layer, wherein a plurality of air gaps are composed of the support plate, the patterned build-up wiring layer, and the patterned build-up insulating layer. The circuit structure of claim 6, wherein the patterned seed layer is an electroplated copper layer.