TWI579990B - Chip package subatrate, chip package structure and method for manufacturing the chip package substrate and the chip package structure - Google Patents

Description

Chip package substrate, chip package structure and manufacturing method

The present invention relates to a chip package substrate, a chip package structure, and a method of fabricating the same.

As electronic products become lighter and thinner, wafer package substrates are also becoming thinner and lighter. In the prior art, when manufacturing a thin chip package substrate, an electrical carrier is usually provided in advance and an electroplated conductive layer is formed on the electrical carrier, and finally part of the electrical carrier and the electroplated conductive layer are removed. Although the thickness of the fabricated wafer package substrate can be reduced, the process of the chip package substrate will be lengthy and costly.

In view of the above, it is necessary to provide a chip package substrate, a chip package structure, and a fabrication method that overcome the above problems.

A chip package substrate comprising a conductive line, a conductive pillar and an encapsulant. The conductive line includes a raw copper layer and a plating layer. The conductive pillar is protruded from the original copper layer away from the plating layer. The conductive pillar includes a plating portion and a solder portion. The plating portion is located between the original copper layer and the solder portion. The encapsulant is formed on the original copper layer and the surface of the conductive pillar. The encapsulant covers the original copper layer and wraps the conductive pillar. The conductive pillar is exposed from the encapsulant, and an end surface of the solder portion away from the original copper layer is in the same plane as an end surface of the encapsulant away from the original copper layer. Inside.

A chip package structure includes a chip package substrate and a wafer. The chip package substrate includes a conductive line, a conductive pillar, and an encapsulant. The conductive line includes a raw copper layer and a plating layer. The conductive pillar is protruded from the original copper layer away from the plating layer. The conductive pillar includes a plating portion and a solder portion. The plating portion is located between the original copper layer and the solder portion. The encapsulant is formed on the original copper layer and the surface of the conductive pillar. The encapsulant covers the original copper layer and wraps the conductive pillar. The conductive pillars are exposed from the encapsulant. An end surface of the solder portion away from the original copper layer is located in the same plane as an end surface of the encapsulant away from the original copper layer. The wafer is mounted on the encapsulant. The wafer includes a plurality of electrode pads. The electrode pads are electrically connected to the conductive pillars in one-to-one correspondence.

A method for fabricating a chip package substrate, comprising the steps of: providing a substrate comprising a carrier plate and a first original copper layer and a second original copper layer on opposite sides of the carrier plate; forming a conductive pillar on the surface of the two original copper layers, The conductive pillar includes a plating portion and a solder portion; an encapsulant is formed on the surface of the two original copper layers, the encapsulant covers the conductive pillar; the encapsulant is ground to expose the conductive pillar; Separating the first separated copper layer from the first original copper layer to expose the first original copper layer; selectively forming a plating layer on the first original copper layer; and etching the first exposed from the plating layer An original copper layer forms a first conductive line.

A method for fabricating a chip package structure, comprising the steps of: providing a chip package substrate comprising a conductive line, a conductive pillar and an encapsulant, the conductive trace comprising a raw copper layer and a plating layer, the conductive pillar being away from the original copper layer The plating layer is convexly disposed, the conductive pillar includes a plating portion and a solder portion, the plating portion is located between the original copper layer and the solder portion, and the encapsulant is formed on the original copper layer and the surface of the conductive pillar , The encapsulant covers the original copper layer and covers the conductive pillars, the conductive pillars are exposed from the encapsulant; a wafer is mounted on the encapsulant, the wafer includes a plurality of electrode pads, The plurality of electrode pads are electrically connected to the conductive pillars in one-to-one correspondence; and a potting gel is filled between the wafer and the encapsulant.

Compared with the prior art, the chip package substrate provided by the present invention can make the chip package substrate thin by using an encapsulant as a carrier body. The method for fabricating the chip package structure provided by the invention does not use an electrical carrier board, so there is no need to increase the subsequent removal step, and the process of the chip package structure is simplified, thereby saving cost.

100‧‧‧ Chip package structure

10‧‧‧ Chip package substrate

11‧‧‧Substrate

110‧‧‧Substrate unit

111‧‧‧Loading board

112‧‧‧First layer

113‧‧‧Second layer

114‧‧‧First separated copper layer

115‧‧‧Second separation copper layer

116‧‧‧First original copper layer

117‧‧‧Second original copper layer

12‧‧‧First conductive column

13‧‧‧Second conductive column

121‧‧‧First plating department

131‧‧‧Second plating department

122‧‧‧First Solder

132‧‧‧Second solder department

123‧‧‧First plating barrier

133‧‧‧Second plating barrier

1231‧‧‧First opening

1331‧‧‧Second opening

14‧‧‧First encapsulant

15‧‧‧Second encapsulant

16‧‧‧First separation board

17‧‧‧Second separation plate

18‧‧‧First conductive line

181‧‧‧Electroplating

19‧‧‧First solder mask

191‧‧‧ openings

192‧‧‧First electrical contact pads

20‧‧‧ wafer

21‧‧‧electrode pads

22‧‧‧ potting colloid

1 is a plan view of a substrate according to a first embodiment of the present invention.

2 is a schematic cross-sectional view of a substrate unit of FIG. 1.

3 is a schematic cross-sectional view showing a first plating barrier layer formed on the first original copper layer of FIG. 2 and a second plating barrier layer and a second conductive pillar formed on the first conductive pillar and the second original copper layer.

4 is a schematic cross-sectional view showing the first plating barrier layer and the second plating barrier layer in FIG.

5 is a cross-sectional view showing the first encapsulant on the first original copper layer and the second encapsulant on the second original copper layer in FIG.

FIG. 6 is a schematic cross-sectional view showing the first encapsulant after the first encapsulant colloid is polished in FIG. 5 and the second encapsulant is polished to expose the second conductive pillar.

Fig. 7 is a cross-sectional view showing the first separation plate and the second separation plate after the substrate unit of Fig. 6 is removed in the Y-axis direction of Fig. 1.

FIG. 8 is a schematic cross-sectional view showing the first original copper layer of the first separating plate of FIG. 7 after the first conductive line is formed.

9 is a cross-sectional view showing the first conductive layer on the surface of the first conductive line in FIG. 8 and separating the substrate unit in the X-axis direction of FIG. 1 to obtain a plurality of chip package substrates.

FIG. 10 is a cross-sectional view showing a wafer after mounting a wafer on the chip package substrate of FIG. 9. FIG.

The chip package substrate 10 provided by the present invention and the method for fabricating the chip package structure 100 having the same are further described in detail below with reference to the accompanying drawings and embodiments.

A method for fabricating a chip package structure 100 according to a first embodiment of the present invention includes the steps of:

In the first step, referring to Figures 1 and 2, a substrate 11 is provided.

The thickness of the substrate 11 in the vertical direction includes a plurality of substrate units 110. The substrate units 110 are distributed in an array.

The thickness direction of the substrate 11 includes a carrier plate 111, a first adhesive layer 112, a second adhesive layer 113, a first separated copper layer 114, a second separated copper layer 115, a first original copper layer 116, and a second original copper layer 117. . The first adhesive layer 112 and the second adhesive layer 113 are respectively located on opposite sides of the carrier board 111. The first separated copper layers 114 are embedded in the first adhesive layer 112 and are distributed in an array. The second separated copper layer 115 is embedded in the second adhesive layer 113 and distributed in an array. Each of the substrate units 110 corresponds to one first separated copper layer 114 and one second separated copper layer 115. The first original copper layer 116 covers the surface of the first adhesive layer 112 and the first separated copper layer 114. The second original copper layer 117 covers the surface of the second adhesive layer and the second separated copper layer 115.

For convenience of description, the following steps and corresponding drawings are described for one substrate unit 110.

In the second step, referring to FIG. 3 and FIG. 4, a plurality of first conductive pillars 12 are formed on the surface of the first original copper layer 116, and a plurality of second conductive pillars 13 are formed on the surface of the second original copper layer 117.

The first conductive pillar 12 includes a first plating portion 121 and a first solder portion 122. The first plating portion 121 is located between the first original copper layer 116 and the first solder portion 122. The second conductive pillar 13 has the same structure as the first conductive pillar 12 and includes a second plating portion 131 and a second solder portion 132.

Forming the first conductive pillar 12 and the second conductive pillar 13 includes: firstly forming a first plating barrier layer 123 and a second plating barrier layer on the surfaces of the first original copper layer 116 and the second original copper layer 117, respectively 133. The first plating barrier layer 123 is provided with a plurality of first openings 1231 to expose a portion of the first original copper layer 116. The second plating barrier layer 133 is provided with a plurality of second openings 1331 to expose a portion of the second original copper layer 117.

Next, a plurality of first plating portions 121 are formed on the first original copper layer 116 exposed from the first opening 1231, and a first solder portion 122 is formed on the first plating portion 121. The second original copper layer exposed on the second opening 1331 is plated to form the second plating portion 131 and the second plating portion 131 is formed on the second plating portion 131. It can be understood that the first solder portion 122 and the second solder portion 132 can serve as a pre-weld material when the wafer is subsequently soldered.

Finally, the first plating barrier layer 123 and the second plating barrier layer 133 are removed.

In the third step, referring to FIG. 5 and FIG. 6, a first seal is formed on the first original copper layer 116. The first encapsulant 14 is coated with the first encapsulant 14 to polish the first encapsulant 14 so that the first encapsulant 14 is away from the surface of the first original copper layer 116. The first conductive pillar 12 is located in the same plane away from the surface of the first original copper layer 116 to expose the first conductive pillar 12; and the second original colloid 15 is formed on the second original copper layer 117, The second encapsulant 15 covers the second conductive pillar 13 and grinds the second encapsulant 15 so that the second encapsulant 15 is away from the surface of the second original copper layer 117 and the second conductive pillar 13 is located away from the surface of the second original copper layer 117 in the same plane to expose the second conductive pillars 13.

In the fourth step, referring to FIG. 1 and FIG. 7, the board is disassembled along the Y-axis direction to separate the first original copper layer 116 from the first separated copper layer 114, to obtain a first separating board 16, and to make the second The original copper layer 117 is separated from the original second separated copper layer 115 to obtain a second separation plate 17.

The board can be removed by laser cutting or fishing.

The following steps are equally applicable to the first separating plate 16 and the second separating plate 17, and only the first separating plate 16 will be described as an example.

In the fifth step, referring to FIG. 8, the first original copper layer 116 is formed into a first conductive line 18 by image transfer and electroplating etching. The first conductive line 18 includes a portion of the first original copper layer 116 and a plating layer. 181. In the embodiment, the plating layer 181 is an electroplated copper layer. The first conductive line 18 is formed on a surface of the first encapsulant 14 .

First, a second plating barrier layer (not shown) is formed on the surface of the first original copper layer 116, and the second plating barrier layer has a patterned structure complementary to the first conductive trace 18 to expose a portion of the a first original copper layer 116; then, a plating layer 181 is formed on the first original copper layer 116; Next, the second plating barrier layer is removed; finally, the first original copper layer 116 exposed from the plating layer is removed by etching to expose a portion of the first encapsulant 14 .

In a sixth step, referring to FIG. 9, a first solder resist layer 19 is formed on the surface of the first conductive line 18, and the first solder resist layer 19 covers the first conductive line 18 and the first conductive line. 18 exposes a portion of the first encapsulant 14 . The first solder resist layer 19 is provided with a plurality of third openings 191, and the exposed portion of the first conductive traces 18 form a first electrical contact pad 192.

In the seventh step, referring to FIG. 1 and FIG. 9, a plurality of chip package substrates 10 are formed along the X-axis.

In the eighth step, referring to FIG. 10, a wafer 20 is mounted on the chip package substrate 10 to form a wafer level chip package structure 100.

The wafer 20 includes a plurality of electrode pads 21. The electrode pads 21 are electrically connected to the first conductive pillars 12 in one-to-one correspondence. The potting pad 21 and the first encapsulant 14 are filled with a potting compound 22 to fix the wafer 20 to the chip package substrate 10.

It can be understood that, since the thickness of the first original copper layer 116 and the second original copper layer 117 of the substrate 11 is relatively thick, the bonding force between the original copper layer and the conductive pillar and the encapsulant is increased. Forming a plurality of first conductive pillars 12 on the surface of the first original copper layer 116, and before forming the plurality of second conductive pillars 13 on the surface of the second original copper layer 117, further comprising the first original copper layer 116 and The second original copper layer 117 is subjected to a thinning process. Therefore, when the first conductive line 18 is formed by subsequent plating, the thickness of the plating layer 181 is greater than the thickness of the first original copper layer 116.

It can be understood that in order to improve the alignment accuracy of the wafer 20 and the chip package substrate 10, the mounting of the wafer 20 can also be performed before the division of the plurality of wafer package substrates 10.

In other embodiments, the substrate 11 may include only the carrier plate 111, the first adhesive layer 112, the second adhesive layer 113, the first original copper layer 116, and the second original copper layer 117. The first adhesive layer 112 is located between the carrier plate 111 and the first original copper layer 116. The second adhesive layer 113 is located between the carrier plate 111 and the second original copper layer 117. At this time, the first adhesive layer 112 and the second adhesive layer 113 are both thermoplastic adhesive layers. When the board is subsequently unpacked, only the melting point of the first adhesive layer and the second adhesive layer 113 is heated, and the first original copper layer 116 is separated from the first adhesive layer 112 to obtain the first separating plate. 16. And separating the second original copper layer 117 from the second adhesive layer 113 to obtain a second separation plate 17.

Referring to FIG. 10 again, the present invention further provides a chip package structure 100 obtained by the above method, comprising a chip package substrate 10 and a wafer 20.

The chip package substrate 10 includes a first conductive line 18 , a first conductive pillar 12 , a first encapsulant 14 , and a first solder resist layer 19 .

The first conductive line 18 includes a first original copper layer 116 and a plating layer 181 formed thereon. The thickness of the first original copper layer 116 is smaller than the thickness of the plating layer 181. The first original copper layer 116 has a thickness of less than 0.3 microns.

The first conductive pillar 12 is formed on the first conductive line 18. Specifically, the first conductive pillar 12 protrudes from the first original copper layer 116 in a direction away from the plating layer 181. The first conductive pillar 12 includes a first plating portion 121 and a first solder portion 122. The first plating portion 121 is located between the first original copper layer 116 and the first solder portion 122. The first solder portion 122 covers the first plating portion 121 to prevent oxidation of a surface of the first plating portion 121 in contact with air.

The first encapsulant 14 is formed on the first original copper layer 116. The first encapsulant 14 covers the first original copper layer 116 and wraps the first conductive pillars 12 . An end surface of the first conductive pillar 12 away from the first original copper layer 116 is located in the same plane as an end surface of the first encapsulant 14 away from the first original copper layer 116. The first solder portion 122 of the first conductive pillar 12 is exposed from the first encapsulant 14 .

The first solder resist layer 19 is formed on the plating layer 181. The first solder resist layer 19 covers a portion of the plating layer 181 and the first encapsulant 14 exposed from the first conductive line 18. The first solder resist layer 19 is provided with a plurality of openings 191, and the exposed portion of the plating layer 181 forms a first electrical contact pad 192.

One end face of the wafer 20 includes a plurality of electrode pads 21. The electrode pads 21 are electrically connected to the first conductive pillars 12 in one-to-one correspondence. A potting compound 22 is filled between the wafer 20 and the first encapsulant 14 to fix the wafer 20 on the chip package substrate 10.

Compared with the prior art, the chip package substrate provided by the present invention can make the chip package substrate thinner by using an encapsulant as a carrier body. The method for fabricating the chip package structure provided by the technical solution does not use an electrical carrier board, so there is no need to increase the subsequent removal step, the process of the chip package structure is simplified, and the cost is saved.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

100‧‧‧ Chip package structure

10‧‧‧ Chip package substrate

20‧‧‧ wafer

18‧‧‧First conductive line

12‧‧‧First conductive column

14‧‧‧First encapsulant

19‧‧‧First solder mask

116‧‧‧First original copper layer

181‧‧‧Electroplating

121‧‧‧First plating department

122‧‧‧First Solder

191‧‧‧ openings

192‧‧‧First electrical contact pads

21‧‧‧electrode pads

22‧‧‧ potting colloid

Claims (9)

A chip package substrate comprising a conductive line, a conductive pillar and an encapsulant, the conductive trace comprising a raw copper layer and a plating layer, the conductive pillar being protruded from the original copper layer away from the plating layer, the conductive pillar comprising a plating portion and a solder portion, the plating portion is located between the original copper layer and the solder portion, the encapsulant is formed on the surface of the original copper layer and the conductive pillar, and the encapsulant covers the original copper layer And coating the conductive pillars, the conductive pillars are exposed from the encapsulant, and an end surface of the solder portion away from the original copper layer is in the same plane as an end surface of the encapsulant away from the original copper layer. The chip package substrate of claim 1, wherein the chip package substrate further comprises a solder resist layer, the solder resist layer covers the plating layer, and the solder resist layer is provided with a plurality of openings to expose a portion of the conductive layer The lines form an electrical connection pad. The chip package substrate of claim 1, wherein the plating layer is an electroplated copper layer. The chip package substrate of claim 1, wherein the original copper layer has a thickness smaller than a thickness of the plating layer. A chip package structure, comprising: the chip package substrate and the wafer according to any one of claims 1 to 4, wherein the wafer is mounted on an encapsulant of the chip package substrate, the wafer includes a plurality of electrode pads, The electrode pads are electrically connected to the conductive pillars in one-to-one correspondence. A method for fabricating a chip package substrate, comprising the steps of: providing a substrate comprising a carrier plate and a first original copper layer and a second original copper layer on opposite sides of the carrier plate; forming a conductive pillar on the surface of the two original copper layers, The conductive pillar includes a plating portion and a solder portion; forming an encapsulant on the surface of the two original copper layers, the encapsulant covering the conductive pillar and covering the two original copper layers; Polishing the encapsulant to expose the conductive pillar; disassembling the plate to expose the first original copper layer; selectively forming a plating layer on the first original copper layer; and etching exposed from the plating layer The first original copper layer forms a first conductive line. The method of fabricating a chip package substrate according to claim 6, wherein the method for fabricating the chip package substrate further comprises forming a first solder resist layer on the first conductive line, wherein the first solder resist layer is provided with a plurality of openings And exposing a portion of the first conductive line to form a first electrical connection pad. The method of fabricating a chip package substrate according to claim 6, wherein the forming the first conductive pillar comprises the steps of: forming a plating barrier layer on a surface of the first original copper layer, wherein the plating barrier layer is provided with a plurality of first openings a plating portion formed on the surface of the first original copper layer exposed from the opening, the plating portion having a thickness smaller than the plating barrier layer; forming a solder portion on a surface of the plating portion; and removing the plating Barrier layer. A method of fabricating a chip package structure, comprising the steps of: providing a chip package substrate according to any one of claims 1 to 4; mounting a wafer on the chip package substrate, the wafer being on the package gel, The wafer includes a plurality of electrode pads, and the plurality of electrode pads are electrically connected to the conductive pillars in one-to-one correspondence; and a potting gel is filled between the wafer and the encapsulant.