TWI578534B - High voltage metal-oxide-semiconductor transistor device - Google Patents

Description

High voltage MOS transistor

The invention relates to a high voltage metal-oxide-semiconductor (hereinafter referred to as HV MOS) transistor component, in particular to a high voltage lateral double-diffused metal-oxide-semiconductor. , HV-LDMOS) transistor components.

Among power components with high-voltage processing capability, double-diffused MOS (DMOS) transistor components continue to receive attention. Common DMOS transistor components are vertical double-diffused MOS (VDMOS) and lateral double-diffused metal oxide semiconductor (LDMOS) transistor components. LDMOS transistor components are widely used in high-voltage operating environments due to their high operating bandwidth and operating efficiency, as well as planar structures that are easily integrated with other integrated circuits, such as CPU power supply (CPU power). Supply), power management system, AC/DC converter, and high-power or high-band power amplifiers. The main feature of the LDMOS transistor component is that it has a low doping concentration and a large area of lateral diffusion drift region, the purpose of which is to alleviate the high voltage between the source terminal and the drain terminal, thereby enabling a higher breakdown of the LDMOS transistor component. Voltage (breakdown Voltage).

The conventional HV-LDMOS transistor component is disposed on a semiconductor substrate having a P-type well, a source disposed in the P-type well, a high-concentration P-type doped region, a gate and a drain . The 汲 is a highly concentrated N-type doped region and is disposed in an N-type well. The N-type well, that is, the aforementioned drift region, has a doping concentration and a length that affect the breakdown voltage and ON-resistance (R _ON ) of the HV-LDMOS transistor element. The gate of the HV-LDMOS transistor component is disposed on a gate dielectric layer and extends above a field oxide layer.

Since the two main characteristics pursued by HV MOS transistor components are low on-resistance and high breakdown voltage, and these two requirements are often conflicting with each other, it is difficult to balance. Therefore, there is still a need for a solution that can operate normally in a high voltage environment while satisfying both low on-resistance and high breakdown voltage.

Accordingly, it is an object of the present invention to provide an HV MOS transistor element having low on-resistance and high breakdown voltage.

According to the scope of the invention provided by the present invention, an HV MOS transistor element is provided. The HV MOS transistor component includes a substrate, at least one An insulating structure disposed on the substrate, a gate disposed on the substrate, and a source region and a drain region are disposed in the substrate on both sides of the gate. The insulating structure includes a recess, and the gate includes a first gate portion disposed on the surface of the substrate, and a second gate portion disposed in the recess, and the second gate A portion extends downward from the first gate portion.

According to the HV MOS transistor of the present invention, a recess is disposed in the insulating structure, and a second gate portion extending from the first gate portion is disposed in the recess to increase a current path (current path) The length and charge accumulation area, and at the same time achieve the purpose of reducing the on-resistance to increase the breakdown voltage, reducing the on-resistance to breakdown voltage ratio (R _ON / BVD ratio).

Please refer to FIG. 1 to FIG. 2 , wherein FIG. 1 is a partial layout diagram of a first preferred embodiment of a HV MOS transistor component provided by the present invention, and FIG. 2 is a cross-sectional view along the A- A schematic view of the section obtained by A' tangential line. As shown in FIG. 1 and FIG. 2, the HV MOS transistor element 100 provided in the preferred embodiment is disposed on a substrate 102, such as a substrate. The substrate 102 has a first conductivity type, which in the preferred embodiment is p-type. The HV MOS transistor element 100 provided in the preferred embodiment includes a gate 120 disposed on the substrate 102 and embedded in the substrate 102. An active region 106 is included, and the gate 120 covers a portion of the active region 106. The active region 106 includes a second conductivity type, and the second conductivity pattern is complementary to the first conductivity pattern. Therefore, in the preferred embodiment, the second conductivity type is n-type, and the active region 106 Is an n-type area. In the active region 106, a base region 108 (shown only in FIG. 2) is formed, and the base region 108 includes a first conductive type and is therefore a p-type base region. In the substrate 102 on both sides of the gate 120, a source region 110 (shown only in FIG. 2) and a drain region 112 (shown only in FIG. 2), the source region 110 and the drain region are respectively disposed. Each of 112 includes a second conductivity type, and thus is an n-type source region and an n-type drain region, respectively. As shown in FIG. 2, the source region 110 is provided in the p-type base region 108. In addition, in the p-type body region 108, a p-type doping region 114 complementary to the n-type source region 110 is further disposed, and the p-type doping region 114 is electrically connected to the n-type source region 110. In addition, the HV MOS transistor component 100 provided by the preferred embodiment is further provided with an n-type high voltage well region 116 and another n-type well region 118 at the 汲 extreme. As shown in FIG. 2, the drain region 112 is disposed in the n-well region 118, and the n-well region 118 is disposed in the n-type high pressure well region 116. The substrate 102 is further provided with a plurality of shallow trench isolation (STI) 104 for electrically isolating the HV MOS transistor device 100 from other components and at least one insulating structure disposed in the substrate 102 under the gate 120. 130. It is also worth noting that in FIG. 1 , the spatial relationship between the gate 120 , the active region 106 and the insulating structure 130 is emphasized, and the source region 110 , the drain region 112 , the base region 108 , and the p-type are not shown. Doped region 114, n The high-pressure well region 116 and the n-type well region 118 constitute components, but those skilled in the art should be able to easily know the formation position of the constituent elements according to the disclosure of FIG. 2, so the spatial relationship of the constituent elements is no longer Narration.

Please also refer to Figures 1 and 2. The insulating structure 130 provided by the HV MOS transistor element 100 provided by the preferred embodiment, such as but not limited to STI, is disposed in the substrate 102 below the gate 120 at one end of the gate region 112, and is as in the first As shown, the gate 120 covers a portion of the insulating structure 130. In addition, it should be noted that, according to the preferred embodiment, a portion of the insulating structure 130 is covered by a patterned mask (not shown) prior to forming the gate 120. For example, the dashed box shown in Figure 1 is the area where the patterned mask is exposed. Subsequently, an etching process is performed, and a suitable etchant having a high etching ratio to the doped region and the insulating material can be formed in the insulating structure 130 through the patterned mask without affecting the contour of the active region 106. Groove 132. One of the grooves 132 has a depth less than one of the insulating structures 130, and one of the grooves 132 has a width smaller than a width of the insulating structure 130. A gate dielectric layer 122 and a gate conductive layer 124 are then sequentially formed on the substrate 102. The formation of the gate dielectric layer 122 can be by any suitable process, such as a deposition process or a thermal oxidation process, but is not limited thereto. Therefore, each surface in the recess 132 must be formed with an insulating material. Since the recess 132 is formed in the insulating structure 130, at least the gate conductive layer 124 is filled in the recess 132 when the gate dielectric layer 122 and the gate conductive layer 124 are formed. Subsequently, the gate dielectric layer 122 and the gate conductive layer 124 are patterned, and formed on the substrate 102 as described above. 1 and the gate 120 shown in Fig. 2. It should be noted that since the gate dielectric layer 122 and the gate conductive layer 124 are filled in the recess 132, the finally formed gate 120 has two portions: a first gate disposed on the surface of the substrate 102. Portion 120a, and a second gate portion 120b extending downwardly from first gate portion 120a and formed within insulating structure recess 132. In addition, the insulating structure 130 electrically isolates the second gate portion 120b from the substrate 102, and the width and thickness of the second gate portion 120b are respectively smaller than the width and depth of the insulating structure 130.

Please continue to refer to Figure 1 and Figure 2. As shown in FIG. 1, since the etchant etches the insulating structure 130 through the active region 106 and the patterned mask in the preferred embodiment, the recess 132 and the second gate portion filled in the recess 132 are formed. As shown in FIG. 1, 120b obtains a U-shaped layout pattern with an opening facing the source region 110. In other words, the second gate portion 120b includes a continuous shape and includes a U-shape with an opening facing the source region 110. As shown in FIG. 2, the first gate portion 120a completely covers the second gate portion 120b, and the first gate portion 120a and the second gate portion 120b are perpendicular to each other and physically contacted with each other. A T-shaped gate 120 as shown in Fig. 2 is formed in the direction of the vertical substrate 102. More importantly, since the gate dielectric layer 122 is disposed between the first gate portion 120a and the substrate 102 and between the second gate portion 120b and the substrate 102, when a suitable voltage is applied to the gate 120 This T-shaped gate can obtain a longer current path and a larger charge accumulation region.

The HV MOS transistor device 100 according to the preferred embodiment is provided with a recess 132 in the insulating structure 130. Therefore, when the gate 120 is formed, a first gate formed on the surface of the substrate 120 is obtained. The portion 120a and a second gate portion 120b disposed in the recess 132. With the T-shaped gate 120 formed by the first gate portion 120a and the second gate portion 120b, the HV MOS transistor element 100 provided in the preferred embodiment obtains a large current path and a charge accumulation region, and thus can simultaneously Achieve the expectation of lowering R _ON and increasing the breakdown voltage.

Please refer to FIG. 3 to FIG. 5 , wherein FIG. 3 is a partial layout diagram of a second preferred embodiment of the HV MOS transistor component provided by the present invention, and FIG. 4 is a cross-sectional view along the B- in FIG. A schematic view of the cross section obtained by B' tangential line, and Fig. 5 is a schematic cross-sectional view taken along the C-C' tangent line in Fig. 3. It should be noted that the same components in the preferred embodiment as the first preferred embodiment may include the same material selection or conductivity type, and therefore will not be further described in the following description. As shown in FIG. 3 to FIG. 5, the HV MOS transistor device 200 of the preferred embodiment includes a substrate 202, a gate 220 disposed on the substrate 202, and an active layer formed in the substrate 202. Region 206, and gate 220 covers a portion of active region 206. In the active region 206, a p-type base region 208 is formed (shown in Figures 4 and 5). In the substrate 202 on both sides of the gate 220, an n-type source region 210 (shown in FIGS. 4 and 5) and an n-type drain region 212 are respectively disposed (shown in FIGS. 4 and 5). ). In addition, in the p-type base region 208, A p-type doped region 214 is disposed. The relative relationship between the p-type body region 208, the n-type source region 210, the n-type drain region 212 and the p-type doping region 214 is the same as that of the first preferred embodiment. In addition, the HV MOS transistor element 200 provided by the preferred embodiment is disposed at the 汲 extreme, and is disposed in an n-type high-voltage well region 216 and another n-type well region 218; and the n-type drain region 212 and the n-type well region. The relative relationship between 218 and n-type high pressure well region 216 is also the same as in the first preferred embodiment. The substrate 202 is further provided with a plurality of STIs 204 for electrically isolating the HV MOS transistor device 200 and other components, and an insulating structure 230 disposed in the substrate 202 under the gate 220. It is also worth noting that in FIG. 3, the spatial relationship between the gate 220, the active region 206 and the insulating structure 230 is emphasized, and the doped regions other than the active region 206 are not shown, but those skilled in the art are familiar with the art. The formation positions of the above constituent elements can be easily understood from the disclosure of Figs. 4 and 5, and the spatial relationship of the constituent elements will not be described again.

Please continue to see Figure 3. It should be noted that in the preferred embodiment, the active region 206 at the source end includes a body portion 206a and a plurality of finger portions 206b, and the finger portions 206b are as shown in FIGS. 3 to 5. It extends in the direction of the drain region 212.

Please also refer to Figures 3 to 5. As described above, in the preferred embodiment, before forming the gate 220, a patterned mask is formed and an etching process is performed, and a recess 232 is formed in the insulating structure 230 through the patterned mask. concave One of the grooves 232 has a depth that is less than a depth of the insulating structure 230, and one of the grooves 232 has a width smaller than a width of the insulating structure 230. A gate dielectric layer 222 and a gate conductive layer 224 are then sequentially formed on the substrate 202. As described above, since the gate dielectric layer 222 and the gate conductive layer 224 are filled in the recess 232, the finally formed gate 220 has two portions: a first gate disposed on the surface of the substrate 202. a portion 220a, and a second gate portion 220b extending downward from the first gate portion 220a and formed in the insulating structure recess 232, and the thickness and depth of the second gate portion 220b are respectively smaller than the width of the insulating structure 230 depth.

Please continue to see Figures 3 and 5. As shown in FIG. 3, since the etchant etches the insulating structure 230 through the active region 206 and the patterned mask in the preferred embodiment, the recess 232 and the second gate portion filled in the recess 232. 220b is as shown in Fig. 3, and a layout pattern of a comb shape is obtained. In other words, the second gate portion 220b includes a continuous shape and includes a comb shape that faces the source region 210 and the comb handle toward the drain region 212. As shown in FIGS. 4 and 5, the first gate portion 220a completely covers the second gate portion 220b, and the first gate portion 220a and the second gate portion 220b are perpendicular to each other and are in physical contact with each other, and A T-shaped gate 220 as shown in Figs. 4 and 5 is formed in the direction of the vertical substrate 202. More importantly, since the gate dielectric layer 222 is disposed between the first gate portion 220a and the substrate 202 and between the second gate portion 220b and the substrate 202, when a suitable voltage is applied to the gate 220 This T-shaped gate can be obtained Long current paths and large charge accumulation areas.

According to the HV MOS transistor device 200 provided in the preferred embodiment, a recess 232 is disposed in the insulating structure 230. Therefore, when the gate 220 is formed, a first gate formed on the surface of the substrate 202 is obtained. The portion 220a and a second gate portion 220b disposed in the recess 232. The HV MOS transistor element 200 provided in the preferred embodiment has a large current path and a charge accumulation region by the T-shaped gate 220 formed by the first gate portion 220a and the second gate portion 220b. At the same time, the expectation of lowering R _ON and increasing the breakdown voltage can be achieved. In addition, in the preferred embodiment, the channel width of the gate 220 is increased by the arrangement of the finger portion 206b of the active region 206, so that the HV MOS transistor device 200 provided by the preferred embodiment can have improved electrical performance. .

Please refer to FIG. 6 to FIG. 8 , wherein FIG. 6 is a partial layout diagram of a third preferred embodiment of the HV MOS transistor component provided by the present invention, and FIG. 7 is a D-D along the sixth diagram. 'The schematic diagram of the section obtained by the tangent line, and the 8th figure is the schematic diagram of the section obtained along the E-E' tangent line in Fig. 6. It should be noted that the same components in the preferred embodiment as the first preferred embodiment may include the same material selection or conductivity type, and therefore will not be further described in the following description. As shown in FIG. 6 to FIG. 8 , the HV MOS transistor device 300 of the preferred embodiment includes a substrate 302 , a gate 320 disposed on the substrate 302 , and an active layer formed in the substrate 300 . Area 306, and The gate 320 covers a portion of the active region 306. As shown in FIG. 7 and FIG. 8, in the active region 306, a p-type body region 308, an n-type source region 310, an n-type drain region 312, and a p-type doping region 314 are formed. An n-type high-pressure well region 316 and another n-type well region 318, and the STI 304 and the insulating structure 330, the relative relationship of the elements is as described in the first preferred embodiment, and thus will not be described herein. It should be noted that in FIG. 6 , the spatial relationship between the gate 320 , the active region 306 and the insulating structure 330 is emphasized, and the doped regions other than the n-type active region 306 are not illustrated, but the skill is familiar to the art. The position of the above-mentioned constituent elements can be easily known from the disclosure of Figures 7 and 8, so the spatial relationship of the constituent elements will not be described again.

Please continue to see Figure 6. It should be noted that in the preferred embodiment, the active region 306 at the source end also includes a body portion 306a and a plurality of finger portions 306b, and the finger portions 306b are as shown in FIGS. 6-8. It extends in the direction of the drain region 312.

Please also refer to Figures 6 to 8. As described above, in the preferred embodiment, before forming the gate 320, a patterned mask (not shown) is formed and an etching process is performed to form a recess 332 through the patterned mask in the insulating structure 330. The depth of one of the grooves 332 is less than the depth of one of the insulating structures 330, and the width of one of the grooves 332 is smaller than the width of one of the insulating structures 330. A gate dielectric layer 322 and a gate conductive layer 324 are then sequentially formed on the substrate 302. It is worth noting that the gate dielectric layer 322 and the gate conductive layer 324 The recess 320 is filled, so that the finally formed gate 320 has two portions: the first gate portion 320a disposed on the surface of the substrate 302 extends downward from the first gate portion 320a and is formed in the insulating layer. The second gate portion 320b within the structural recess 332.

Please continue to see Figures 6 and 8. As shown in FIG. 6, since the etchant etches the insulating structure 330 through the active region 306 and the patterned mask in the preferred embodiment, the recess 332 and the second gates filled in the recess 332 are formed. The portion 320b, as shown in Fig. 6, obtains a discontinuous shape, for example, an island-like layout pattern, respectively. In other words, each of the second gate portions 320b includes a discontinuous island shape, and the insulating structure 330 is inserted into the second gate portion 320b as shown in FIG. As shown in FIGS. 7 and 8, the first gate portion 320a completely covers the second gate portion 320b, and the first gate portion 320a and the second gate portion 320b are perpendicular to each other and physically contact each other, and A T-shaped gate 320 as shown in Figs. 7 and 8 is formed in the direction of the vertical substrate 302. More importantly, since the gate dielectric layer 322 is disposed between the first gate portion 320a and the substrate 302 and between the second gate portion 320b and the substrate 302, when a suitable voltage is applied to the gate 320 This T-shaped gate can obtain a longer current path and a larger charge accumulation region.

The HV MOS transistor element 300 according to the preferred embodiment is provided with a recess 332 in the insulating structure 330 adjacent to the drain region 312. Therefore, when the gate 320 is formed, a surface formed on the substrate 320 is obtained. The upper first gate portion 320a and the second gate portion 320b disposed in the recess 332. The HV MOS transistor element 300 provided by the preferred embodiment has a large current path and a charge accumulation region by the T-shaped gate 320 formed by the first gate portion 320a and the second gate portion 320b. At the same time, it is expected to reduce R _ON and increase the breakdown voltage. In addition, by increasing the channel width of the gate 320 by the arrangement of the finger portion 306b of the active region 306, the HV MOS transistor device 300 provided by the preferred embodiment can further improve the electrical performance.

In addition, from the first preferred embodiment to the third preferred embodiment, when the groove 132/232/332 required for the HV MOS transistor component 100/200/300 provided by the present invention is fabricated, the pattern is The opposing relationship of the mask to the active region 106/206/306 (and its finger portions 206b/306b) results in differently shaped grooves 132/232/332, and subsequently a second gate portion 120b/220b of a different shape is obtained /320b. When the patterned mask is near the 汲 extreme, the second gate portion 120b/220b/320b has a continuous shape, such as the U-shape of the opening shown in FIG. 1 facing the source region 110. When the patterned mask is disposed slightly closer to the source extreme direction, the second gate portion 120b/220b/320b may have a continuous shape, such as the comb shape shown in FIG. The second gate portion 120b/220b/320b has a discontinuous island shape as the patterned mask is placed closer to the source extreme. Briefly, the present invention can be adapted to different product needs by adjusting the patterned mask and active area. The relative relationship of 106/206/306 (and its finger portions 206b/306b) results in second gate portions 120b/220b/320b of different shapes.

In addition, please refer to FIG. 9 and FIG. 10, and FIG. 9 and FIG. 10 are respectively partial schematic views of other variations provided by the preferred embodiment. It should be noted that the relationship between the gate and the insulating structure is only shown in FIG. 9 and FIG. 10, but those skilled in the art should be able to easily think according to the disclosure of the first to third preferred embodiments. And other HV MOS transistors constitute the position of the components, so these components will not be described again. It should be noted that the gate and insulation structures illustrated in Figures 9 and 10 may be combined with any of the foregoing first to third preferred embodiments in accordance with the process or product requirements.

As shown in FIG. 9, in accordance with the gate 120/220/320 provided by the variation of the present invention, the first gate portion 120a/220a/320a still completely covers the second gate portion 120b/220b/320b, However, the first gate portions 120a/220a/320a and the second gate portions 120b/220b/320b form an L-shaped gate instead of a T-shaped gate. As shown in FIG. 10, in accordance with the variation of the present invention provided by the gate 120/220/320, when the recess 132/232/332 is formed in the insulating structure 130/230/330, the recess 132/232 The depth and width of /332 may be approximately equal to or less than the width of the insulating structure 130/230/330, such that the second gate portion 120b/220b/320b formed in the recess 132/232/332 achieves a greater width, The first gate portion 120a/220a/320a covers a portion of the second gate portion as shown in FIG. 120b/220b/320b for longer current paths. In addition, since the depth and width of the grooves 132/232/332 may be approximately equal to the width of the insulating structure 130/230/330, the gate conductive layer 124/224/324 may be formed when the gate conductive layer 124/224/324 is formed. Fill or not fill the groove 132/232/332.

It will thus be appreciated that the variations provided by the present invention are related to the size of the recesses 132/232/332 disposed within the insulating structure 130/230/330. It should be noted that the variation principle provided by the present invention is that the depth and width of the grooves 132/232/330 are respectively less than or equal to the depth and width of the insulating structure 130/230/330. Therefore, the thickness and width of the second gate portions 120b/220b/320b formed on the insulating structures 130/230/330 have a principle of less than the depth and width of the insulating structures 130/230/330.

In the above, the HV MOS transistor component provided by the present invention is provided with a recess in the insulating structure, and a gate portion is disposed in the recess, and according to the patterned mask and the active region for forming the recess. The relative relationship of (and its finger portions), the second gate portion provided by the present invention may comprise a continuous U-shape or comb shape, or comprise a discontinuous island shape. By virtue of the second gate portion disposed in the recess, the present invention successfully increases the length of the current path and the charge accumulation region, thereby simultaneously reducing the on-resistance for increasing the breakdown voltage, thereby achieving a reduction in on-resistance and breakdown voltage. ratio. In addition, the gate width of the gate is increased by the finger portion of the active region, so that the present invention can further improve the electrical performance of the HV MOS transistor component.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200, 300‧‧‧ high voltage MOS transistor components

102, 202, 302‧‧‧ base

104, 204, 304‧‧‧ shallow trench isolation

106, 206, 306‧‧‧ active areas

206a, 306a‧‧‧ active area main part

206b, 306b‧‧‧ active area finger

108, 208, 308‧‧‧ base area

110, 210, 310‧‧‧ source area

112, 212, 312‧‧ ‧ bungee area

114, 214, 314‧‧‧p-type doped regions

116, 216, 316‧‧‧n type high pressure well area

118, 218, 318‧‧‧n type well area

120, 220, 320‧‧‧ gate

120a, 220a, 320a‧‧‧ first gate part

120b, 220b, 320b‧‧‧ second gate part

122, 222, 322‧‧ ‧ gate dielectric layer

124, 224, 324‧‧ ‧ gate conductive layer

130, 230, 330‧‧‧ insulation structure

132, 232, 332‧‧‧ grooves

A-A’, B-B’, C-C’, D-D’, E-E’‧‧‧ tangent

1 is a partial layout diagram of a first preferred embodiment of a HV MOS transistor component provided by the present invention.

Fig. 2 is a schematic cross-sectional view taken along line A-A' in Fig. 1.

FIG. 3 is a partial layout diagram of a second preferred embodiment of a HV MOS transistor component provided by the present invention.

Fig. 4 is a schematic cross-sectional view taken along line B-B' in Fig. 3.

Fig. 5 is a schematic cross-sectional view taken along line C-C' in Fig. 3.

Figure 6 is a partial layout diagram of a third preferred embodiment of a HV MOS transistor component provided by the present invention.

Fig. 7 is a schematic cross-sectional view taken along line D-D' in Fig. 6.

Fig. 8 is a schematic cross-sectional view taken along line E-E' in Fig. 6.

9 and 10 are partial schematic views of other variations of the preferred embodiment, respectively.

100‧‧‧High voltage MOS transistor components

104‧‧‧Shallow trench isolation

106‧‧‧Active area

120‧‧‧ gate

120a‧‧‧first gate part

120b‧‧‧second gate part

130‧‧‧Insulation structure

132‧‧‧ Groove

A-A’‧‧‧ tangent

Claims (20)

A high voltage metal-oxide-semiconductor (HV MOS) transistor component, comprising: a substrate; at least one insulating structure disposed on the substrate, wherein the insulating structure includes a recess; a gate electrode disposed on the substrate, the gate further comprising: a first gate portion disposed on the surface of the substrate; and a second gate portion, the second gate portion being the first gate portion a portion extending downwardly and disposed in the recess; a gate dielectric layer disposed under the gate, and the gate dielectric layer simultaneously contacting the first gate portion and the second gate portion And a source region and a drain region are disposed in the substrate on both sides of the gate. The HV MOS transistor component of claim 1, wherein the first gate portion and the second gate portion are perpendicular to each other. The HV MOS transistor component of claim 1, wherein the first gate portion and the second gate portion are in physical contact with each other. The HV MOS transistor component of claim 1, wherein the second gate portion comprises a continuous shape. The HV MOS transistor component of claim 4, wherein the second gate portion comprises a U-shaped shape, and the opening of the U-shape is toward the source region. The HV MOS transistor component of claim 4, wherein the second gate portion comprises a comb shape. The HV MOS transistor component of claim 1, wherein the second gate portion comprises a discontinuous island shape. The HV MOS transistor component of claim 7, wherein the insulating structure is interposed in the second gate portion of the discontinuous island shape. The HV MOS transistor component of claim 1, wherein the first gate portion completely covers the second gate portion. The HV MOS transistor device of claim 9, wherein the first gate portion and the second gate portion form a T-shaped gate. The HV MOS transistor device of claim 9, wherein the first gate portion and the second gate portion form an L-shaped gate. For example, the HV MOS transistor component described in claim 1 is Wherein the first gate portion covers a portion of the second gate portion. The HV MOS transistor component of claim 1, wherein the insulating structure electrically isolates the second gate portion from the substrate. The HV MOS transistor device of claim 1, further comprising a gate dielectric layer disposed between the first gate portion and the substrate. The HV MOS transistor device of claim 14, wherein the gate dielectric layer is disposed between the second gate portion and the substrate. The HV MOS transistor component of claim 1, wherein one of the grooves has a depth less than a depth of the insulating structure. The HV MOS transistor component of claim 16, wherein a thickness of one of the second gate portions is less than the depth of the recess. The HV MOS transistor component of claim 1, wherein a width of one of the second gate portions is less than a width of the insulating structure. The HV MOS transistor component of claim 1, further comprising a doped region disposed in the substrate and the gate covering portion The doped region. The HV MOS transistor component of claim 19, wherein the doped region further comprises a plurality of finger portions, and the finger portions extend toward the drain region.