TWI527192B - Semiconductor structure and method of forming same - Google Patents

Description

Semiconductor structure and method of forming same

The present invention relates to a semiconductor structure and a method of forming the same, and more particularly to a metal oxide semiconductor structure and a method of forming the same.

In recent decades, the semiconductor industry has continued to shrink the size of semiconductor structures while improving the unit cost of speed, performance, density, and integrated circuits. In recent years, energy-saving ICs have become one of the key developments in semiconductor structures. Energy management ICs commonly use LDMOS or EDMOS as switches.

For example, in order to increase the breakdown voltage (BVdss) of a semiconductor structure such as a lateral double-diffused metal oxide semiconductor (LDMOS) or an extended-dip metal-oxide-semiconductor (EDMOS), one method is to reduce the doping concentration of the drain region and Increase the drift length. However, this method increases the specific opening resistance (Ron, sp) of the semiconductor structure, so that BVdss and Ron, sp cannot be simultaneously improved.

The present invention relates to a semiconductor structure and a method of forming the same. Semiconductor structures have excellent performance and are inexpensive to manufacture.

A semiconductor structure is provided. The semiconductor structure includes a first semiconductor region, a second semiconductor region, a dielectric structure, and a gate electrode layer. The first semiconductor region includes a first doped region and a second doped region. The first semiconductor region, the first doped region, and the second doped region have a first conductivity type. The second semiconductor region includes a third doped region. The second semiconductor region and the third doped region have opposite to the first conductive region Type of second conductivity type. The second doped region is adjacent between the first doped region and the third doped region. The second doped region has a doped diffusion. The doped diffusion extends from the top of the second doped region to the third doped region. The doped diffusion portion has a first conductivity type. The dielectric structure is on the first semiconductor region and the second semiconductor region. The gate electrode layer is on the dielectric structure.

A method of forming a semiconductor structure is provided. The method includes the following steps. A first semiconductor region is formed in the substrate. The first semiconductor region includes a first doped region and a second doped region. The first semiconductor region, the first doped region, and the second doped region have a first conductivity type. A second semiconductor region is formed in the substrate. The second semiconductor region includes a third doped region. The second semiconductor region and the third doped region have a second conductivity type opposite to the first conductivity type. The second doped region is adjacent between the first doped region and the third doped region. The second doped region has a doped diffusion. The doped diffusion extends from the top of the second doped region to the third doped region. The doped diffusion portion has a first conductivity type. A dielectric structure is formed on the first semiconductor region and the second semiconductor region. A gate electrode layer is formed on the dielectric structure.

Some embodiments are described below, and in conjunction with the drawings, a detailed description is as follows:

1 is a cross-sectional view of a semiconductor structure in accordance with an embodiment. The semiconductor structure includes a substrate 102. For example, substrate 102 includes, but is not limited to, an insulating layer overlying germanium (SOI), an epitaxial material, or a non-exfoliated material.

The first semiconductor region 104 is located on the substrate 102. The first semiconductor region 104 can include a well region 106, a first doped region 108, a second doped region 110, and a top doped region 120. The top doping region 120 is formed in the first doping region 108 and the second In the top portion of the doped region 110.

The well region 106, the first doped region 108, the second doped region 110, and the top doped region 120 have a first conductivity type such as an N conductivity type.

The second semiconductor region 112 includes a third doped region 114. The third doping region 114 has a second conductivity type, such as a P conductivity type, opposite to the first conductivity type. The third doped region 114 is adjacent to the first semiconductor region 104.

The second doping region 110 is adjacent between the first doping region 108 and the third doping region 114. In an embodiment, the second doped region 110 has a doped diffusion portion 122. The doped diffusion portion 122 extends from the top of the second doping region 110 toward the third doping region 114. Specifically, the doped diffusion portion 122 has a tip end that is in contact with the bottom surface of the first dielectric layer 124 of the dielectric structure 116. The doped diffusion portion 122 has a first conductivity type such as an N conductivity type.

Field plate doped region 128 may be formed in second doped region 110 of first semiconductor region 104 under dielectric structure 116. In an embodiment, the field plate doped region 128 has a second conductivity type, such as a P conductivity type.

A first heavily doped contact 130 is formed in the first doped region 108 of the first semiconductor region 104. The second heavily doped contact 132 and the third heavily doped contact 134 are formed in the third doped region 114 of the second semiconductor region 112. The first heavily doped contact 130 and the second heavily doped contact 132 have a first conductivity type, such as an N conductivity type. The third heavily doped contact 134 has a second conductivity type, such as a P conductivity type.

The dielectric structure 116 can be located on the first doped region 108 and the second doped region 110 of the first semiconductor region 104 and the third doped region 114 of the second semiconductor region 112. The dielectric structure 116 can be between the first heavily doped contact 130 and the second heavily doped contact 132.

The dielectric structure 116 includes a first dielectric layer 124 and a second dielectric layer 126. The first dielectric layer 124 is adjacent to the second dielectric layer 126. The first dielectric layer 124 and the second dielectric layer 126 may respectively comprise an oxide or a nitride, such as hafnium oxide or tantalum nitride, or other suitable high-k material. For example, the first dielectric layer 124 or the second dielectric layer 126 may have an oxide-nitride-oxide (ONO) structure.

The gate electrode layer 118 can be on the first dielectric layer 124 and the second dielectric layer 126 of the dielectric structure 116. Gate electrode layer 118 can comprise a metal, polysilicon, metal halide, or other suitable material.

The insulating structure 136 is not limited to the field oxide (FOX) shown in FIG. For example, the insulating structure 136 can be shallow trench isolation (STI) or deep trench isolation (DTI).

In some embodiments, the well region 106 of the first semiconductor region 104 is omitted, such that the first doped region 108 of the first semiconductor region 104 and the third doped region of the second doped region 110 and the second semiconductor region 112 The 114 series is formed in the substrate 102.

In an embodiment, the semiconductor structure is a metal oxide semiconductor (MOS) device, such as LDMOS or EDMOS. In detail, in the example in which the first conductivity type is the N conductivity type and the second conductivity type is the P conductivity type, the semiconductor structure is an N-channel LDMOS or an N-channel EDMOS. In contrast, in the example where the first conductivity type is a P conductivity type and the second conductivity type is an N conductivity type, the semiconductor structure is a P channel LDMOS or a P channel EDMOS. The first heavily doped contact 130 is used as a drain. The second heavily doped contact 132 serves as the source.

In an embodiment, the second doped region 110 located in the drift region has a net concentration of the first conductivity type dopant that is smaller than a net concentration of the first conductivity type dopant of the first doping region 108. Reduce the specific on-resistance (Ron, sp) of the device. The top doped region 120 is formed in the second doped region 110 (drift region), which can reduce the specific turn-on resistance of the device. The field plate doped region 128 located in the drift region forms a floating area and raises the breakdown voltage (BVdss) of the device.

Since the second doping region 110 of the first semiconductor region 104 has a doped diffusion portion 122 extending toward the third doping region 114 of the second semiconductor region 112, therefore. The effective channel length of the device is reduced and the channel resistance is reduced.

In an embodiment, the first dielectric layer 124 of the dielectric structure 116 has a uniform first thickness T1. The second dielectric layer 126 has a uniform second thickness T2. The first thickness T1 is smaller than the second thickness T2. In an embodiment, the first dielectric layer 124 is used as a gate dielectric layer. The use of a second dielectric layer 126 having a thickness thicker than the first dielectric layer 124 for insulating isolation can increase the breakdown voltage of the device. The thickness of the second dielectric layer 126 is less than the thickness of the insulating structure 136 to reduce the specific turn-on resistance of the device.

The first dielectric layer 124 and the second dielectric layer 126 have a flat common bottom surface S. The dielectric structure 116 of the embodiment can provide a shorter current path in the drift region of the device, as compared to the second dielectric layer using a field oxide comparative example (not shown), thereby reducing the specific turn-on resistance.

FIGS. 1 through 4 illustrate a method of forming a semiconductor structure in accordance with an embodiment. Referring to FIG. 2, a well region 106 is formed in the substrate 102 using a doping step.

Referring to FIG. 3, the first semiconductor region 104 and the second semiconductor region 112 are respectively formed in the well region 106 by a doping step. The portion in which the first semiconductor region 104 overlaps the second semiconductor region 112 is the second doped region 110. The order in which the first semiconductor region 104 and the second semiconductor region 112 are formed is not limited. In one embodiment, the first semiconductor region 104 is formed prior to the second semiconductor region 112. In another embodiment, the first semiconductor region 104 is formed after the second semiconductor region 112. After the doping step is performed to form the first semiconductor region 104 and the second semiconductor region 112, a thermal annealing step is performed. Since the first conductivity type of the first semiconductor region 104, for example, the N conductivity type dopant, and the second conductivity type of the second semiconductor region 112, such as the P conductivity type dopant, have different diffusion characteristics for the thermal diffusion step, causing thermal diffusion After the step, a second doped region 110 having a doped diffusion portion 122 is obtained. The thermal diffusion step may be performed at any point after the formation of the first semiconductor region 104 and the second semiconductor region 112, for example, before forming the field plate doped region 128, or after forming the gate electrode layer 118 (Fig. 4) .

Referring to FIG. 3, a field plate doped region 128 is then formed in the second doped region 110 by a doping step. In some embodiments, the well region 106 is omitted, such that the first doped region 108 of the first semiconductor region 104 and the second doped region 114 of the second doped region 110 and the second semiconductor region 112 are formed on the substrate 102. in.

Referring to FIG. 4, a dielectric structure 116 is formed over the first semiconductor region 104 and the second semiconductor region 102. For example, the first dielectric layer 124 and the second dielectric layer 126 of the dielectric structure 116 can be formed by thermal oxidation or deposition methods such as chemical vapor deposition or physical vapor deposition. In some embodiments, the lower portion of the second dielectric layer 126 can be formed first, and then formed in the first The upper portion of the second dielectric layer 126 is formed simultaneously with the dielectric layer 124. Referring to FIG. 4, a gate electrode layer 118 is formed on the dielectric structure 116.

Referring to FIG. 1 , a top doping region 120 is formed in the first doping region 108 and the second doping region 110 of the first semiconductor region 104 by a doping step. The top doped region 120 can be formed using the gate electrode layer 118 as a mask. A first heavily doped contact 130 and a second heavily doped contact 132 are formed in the first doped region 108 of the first semiconductor region 104 and the third doped region 114 of the second semiconductor region 112 by a doping step. A third heavily doped contact 134 is formed in the third doped region 114 using a doping step.

The semiconductor structure of the embodiment can be formed using a standard high voltage (HV) process, thus eliminating the need for an additional mask and reducing manufacturing costs.

Figure 5 illustrates a top view of a semiconductor structure in accordance with an embodiment. In some embodiments, the cross-sectional view of the semiconductor structure along line AB is as shown in FIG. A cross-sectional view of the semiconductor structure along the CD line is shown in FIG. Referring to FIGS. 5-7, FIG. 5 shows only the dielectric structure 216 of the semiconductor structure, the gate electrode layer 218, the first heavily doped contact 230, the second heavily doped contact 232, and the third heavily doped. Contact 234 and field plate doped region 228. Referring to FIGS. 5 and 7, a plurality of field plate doped regions 228 are separated from each other by a second doped region 210 of the first semiconductor region 204. The field plate doped region 228 of this example has a stripe shape (or rectangular shape, rectangular shape), but the disclosure is not limited thereto, and the field plate doped region 228 may also have a honeycomb shape, a hexagonal shape, an octagonal shape, and a circle shape. Circle, or square. The difference between the semiconductor structure shown in FIG. 7 and the semiconductor structure shown in FIG. 1 is that the top doped region 120 in FIG. 1 is omitted. Furthermore, the first heavily doped contact 230 is adjacent to the second doped region 210 of the first semiconductor region 204.

Figure 8 illustrates a top view of a semiconductor structure in accordance with an embodiment. In some embodiments, the cross-sectional view of the semiconductor structure along the EF line is as shown in FIG. A cross-sectional view of the semiconductor structure along the GH line is shown in FIG. Referring to FIGS. 8-10, FIG. 8 shows only the dielectric structure 316 of the semiconductor structure, the gate electrode layer 318, the first heavily doped contact 330, the second heavily doped contact 332, and the third heavily doped. Contact 334 and field plate doped region 328. The difference between the semiconductor structure shown in FIG. 8 and the semiconductor structure shown in FIG. 5 is that the gate electrode layer 318 has a plurality of mutually separated protrusions 338. The projections 338 correspond to the field plate doped regions 328. The projection 338 is not limited to the rectangular shape shown in FIG. 8, and for example, the projection 338 may have an arc shape, a triangular shape, or any other shape. The difference between the semiconductor structure illustrated in FIG. 10 and the semiconductor structure illustrated in FIG. 1 is that the first heavily doped contact 330 is adjacent to the second doped region 310 of the first semiconductor region 304.

11 is a top view of a semiconductor structure in accordance with an embodiment. In some embodiments, the cross-sectional view of the semiconductor structure along the IJ line is similar to the cross-sectional view of the semiconductor structure shown in FIG. The cross-sectional view of the semiconductor structure along the LM line is as shown in Fig. 12. Referring to FIG. 11 and FIG. 12, FIG. 11 shows only the dielectric structure 416 of the semiconductor structure, the gate electrode layer 418, the first heavily doped contact 430, the second heavily doped contact 432, and the third heavily doped. Contact 434 and field plate doped region 428. The difference between the semiconductor structure illustrated in FIGS. 11 and 12 and the semiconductor structure illustrated in FIGS. 5 and 7 is that the field plate doped regions 428 are laterally separated from each other.

Figure 13 is a top plan view of a semiconductor structure in accordance with an embodiment. In some embodiments, the cross-sectional view of the semiconductor structure along the OP line is similar to the cross-sectional view of the semiconductor structure shown in FIG. Semiconductor structure along the QR line The cross-sectional view is similar to the cross-sectional view of the semiconductor structure shown in FIG. The difference between the semiconductor structure shown in FIG. 13 and the semiconductor structure shown in FIG. 11 is that the field plate doped region 528 has a honeycomb shape (hexagonal shape). In other embodiments, the field plate doped region 528 can have a stripe shape, a rectangular shape (a rectangular shape, a square shape), an octagon shape, or a circular shape.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

102‧‧‧Base

104, 204, 304‧‧‧ First semiconductor area

106‧‧‧ Well Area

108‧‧‧First doped area

110, 210, 310, 410‧‧‧ second doped area

112‧‧‧second semiconductor area

114‧‧‧ Third doped area

116, 216, 316, 416‧‧‧ dielectric structure

118, 218, 318, 418‧‧ ‧ gate electrode layer

120‧‧‧Top doped area

122‧‧‧Doped diffusion

124‧‧‧First dielectric layer

126‧‧‧Second dielectric layer

128, 228, 328, 428, 528‧‧‧ field plate doping

130, 230, 330, 430‧‧‧ first heavily doped contacts

132, 232, 332, 432‧‧‧Second heavily doped contacts

134, 234, 334, 434‧‧‧ third heavily doped contacts

136‧‧‧Insulation structure

338‧‧‧protrusion

S‧‧‧ bottom surface

T1, T2‧‧‧ thickness

FIGS. 1 through 4 illustrate a semiconductor structure and a method of forming the same according to an embodiment.

Figure 5 illustrates a top view of a semiconductor structure in accordance with an embodiment.

Figure 6 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

FIG. 7 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 8 illustrates a top view of a semiconductor structure in accordance with an embodiment.

Figure 9 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 10 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

11 is a top view of a semiconductor structure in accordance with an embodiment.

Figure 12 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 13 is a top plan view of a semiconductor structure in accordance with an embodiment.

102‧‧‧Base

104‧‧‧First Semiconductor District

106‧‧‧ Well Area

108‧‧‧First doped area

110‧‧‧Second doped area

112‧‧‧second semiconductor area

114‧‧‧ Third doped area

116‧‧‧Dielectric structure

118‧‧‧ gate electrode layer

120‧‧‧Top doped area

122‧‧‧Doped diffusion

124‧‧‧First dielectric layer

126‧‧‧Second dielectric layer

128‧‧‧ Field plate doping area

130‧‧‧First heavily doped contact

132‧‧‧Second heavily doped contact

134‧‧‧ Third heavily doped contact

136‧‧‧Insulation structure

S‧‧‧ bottom surface

T1, T2‧‧‧ thickness

Claims (10)

A semiconductor structure includes a first semiconductor region including a first doped region and a second doped region, wherein the first semiconductor region, the first doped region, and the second doped region have a first a second semiconductor region includes a third doped region, wherein the second semiconductor region and the third doped region have a second conductivity type opposite to the first conductivity type, the second doping The doped region is adjacent between the first doped region and the third doped region, and the second doped region has a doped diffusion portion extending from a top of the second doped region to the third doped region The doped diffusion portion has the first conductivity type; a dielectric structure is disposed on the first semiconductor region and the second semiconductor region, the dielectric structure includes a first dielectric layer; and a gate electrode layer, Located on the dielectric structure; wherein the doped diffusion has a tip that is in contact with a bottom surface of the first dielectric layer of the dielectric structure. The semiconductor structure of claim 1, wherein the first semiconductor region further comprises a top doped region formed in a top portion of the first doped region, the top doped region having the first conductive type. The semiconductor structure of claim 1, wherein the first semiconductor region further comprises a top doped region formed in a top portion of the second doped region, the top doped region having the first conductive type. The semiconductor structure of claim 1, wherein a net concentration of the first conductivity type dopant of the second doping region is smaller than a net concentration of the first conductivity type dopant of the first doping region. . The semiconductor structure of claim 1, wherein the dielectric structure further comprises a second dielectric layer, the first dielectric layer adjoining the second dielectric layer. The semiconductor structure of claim 5, wherein the first dielectric layer has a uniform first thickness, and the second dielectric layer has a uniform second thickness, the first thickness being less than the first Two thicknesses. The semiconductor structure of claim 5, wherein the first dielectric layer and the second dielectric layer have a flat common bottom surface. The semiconductor structure of claim 1, further comprising at least one field plate doped region formed in the first semiconductor region under the dielectric structure, wherein the field plate doped region has the second conductive region type. The semiconductor structure of claim 8, wherein the gate electrode layer has a plurality of mutually separated protrusions, and the protrusions correspond to a plurality of the field plate doped regions. A method of forming a semiconductor structure includes: forming a first semiconductor region in a substrate, wherein the first semiconductor region includes a first doped region and a second doped region, the first semiconductor region, the first The doped region and the second doped region have a first conductivity type; a second semiconductor region is formed in the substrate, wherein the second semiconductor region includes a third doped region, the second semiconductor region and the first The third doped region has a second conductivity type opposite to the first conductivity type, the second doped region is adjacent between the first doped region and the third doped region, and the second doped region has a doped diffusion portion extending from a top of the second doping region to the third doping region, the doped diffusion portion having the first conductivity type; forming a dielectric structure in the first semiconductor region and the first Second semiconductor The dielectric structure includes a first dielectric layer; and a gate electrode layer is formed on the dielectric structure; wherein the doped diffusion portion has a bottom surface of the first dielectric layer and the dielectric structure a tip of contact.