TWI577014B - Heterojunction bipolar transistor - Google Patents
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- TWI577014B TWI577014B TW103124409A TW103124409A TWI577014B TW I577014 B TWI577014 B TW I577014B TW 103124409 A TW103124409 A TW 103124409A TW 103124409 A TW103124409 A TW 103124409A TW I577014 B TWI577014 B TW I577014B
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- 229910052751 metal Inorganic materials 0.000 description 25
- 239000002184 metal Substances 0.000 description 25
- 239000010410 layer Substances 0.000 description 19
- 239000011241 protective layer Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
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Description
本發明係有關一種異質接面雙極性電晶體,尤指一種具有較高的射極對基極面積比,以提高電晶體功率增益之異質接面雙極性電晶體。 The present invention relates to a heterojunction bipolar transistor, and more particularly to a heterojunction bipolar transistor having a higher emitter to base area ratio to improve transistor power gain.
近年來,隨著行動裝置產業的蓬勃發展,對高功率、高功率增益、高功率增益效率的需求日益增。由於化合物半導體異質接面雙極性電晶體積體電路具有高功率、高功率增益、高線性度等優點,常被應用於製作行動裝置中的功率放大器等元件,因此,若能改進化合物半導體異質接面雙極性電晶體佈局,將能有效提升功率增益及功率增益效率,提高產品競爭力。 In recent years, with the booming mobile device industry, there is an increasing demand for high power, high power gain, and high power gain efficiency. Due to the advantages of high power, high power gain, and high linearity of the compound semiconductor heterojunction bipolar electro-crystal volume circuit, it is often used to fabricate components such as power amplifiers in mobile devices. Therefore, if the compound semiconductor heterojunction can be improved The bipolar transistor layout will effectively improve power gain and power gain efficiency and enhance product competitiveness.
異質接面雙極性電晶體的輸出功率增益係與電晶體的基極與集極間接面電容有關,此接面電容值正比於基極面積。射極對基極面積比(emitter area/ base area,EA/BA)越大,則基極與集極間接面電容越小,因此增加射極對基極面積比,可有效縮小集極電容,進而提高輸出功率增益。 The output power gain of a heterojunction bipolar transistor is related to the base and collector indirect plane capacitance of the transistor. The junction capacitance is proportional to the base area. The larger the emitter-to-base area ratio (EA/BA) is, the smaller the base and collector indirect surface capacitance is. Therefore, the emitter-to-base area ratio is increased, and the collector capacitance can be effectively reduced. In turn, the output power gain is increased.
本發明之主要目的在於提供一種異質接面雙極性電晶體,其具有以下特徵:1.具有較高的射極對基極面積比(EA/BA),以提高異質接面雙極性電晶體之功率增益;2.具有較小的集極電阻,以提供異質接面雙極性電晶體之功率增益效 率;3.具有較佳的射極電流分佈,以增進異質接面雙極性電晶體的高功率運作能力。 The main object of the present invention is to provide a heterojunction bipolar transistor having the following characteristics: 1. having a higher emitter to base area ratio (EA/BA) to enhance the heterojunction bipolar transistor. Power gain; 2. Has a smaller collector resistance to provide power gain efficiency of a heterojunction bipolar transistor Rate; 3. Has a better emitter current distribution to enhance the high power operation capability of the heterojunction bipolar transistor.
為達上述目的,本發明提供一種異質接面雙極性電晶體,其包括:一個長條形基極平台、一個長條形基極電極、兩個長條形射極、一個長條形集極以及兩個長條形集極電極,其中前述之長條形基極電極係沿前述之基極平台之長軸設置於前述之基極平台之上,且前述之基極電極之中央處或鄰近中央處設有一個基極導孔;前述之兩個長條形射極係分別位於前述基極平台上、前述基極電極之兩側,且前述之射極區中的每一個其上方設有一個長條形射極電極;前述之集極係位於前述基極平台之下;而前述之兩個長條形集極電極係分別位於前述集極之上、前述之基極平台相對之兩側。 To achieve the above object, the present invention provides a heterojunction bipolar transistor comprising: an elongated base platform, an elongated base electrode, two elongated emitters, and a long strip collector And two long strip-shaped collector electrodes, wherein the long strip-shaped base electrode is disposed on the base platform along the long axis of the base platform, and at or near the center of the base electrode a base via hole is disposed at the center; the two elongated strip emitters are respectively located on the base platform and the two sides of the base electrode, and each of the foregoing emitter regions is disposed above a strip-shaped emitter electrode; the collector is located below the base platform; and the two strip-shaped collector electrodes are respectively located above the collector and opposite sides of the base platform .
本發明並提供另一種異質接面雙極性電晶體,其包括:一個長條形基極平台、一個工字形射極、兩個基極電極、一個長條形集極以及兩個長條形集極電極,其中前述之工字形射極係位於前述之基極平台上,其於工字形之兩側分別設有一凹陷部,且前述之工字形射極區上設有兩個長條形射極電極;前述之基極電極係分別設於前述基極平台上、前述工字形射極兩側之凹陷部內,且每一個基極電極於其鄰近基極平台中央處之一端設有一個基極導孔;前述之集極係位於前述基極平台之下;而前述之兩個長條形集極電極係分別位於前述集極之上、前述之基極平台相對之兩側。 The present invention also provides another heterojunction bipolar transistor comprising: an elongated base platform, an I-shaped emitter, two base electrodes, a long strip collector, and two long strip sets a pole electrode, wherein the aforementioned I-shaped emitter is located on the base platform, and a recess is respectively disposed on two sides of the I-shape, and two elongated emitters are disposed on the I-shaped emitter region The electrodes are respectively disposed on the base platform and the recesses on both sides of the I-shaped emitter, and each base electrode is provided with a base guide at one end of the base plate adjacent to the center of the base platform. a hole; the foregoing collector is located under the base platform; and the two elongated collector electrodes are respectively located above the collector and opposite sides of the aforementioned base platform.
於實施時,前述之基極電極係沿前述之基極平台之長軸,設置於前述基極平台上、前述基極平台之短軸中央處或鄰近中央處。 In the implementation, the base electrode is disposed on the base platform, at the center of the short axis of the base platform or adjacent to the center along the long axis of the base platform.
於實施時,前述之長條形基極平台之長寬比範圍為1.2:1至15:1。 In implementation, the aforementioned elongated base platform has an aspect ratio ranging from 1.2:1 to 15:1.
於實施時,前述之基極平台、射極電極及集極電極皆為長方形。 In the implementation, the base platform, the emitter electrode and the collector electrode are all rectangular.
於實施時,前述之工字形射極之凹陷部係設於前述之基極平台之短軸中央處或鄰近中央處。 In implementation, the recessed portion of the aforementioned I-shaped emitter is disposed at or near the center of the short axis of the aforementioned base platform.
於實施時,前述之基極平台、射極以及集極係為彎折的長條形,該彎折處係位於長條形之中央處或鄰近中央處。 In implementation, the aforementioned base platform, emitter, and collector are bent elongated strips that are located at or near the center of the elongated strip.
於實施時,前述之基極平台、射極以及集極係為彎折的長條形,該彎折處係位於長條形之中央處或鄰近中央處,且彎折的角度為90°。 In the implementation, the aforementioned base platform, the emitter and the collector are bent long strips, and the bends are located at or near the center of the elongated strip, and the angle of the bend is 90°.
為對於本發明之特點與作用能有更深入之瞭解,茲藉實施例配合圖式詳述於後。 For a better understanding of the features and functions of the present invention, the embodiments are described in detail below with reference to the drawings.
100、200、300‧‧‧異質接面雙極性電晶體 100, 200, 300‧‧‧ Heterojunction Bipolar Transistor
110、210、310‧‧‧基極平台 110, 210, 310‧‧‧ base platform
111、211a、211b、311‧‧‧基極電極 111, 211a, 211b, 311‧‧‧ base electrode
112、212a、212b、312‧‧‧基極導孔 112, 212a, 212b, 312‧‧‧ base guide hole
120a、120b、220、320a、320b‧‧‧射極 120a, 120b, 220, 320a, 320b‧‧ ‧ emitter
121a、121b、221、321a、321b‧‧‧射極電極 121a, 121b, 221, 321a, 321b‧‧‧ emitter electrodes
130、230、330‧‧‧集極 130, 230, 330‧‧ ‧ collector
131a、131b、231a、231b、331‧‧‧集極電極 131a, 131b, 231a, 231b, 331‧‧ ‧ collector electrodes
140a~140e、240a~240d‧‧‧第一金屬層之金屬導線 140a~140e, 240a~240d‧‧‧Metal wire of the first metal layer
150、250‧‧‧第二金屬層之金屬導線 150, 250‧‧‧Metal wire of the second metal layer
第1A及1B圖係為本發明所提供的一種異質接面雙極性電晶體之一實施例之俯視示意圖。 1A and 1B are top plan views of an embodiment of a heterojunction bipolar transistor provided by the present invention.
第2A及2B圖係為本發明所提供的一種異質接面雙極性電晶體之一實施例分別沿A-A’及B-B’線之剖面結構示意圖。 2A and 2B are schematic cross-sectional views of an embodiment of a heterojunction bipolar transistor according to the present invention taken along lines A-A' and B-B', respectively.
第3A及3B圖係為本發明所提供的一種異質接面雙極性電晶體之另一實施例之俯視示意圖。 3A and 3B are top plan views of another embodiment of a heterojunction bipolar transistor provided by the present invention.
第4、5及6圖係為本發明所提供的一種異質接面雙極性電晶體之其他實施例之俯視示意圖。 Figures 4, 5 and 6 are top plan views of other embodiments of a heterojunction bipolar transistor provided by the present invention.
第1A、1B、2A及2B圖所示係為本發明所提供的一種I型異質接面雙極性電晶體100之一實施例,其包括:一個長方形基極平台110、一個長方形基極電極111、兩個長方形射極120a、120b、一個長條形集極130以及兩個長方形集極電極131a、131b,其中長方形基極電極111係沿基極平 台110之長軸Y設置於基極平台110之上,且基極電極111之中央處或鄰近中央處設有一個基極導孔112;兩個長方形射極120a、120b係分別位於基極平台110上、基極電極111之兩側,且射極區120a、120b中的每一個其上方設有一長方形射極電極121a、121b;集極130係位於基極平台110之下;而兩個長方形集極電極131a、131b係分別位於集極130之上、基極平台110相對之兩側。 1A, 1B, 2A and 2B are an embodiment of a type I heterojunction bipolar transistor 100 provided by the present invention, comprising: a rectangular base platform 110 and a rectangular base electrode 111. Two rectangular emitters 120a, 120b, one elongated collector 130 and two rectangular collector electrodes 131a, 131b, wherein the rectangular base electrode 111 is flat along the base The long axis Y of the stage 110 is disposed on the base platform 110, and a base via hole 112 is disposed at or near the center of the base electrode 111; the two rectangular emitters 120a, 120b are respectively located on the base platform 110, on both sides of the base electrode 111, and each of the emitter regions 120a, 120b is provided with a rectangular emitter electrode 121a, 121b; the collector 130 is located below the base platform 110; and two rectangles The collector electrodes 131a and 131b are respectively located above the collector 130 and opposite sides of the base platform 110.
於實施時,上述之基極電極111、射極電極121以及集極電極131a、131b係分別電性連接於由一第一金屬層所形成之金屬導線(140a~140e),再透過第一金屬層電性連接於由一第二金屬層所形成之金屬導線150,藉由第一或第二金屬層與其他電子元件連接以構成所需電路。I型異質接面雙極性電晶體100與第一金屬層之間無電性連接的部份以一至多層保護層隔離(如160a),而第一金屬層與第二金屬層之間無電性連接的部份亦以至少一層保護層隔離(如160b、160c),保護層的材料必須具有電絕緣性,同時必需能防止金屬層或其他結構的材料擴散進入異質接面雙極性電晶體,在本實施例中,所述一至多層保護層可以氮化矽(SiN)、聚酰亞胺(polyimide)等隔絕性佳的材料構成。 In the implementation, the base electrode 111, the emitter electrode 121, and the collector electrodes 131a and 131b are electrically connected to the metal wires (140a-140e) formed by a first metal layer, and then pass through the first metal. The layer is electrically connected to the metal wire 150 formed by a second metal layer, and is connected to other electronic components by the first or second metal layer to form a desired circuit. The portion of the I-type heterojunction bipolar transistor 100 that is electrically connected to the first metal layer is isolated by one or more protective layers (eg, 160a), and the first metal layer and the second metal layer are not electrically connected. The part is also isolated by at least one protective layer (such as 160b, 160c). The material of the protective layer must be electrically insulating, and it must be prevented from diffusing into the heterojunction bipolar transistor in the metal layer or other structure. In one example, the one to more protective layers may be made of a material having good insulating properties such as tantalum nitride (SiN) or polyimide.
集極與射極間電阻(RCE)與集極與射極相鄰周長的長度相關,集極與射極相鄰周長長度越長,則RCE越低。本發明所提供之異質接面雙極性電晶體中,集極位於射極之兩側的設計可增加集極與射極相鄰周長的長度,因此能降低集極電阻RCE,進而提供異質接面雙極性電晶體之功率增益效率。此外,本發明所提供之設計中,電晶體運作時是從第一金屬層通過基極導孔向電晶體輸入訊號,由於基極導孔是位於電晶體的中央處,使得射極電流的分布為對稱或接近對稱,因此能增進異質接面雙極性電晶體的高功率運作能力。 The collector-to-emitter resistance (R CE ) is related to the length of the collector and the emitter's adjacent perimeter, and the longer the perimeter of the collector and emitter is, the lower the R CE is . In the heterojunction bipolar transistor provided by the present invention, the design of the collector on both sides of the emitter can increase the length of the perimeter of the collector and the emitter, thereby reducing the collector resistance R CE and providing heterogeneity The power gain efficiency of the junction bipolar transistor. In addition, in the design provided by the present invention, the transistor operates by inputting a signal from the first metal layer through the base via hole to the transistor, and the emitter current is distributed because the base via hole is located at the center of the transistor. Symmetrical or nearly symmetrical, thus improving the high power operation capability of heterojunction bipolar transistors.
在本實施例中,為達到最佳的射極對基極之面積比,前述之長方形基極平台之長寬比範圍可為1.2:1至15:1中的任意值,例如2:1、3:1、4:1、5:1、6:1、7:1、8:1、9:1、10:1、11:1、12:1、13:1、14:1或15:1,其中以2:1至12:1為較佳,3:1至12:1為更佳,或甚至4:1至10:1為更佳。 In this embodiment, in order to achieve an optimum ratio of the emitter to the base, the aspect ratio of the rectangular base platform may be any value from 1.2:1 to 15:1, for example, 2:1. 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, 11:1, 12:1, 13:1, 14:1 or 15: 1, preferably 2:1 to 12:1, more preferably 3:1 to 12:1, or even 4:1 to 10:1.
前述之基極、射極、集極及設於其上之基極、射極、集極電極亦可為其他任意長條形的形狀,例如橢圓形,只要長條形的長軸彼此保持平行即可,如第4圖所示。 The base, the emitter, the collector, and the base, the emitter, and the collector electrode disposed thereon may be any other elongated shape, such as an elliptical shape, as long as the long axes of the elongated lines are parallel to each other That's it, as shown in Figure 4.
前述之基極、射極、集極及設於其上之基極、射極、集極電極亦可為任意彎折的長條形,其可具有一或多個彎折處,如第6圖所示之具有一個彎折處的L形異質接面雙極性電晶體300,其基極平台310、兩個射極320a、320b、集極330皆為L形,其彎折角度可為大於0°至小於180°,在第6圖所示的實施例中,該彎折角度約為90°。 The base, the emitter, the collector, and the base, the emitter, and the collector electrode disposed thereon may be any bent elongated shape, and may have one or more bends, such as the sixth The L-shaped heterojunction bipolar transistor 300 has a bent portion, and the base platform 310, the two emitters 320a, 320b, and the collector 330 are all L-shaped, and the bending angle can be greater than 0° to less than 180°, in the embodiment shown in Fig. 6, the bending angle is about 90°.
第3A及3B圖係為本發明所提供的一種H型異質接面雙極性電晶體200之一實施例之俯視示意圖,其包括:一個長方形基極平台210、一個工字形射極220、兩個基極電極211a、211b、一個長方形集極230以及兩個長條形集極電極231a、231b,其中工字形射極220係位於基極平台210上,其於工字形之兩側分別設有一凹陷部222a、222b,且工字形射極區220上設有一個工字形射極電極221;基極電極211a、211b係分別設於基極平台210上、工字形射極220兩側之凹陷部222a、222b內,且每一個基極電極211a/211b於其鄰近基極平台210中央處之一端設有一個基極導孔212a/212b;而前述之長方形集極230係位於基極平台210之下,兩個長條形集極電極231a、231b係分別位於集極230之上、基極平台210相對之兩側。 3A and 3B are top plan views of an embodiment of an H-type heterojunction bipolar transistor 200 provided by the present invention, comprising: a rectangular base platform 210, an I-beam emitter 220, and two a base electrode 211a, 211b, a rectangular collector 230 and two elongated collector electrodes 231a, 231b, wherein the I-shaped emitter 220 is located on the base platform 210, and a recess is respectively arranged on both sides of the I-shaped The portion 222a, 222b, and the I-shaped emitter region 220 is provided with an I-shaped emitter electrode 221; the base electrodes 211a, 211b are respectively disposed on the base platform 210, the recessed portion 222a on both sides of the I-shaped emitter 220 222b, and each of the base electrodes 211a/211b is provided with a base via 212a/212b at one end of the base of the base platform 210; and the aforementioned rectangular collector 230 is located under the base platform 210. The two strip-shaped collector electrodes 231a and 231b are respectively located above the collector 230 and opposite sides of the base platform 210.
於實施時,上述之基極電極211a、211b、射極電極221以及集極電極231a、231b係分別電性連接於由一第一金屬層所形成之金屬導線 (240a~240d),再透過第一金屬層電性連接於由一第二金屬層所形成之金屬導線250,藉由該第一或第二金屬層與其他電子元件連接以構成所需電路。H型異質接面雙極性電晶體200與第一金屬層之間無電性連接的部份以一至多層保護層隔離,而第一金屬層與第二金屬層之間無電性連接的部份亦以至少一層保護層隔離,保護層的材料必須具有電絕緣性,同時必需能防止金屬層或其他結構的材料擴散進入異質接面雙極性電晶體,在本實施例中,所述一至多層保護層可以氮化矽(SiN)、聚酰亞胺(polyimide)等隔絕性佳的材料構成。 In the implementation, the base electrodes 211a and 211b, the emitter electrode 221 and the collector electrodes 231a and 231b are electrically connected to the metal wires formed by a first metal layer. (240a-240d) is electrically connected to the metal wire 250 formed by a second metal layer through the first metal layer, and the first or second metal layer is connected to other electronic components to form a desired circuit. The portion of the H-type heterojunction bipolar transistor 200 that is electrically connected to the first metal layer is isolated by one or more protective layers, and the portion of the first metal layer and the second metal layer that is not electrically connected is also At least one protective layer is isolated, and the material of the protective layer must be electrically insulated, and at the same time, it is necessary to prevent the material of the metal layer or other structure from diffusing into the heterojunction bipolar transistor. In this embodiment, the one to more protective layers may be It is composed of a material having excellent barrier properties such as tantalum nitride (SiN) or polyimide.
在本實施例中,為達到最佳的射極對基極之面積比,前述之長方形基極平台之長寬比範圍可為1.2:1至15:1中的任意值,例如2:1、3:1、4:1、5:1、6:1、7:1、8:1、9:1、10:1、11:1、12:1、13:1、14:1或15:1,其中以2:1至12:1為較佳,3:1至12:1為更佳,或甚至4:1至10:1為更佳。 In this embodiment, in order to achieve an optimum ratio of the emitter to the base, the aspect ratio of the rectangular base platform may be any value from 1.2:1 to 15:1, for example, 2:1. 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, 11:1, 12:1, 13:1, 14:1 or 15: 1, preferably 2:1 to 12:1, more preferably 3:1 to 12:1, or even 4:1 to 10:1.
前述之基極、射極、集極及設於其上之基極、射極、集極電極亦可為其他任意長條形的形狀,例如橢圓形,只要長條形的長軸彼此保持平行即可,如第5圖所示。 The base, the emitter, the collector, and the base, the emitter, and the collector electrode disposed thereon may be any other elongated shape, such as an elliptical shape, as long as the long axes of the elongated lines are parallel to each other That's it, as shown in Figure 5.
本發明具有以下優點: The invention has the following advantages:
1.本發明所提供的長條形異質接面雙極性電晶體,具有較高的射極對基極面積比(EA/BA),使異質接面雙極性電晶體之功率增益得以提高。 1. The strip-shaped heterojunction bipolar transistor provided by the invention has a high emitter-to-base ratio (EA/BA), which improves the power gain of the heterojunction bipolar transistor.
2.集極位於射極之兩側的設計可增加集極與射極相鄰周長的長度,並藉由將射極與集極設計成長條形來獲得較長的週長,因此能得到相對較低的集極與射極間電阻RCE,進而提供異質接面雙極性電晶體之功率增益效率。 2. The design of the collector on both sides of the emitter can increase the length of the perimeter of the collector and the emitter, and obtain a longer perimeter by designing the emitter and the collector to form a strip, thus obtaining The relatively low collector-to-emitter resistance R CE provides the power gain efficiency of the heterojunction bipolar transistor.
3.射極電流的分布為對稱或接近對稱,因此能增進異質接面雙極性電晶體的高功率運作能力。 3. The distribution of the emitter current is symmetric or nearly symmetrical, thus improving the high power operation capability of the heterojunction bipolar transistor.
綜上所述,本發明提供之異質接面雙極性電晶體確實可達到 預期之目的,能提供較高的射極對基極面積比,使異質接面雙極性電晶體之功率增益得以提高。此外,本發明提供之異質接面雙極性電晶體具有較小的集極與射極間電阻,可提高異質接面雙極性電晶體的功率增益效率,其為該異質接面雙極性電晶體製作的功率放大器的主要性能訴求。其確具產業利用之價值,爰依法提出發明專利申請。 In summary, the heterojunction bipolar transistor provided by the present invention can be achieved The intended purpose is to provide a higher emitter-to-base ratio, which increases the power gain of the heterojunction bipolar transistor. In addition, the heterojunction bipolar transistor provided by the invention has a small collector-to-emitter resistance, which can improve the power gain efficiency of the heterojunction bipolar transistor, which is fabricated by the heterojunction bipolar transistor. The main performance appeal of the power amplifier. It does have the value of industrial use, and it submits invention patent applications according to law.
又上述說明與圖示僅是用以說明本發明之實施例,凡熟於此業技藝之人士,仍可做等效的局部變化與修飾,其並未脫離本發明之技術與精神。 The above description and the drawings are merely illustrative of the embodiments of the present invention, and those skilled in the art can still make equivalent local variations and modifications without departing from the spirit and scope of the invention.
100‧‧‧異質接面雙極性電晶體 100‧‧‧ Heterojunction bipolar transistor
110‧‧‧基極平台 110‧‧‧base platform
111‧‧‧基極電極 111‧‧‧ base electrode
112‧‧‧基極導孔 112‧‧‧Base guide hole
120a、120b‧‧‧射極 120a, 120b‧‧ ‧ emitter
121a、121b‧‧‧射極電極 121a, 121b‧‧ ‧ emitter electrode
130‧‧‧集極 130‧‧‧ Collector
131a、131b‧‧‧集極電極 131a, 131b‧‧‧ collector electrode
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103124409A TWI577014B (en) | 2014-07-16 | 2014-07-16 | Heterojunction bipolar transistor |
| US14/692,227 US20160020307A1 (en) | 2014-07-16 | 2015-04-21 | Heterojunction Bipolar Transistor |
| US15/204,659 US9911837B2 (en) | 2014-07-16 | 2016-07-07 | Heterojunction bipolar transistor |
| US15/875,700 US10553709B2 (en) | 2014-07-16 | 2018-01-19 | Heterojunction bipolar transistor |
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| TW103124409A TWI577014B (en) | 2014-07-16 | 2014-07-16 | Heterojunction bipolar transistor |
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| TWI577014B true TWI577014B (en) | 2017-04-01 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5140399A (en) * | 1987-04-30 | 1992-08-18 | Sony Corporation | Heterojunction bipolar transistor and the manufacturing method thereof |
| TW200408124A (en) * | 2002-11-08 | 2004-05-16 | Win Semiconductors Corp | Heterojunction bipolar transistor power transistor |
| US20060017065A1 (en) * | 2004-07-21 | 2006-01-26 | Sony Corporation | Bipolar transistor and fabrication method of the same |
| US20070012949A1 (en) * | 2005-07-13 | 2007-01-18 | Katsuhiko Kawashima | Bipolar transistor and power amplifier |
| TW200939471A (en) * | 2008-03-10 | 2009-09-16 | Silicon Based Tech Corp | A semiconductor device and its manufacturing methods |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5140399A (en) * | 1987-04-30 | 1992-08-18 | Sony Corporation | Heterojunction bipolar transistor and the manufacturing method thereof |
| TW200408124A (en) * | 2002-11-08 | 2004-05-16 | Win Semiconductors Corp | Heterojunction bipolar transistor power transistor |
| US20060017065A1 (en) * | 2004-07-21 | 2006-01-26 | Sony Corporation | Bipolar transistor and fabrication method of the same |
| US20070012949A1 (en) * | 2005-07-13 | 2007-01-18 | Katsuhiko Kawashima | Bipolar transistor and power amplifier |
| TW200939471A (en) * | 2008-03-10 | 2009-09-16 | Silicon Based Tech Corp | A semiconductor device and its manufacturing methods |
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