TWI575492B - Gate driving circuit - Google Patents

Description

Gate drive circuit

The present invention relates to a gate driving circuit, and more particularly to a gate driving circuit for recharging a node to output a gate driving signal after a touch detection phase.

As technology evolves, today's panels are often integrated with display and touch functions to provide a convenient interface to the user. In an in-cell touch panel, the in-cell touch panel is provided with a gate driving circuit and a touch circuit on the same substrate, and the gate driving signal line and the touch signal line may be mutually Very close, so the gate drive signal and the touch signal will interfere with each other. Due to the strong intensity of the gate drive signal, the gate drive signal often causes noise and interferes with the touch signal through the capacitive coupling effect, and reduces the signal to noise ratio (SNR) of the touch operation.

In the conventional method, in order to prevent the touch signal from being disturbed by the gate driving signal, generally, during the touch sensing period of the enabling touch circuit, several specific signals in the gate driving circuit are pulled down to the low level. The level is to prevent the gate driving circuit and the touch circuit from operating at the same time and interfere with each other. However, at the same time, how to make the gate driving circuit resume normal operation after the touch sensing period becomes a problem that must be considered when designing the gate driving circuit. On the other hand, since the components of the gate driving circuit are susceptible to long-term voltage stress under such a structure, the components in the gate driving circuit are also prone to aging problems.

The present invention is directed to a gate drive circuit that is capable of re-operational operation after a touch sensing period and prevents components in the gate drive circuit from ageing too quickly.

The gate driving circuit disclosed in the present invention comprises a driving switch, an input module, a pull-down module, a first switch, a second switch, a third switch, a capacitor and a reset switch. The input module is coupled to the first node. The pull-down module is coupled to one end of the drive switch. One end of the first switch is coupled to the charging signal end, the other end is coupled to the second node, and the control end is coupled to the storage node. The storage node is fed into the input signal. One end of the second switch is coupled to the second reference voltage end, the other end is coupled to the third node, and the control end is coupled to the storage node. One end of the third switch is coupled to the third node, the other end is coupled to the first node, and the control end is coupled to the second node. The two ends of the capacitor are respectively coupled to the storage node and the second node. One end of the reset switch is coupled to the first node, the other end is coupled to the first reference voltage end, and the control end is coupled to the reset signal end. The driving switch selectively adjusts the voltage level of the driving signal to the voltage level of the clock signal according to the voltage level of the first node, and the first node is fed into the input signal. The input module is configured to selectively adjust the voltage level of the input signal according to the driving signal of the previous stage or the driving signal of the subsequent stage. The pull-down module is configured to selectively couple the driving switch to the first reference voltage terminal according to the first pull-down signal or the second pull-down signal to adjust the voltage level of the driving signal.

In summary, the present invention provides a gate driving circuit that pre-stores a data voltage in a storage node, thereby suspending the operation of the gate driving circuit and venting some nodes during the touch sensing phase. The voltage is applied to prevent the component from being subjected to long-term bias stress. And after the end of the touch sensing phase, the corresponding node is recharged with the voltage stored by the storage node and the corresponding switching element. Thereby, the gate driving circuit can generate the desired gate driving signal again after the touch sensing period, and at the same time, the components in the gate driving circuit are prevented from being rapidly aged due to the long-term bias stress.

The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1. FIG. 1 is a functional block diagram of a gate driver according to an embodiment of the invention. As shown in FIG. 1, the gate driver 1 includes gate driving circuits 10_1 to 10_N. Where N is a positive integer greater than 3. In this embodiment, the gate driving circuits 10_1~10_N are sequentially connected in series, and the gate driving circuits 10_1~10_N are used to generate the driving signals G[1]~G[N]. In more detail, the gate driving circuit 10_1 generates the driving signal G[1] in accordance with the clock signal CK and the enable signal ST[1]. The start signal ST[1] is defined by those skilled in the art and is not limited herein. Similarly, the gate driving circuit 10_2 generates the driving signal G[2] according to the clock signal CK and the driving signal G[1]. As for the related actions of the gate driving circuits 10_3~10_N, etc., the analogy can be analogized with the above contents according to FIG. 1 and will not be described herein. The gate driving circuits 10_1~10_N are made, for example, in an amorphous silicon (A-Si) process, a poly-Silicon process, or a low-temperature silicon substrate process, and are not used here. limit. The following is an example of the architecture of FIG. 1. However, the gate driver 1 can also adopt a two- or one-pass architecture, and is not limited to this embodiment.

Please refer to FIG. 2, which is a circuit diagram of an embodiment of one of the gate driving circuits according to FIG. In the embodiment corresponding to FIG. 2, the gate driving circuit 10_N is taken as an example. However, the structure and operation of the remaining gate driving circuit are similar to those of the gate driving circuit 10_N, and those skilled in the art have a general knowledge. Can be derived from this specification. As shown in FIG. 2, the gate driving circuit 10_N has a driving switch Td, an input module 120, a pull-down module 140, a first switch T1, a second switch T2, a third switch T3, a capacitor C1, and a reset switch Trst.

The first end of the driving switch Td is coupled to the clock signal end to receive the clock signal CK. The second end of the driving switch Td is coupled to the output terminal NG, and the driving switch Td selectively provides the driving signal G[N] via the output terminal NG. The control terminal of the driving switch Td is coupled to the first node NQ, the first node NQ is fed with the input signal Sin, and the first node NQ has a voltage level Q[N]. The input module 120 is coupled to the first node NQ, and the input module 120 receives the first input voltage U2D, the second input voltage D2U, the driving signal G[N-1] of the previous stage, and the driving signal G[N+ of the subsequent stage. 1]. The pull-down module 140 is coupled to the output terminal NG and the first reference voltage terminal, and the pull-down module 140 receives the first reference voltage VSS via the first reference voltage terminal. The voltage regulator module 160 is coupled to the first node NQ and the first reference voltage terminal, and the voltage regulator module 160 receives the first reference voltage VSS via the first reference voltage terminal. Subsequent description will be made with the first reference voltage VSS being a low voltage level.

In an embodiment, when the scanning direction is from top to bottom, the first input voltage U2D is at a high voltage level, the second input voltage D2U is at a low voltage level, and when the scanning direction is from bottom to top. The first input voltage U2D is a low voltage level, and the second input voltage D2U is a high voltage level. The scanning direction and the relative sizes of the first input voltage U2D and the second input voltage D2U are freely defined by those skilled in the art and will not be described herein. The following is an embodiment in which the scanning direction is from top to bottom, and the first input voltage U2D is at a high voltage level and the second input voltage D2U is at a low voltage level.

One end of the first switch T1 is coupled to the charging signal, and the other end of the first switch T1 is coupled to the second node NB. The control end of the first switch T1 is coupled to the storage node NA. The storage node NA is fed into the input signal Sin. The storage node NA has a voltage level A[N], and the second node NB has a voltage level B[N]. One end of the second switch T2 is coupled to the second reference voltage VDD, the other end of the second switch T2 is coupled to a third node NC, and the control end of the second switch T2 is coupled to the storage node NA. Subsequent description will be made with the second reference voltage VDD being at a high voltage level. The third switch T3 is coupled to the third node NC, the other end of the third switch T3 is coupled to the first node NQ, and the control end of the third switch T3 is coupled to the second node NB. The two ends of the capacitor C1 are respectively coupled to the storage node NA and the second node NB. One end of the reset switch Trst is coupled to the first node NQ, the other end of the reset switch Trst is coupled to the first reference voltage terminal to receive the first reference voltage VSS, and the control end of the reset switch Trst is coupled to the reset signal terminal for receiving Reset signal Srst. The third node NC has a voltage level C[N].

The driving switch Td selectively adjusts the voltage level of the driving signal G[N] to the voltage level of the clock signal CK[N] according to the voltage level Q[N] of the first node NQ. From another perspective, the drive switch Td is controlled by the voltage level Q[N] to selectively conduct the output terminal NG to the clock signal terminal. In an embodiment, when the voltage level Q[N] is a high voltage level, the driving switch Td is turned on to adjust the voltage level of the driving signal G[N] to the voltage level of the clock signal CK[N]. Bit.

The input module 120 is configured to selectively adjust the voltage level of the input signal Sin to the first input voltage U2D according to the driving signal G[N-1] of the previous stage or the driving signal G[N+1] of the subsequent stage. The second input voltage D2U. In the embodiment shown in FIG. 2, the input module 120 has, for example, a first input switch Tin1 and a second input switch Tin2. One end of the first input switch Tin1 receives the first input voltage U2D, and the other end of the first input switch Tin1 is coupled to the first node NQ, and the control end of the first input switch Tin1 receives the driving signal G[N-1] of the previous stage. One end of the second input switch Tin2 receives the second input voltage D2U, the other end of the second input switch Tin2 is coupled to the first node NQ, and the control end of the second input switch Tin2 receives the drive signal G[N+1] of the subsequent stage. Therefore, when the driving signal G[N-1] of the current stage is the high voltage level and the driving signal G[N+1] of the subsequent stage is the low voltage level, the first input switch Tin1 is turned on and the second input switch Tin2 is not turned on. The voltage level Q[N] of the first node NQ is adjusted to the first input voltage U2D. When the driving signal G[N-1] of the current stage is the low voltage level and the driving signal G[N+1] of the subsequent stage is the high voltage level, the first input switch Tin1 is not turned on and the second input switch Tin2 is turned on, The voltage level Q[N] of a node NQ is adjusted to the second input voltage D2U.

The pull-down module 140 is configured to selectively couple the output terminal NG to the first reference voltage terminal according to the first pull-down signal XCK or the second pull-down signal P[N] to selectively drive the driving signal G[N] The voltage level is adjusted to the first reference voltage VSS. The first pull-down signal XCK is, for example, a reverse clock signal CK, and the second pull-down signal P[N] is, for example, a voltage level of a node of the gate driving circuit 10_N or an external driving signal. Here, the second pull-down signal P[N] is taken as an example of the voltage level of a node in the gate driving circuit 10_N. The above is merely an example and is not limited to this. As shown, the pull-down module 140 has, for example, pull-down switches Tpd1, Td2. The two ends of the pull-down switch Tpd1 are respectively coupled to the output end NG and the first reference voltage end, and the control end of the pull-down switch Tpd1 receives the first pull-down signal XCK. The two ends of the pull-down switch Tpd2 are respectively coupled to the output terminal NG and the first reference voltage terminal, and the control terminal of the pull-down switch Tpd2 receives the second pull-down signal P[N]. When one of the first pull-down signal XCK and the second pull-down signal P[N] is at a high voltage level, the pull-down switches Tpd1 and Tpd2 are correspondingly turned on to couple the output terminal NG to the first reference voltage terminal. .

In addition, in the embodiment shown in FIG. 2, the gate driving circuit 10_N further has a capacitor C2 and a fourth switch T4. The two ends of the capacitor C2 are respectively coupled to one end of the driving switch Td and the control end of the driving switch Td to form a coupling path. The two ends of the fourth switch T4 are coupled between the first node NQ and the storage node NA, and the control end of the fourth switch T4 receives the first pull-down signal XCK. The fourth switch T4 selectively feeds the input signal Sin to the storage node NA according to the first pull-down signal XCK. In this embodiment, when the first pull-down signal XCK is at a high voltage level, the fourth switch T4 is turned on to feed the input signal Sin to the storage node NA. In other embodiments, the input signal Sin may be fed into the storage node NA in a different manner, which is illustrated by other examples.

For the sake of brevity, the above-mentioned high voltage level VH is defined as the high voltage level mentioned later, and the above low voltage level is defined as the same low voltage level VL. However, in practice, each of the above signals may have different high voltage levels or different low voltage levels, which are freely designed by those skilled in the art and are not limited herein.

Please refer to FIG. 3 together to explain the operation mode of the gate driving circuit. FIG. 3 is a timing diagram of the gate driving circuit according to FIG. As shown in FIG. 3, one operation period of the gate driving circuit 10_N is defined with a pull-up phase ST1, a touch sensing phase ST2, a recharging phase ST3, a driving phase ST4, a transition phase ST5, and a pull-down phase ST6. When the touch panel of the gate driving circuit 10_N is touch-sensed, the gate driving circuit 10_N enters the touch sensing stage ST2, and then enters the recharging stage ST3, and sequentially enters the driving stage. ST4, transition phase ST5 and pulldown phase ST6. When the touch panel to which the gate driving circuit 10_N belongs is not touch-sensed, the gate driving circuit 10_N sequentially enters the pull-up phase ST1, the recharging phase ST3, the driving phase ST4, the transition phase ST5, and the pull-down phase ST6. The operation mode of the touch sensing by the touch panel to which the gate driving circuit 10_N belongs is described as an example.

In the pull-up phase ST1, the drive signal G[N-1] of the previous stage and the first pull-down signal XCK are at the high voltage level VH. At this time, the first input switch Tin1, the first switch T1, the second switch T2, the fourth switch T4, the drive switch Td, and the pull-down switch Tpd1 are turned on. Correspondingly, the voltage level of the input signal Sin is adjusted to the first input voltage U2D, and the input signal Sin is fed to the first node NQ and the storage node NA such that the voltage level Q[N] of the first node NQ is The voltage level A[N] of the storage node NA is nearly the same. The voltage level B[N] of the second node NB is a low voltage level VL. The voltage level C[N] of the third node NC is a high voltage level VH. The output terminal NG is coupled to the first reference voltage terminal, so the driving signal G[N] is the low voltage level VL. Wherein, the voltage levels of the three terminals of the second switch T2 are close to the high voltage level VH or equal to the high voltage level VH, so the second switch T2 is less affected by the bias stress at this stage, Therefore, it does not deteriorate rapidly and still retains the original charging capability. According to the above operation mode, the first switch T1, the second switch T2 and the third switch T3 can also be defined as a temporary storage module for temporarily storing the voltage of the input signal Sin in the storage node NA of the temporary storage module. .

In an embodiment, the voltage level of each node in the pull-up phase ST1 can be expressed as follows: Q[N]=VH-VTH_Tin1 G[N]=VL A[N]=VH-VTH_Tin1 B[N]=VL C[N]=VH-VTH_Tin1-VTH_T2 where VTH_Tin1 is the turn-on voltage of the first input switch Tin1, and VTH_T2 is the turn-on voltage of the second switch T2.

In the touch sensing phase ST2, the touch panel to which the gate driving circuit 10_N belongs performs touch sensing, the reset signal Srst is pulled to the high voltage level VH, and the other signals shown in FIG. 3 are low voltage. Bit VL. At this time, the reset switch Trst is turned on, the first node NQ is coupled to the first reference voltage terminal, and the voltage level Q[N] is correspondingly pulled down to the low voltage level VL, and the driving signal G[N] is also It is a low voltage level VL. Since the storage node NA temporarily stores the voltage level of the input signal Sin, the first switch T1 and the second switch T2 are also turned on. The voltage levels of the remaining nodes described above remain substantially unchanged. In an embodiment, the length of the touch sensing phase ST2 is, for example, 200 microseconds (μs) longer than other phases, but since the voltage level Q[N] is pulled low in this phase. It is possible to prevent the drive switch Td from being subjected to the bias stress for a long time in this stage. In an embodiment, the voltage level of each node in the touch sensing phase ST2 can be expressed as follows: Q[N]=VL G[N]=VL A[N]=VH-VTH_Tin1 B[N]=VL C[N]=VH-VTH_Tin1-VTH_T2

In the recharging phase ST3, the charging signal Cha is at a high voltage level, and the other signals shown in FIG. 3 are at a low voltage level VL. At this time, the first switch T1, the second switch T2, and the third switch T3 are turned on. Correspondingly, the voltage level Q[N] of the first node NQ is pulled high to the high voltage level VH such that the drive switch Td is turned on. In other words, although the voltage level Q[N] is pulled low in the touch sensing phase ST2, by the above-described timing operation, the first switch T1, the second switch T2, and the third switch T3 are The voltage level A[N] of the storage node NA again adjusts the voltage level Q[n] to a relatively high voltage level, and substantially returns to the state at the pull-up stage ST1.

From the viewpoint of circuit design, the charging ability of the second switch T2 and the third switch T3 to the first node NQ is designed to be similar to the charging capability of the first input switch Tin1 to the first node NQ. As described above, since the second switch T2 and the third switch T3 can be prevented from being affected by the bias stress for a long time and retain the original charging capability, the gate driving circuit 10_N is in the pull-up phase ST1 and the recharging phase ST3, respectively. The first node NQ can still pull the voltage level Q[N] to a similar voltage level through different charging paths, so that the gate driving circuit 10_N can output the same regardless of whether the touch sensing stage ST2 is experienced. Drive signal G[N]. In a defined manner, the third switch T3 can also be regarded as a charging switch, and the two ends thereof are respectively coupled to the second reference voltage end and the first node NQ, and when the third switch T3 is also the control end of the charging switch is coupled When the signal terminal is charged, the third switch T3 selectively turns on the first node NQ to the second reference voltage terminal according to the charging signal Cha. For details on how to output the drive signal G[N] according to the voltage level Q[N], please refer to the following description. In an embodiment, the voltage level of each node in the recharging phase ST3 can be expressed as follows: Q[N]=VH-VTH_T3 G[N]=VL A[N]=VH-VTH_Tin1+(VH-VL) B [N]=VH C[N]=VH where VTH_T3 is the turn-on voltage of the third switch T3.

In the driving phase ST4, the clock signal CK is adjusted to the high voltage level VH, and the other signals shown in FIG. 3 are the low voltage level VL. At this time, the first switch T1 and the second switch T2 are electrically connected to the drive switch Td. The voltage level of the first node NQ is pushed higher by the clock signal CK via the coupling path formed by the capacitor C2, thereby causing the driving switch Td to be stably turned on. Correspondingly, the driving signal G[N] is the high voltage level VH, and the voltage level and the waveform of the driving signal G[N] are close to when the display panel to which the gate driving circuit 10_N belongs is not in the touch sensing stage. Voltage level and waveform. In an embodiment, the voltage level of each node in the driving stage ST4 can be expressed as follows: Q[N]=VH-VTH_T2+(VH-VL) G[N]=VH A[N]=VH-VTH_Tin1 B[ N]=VL C[N]=VH-VTH_Tin1-VTH_T2

In the transition phase ST5, each signal is at a low voltage level VL. Correspondingly, the drive signal G[N] is a low voltage level VL. In an embodiment, the voltage level of each node in the transition phase ST5 can be expressed as follows: Q[N]=VH-VTH_T2 G[N]=VL A[N]=VH-VTH_Tin1 B[N]=VL C [N]=VH-VTH_Tin1-VTH_T2

In the pull-down phase ST6, the first pull-down signal XCK and the drive signal G[N+1] of the subsequent stage are at the high voltage level VH. At this time, the second input switch Tin2 and the fourth switch T4 are turned on such that the voltage level of the storage node NA is adjusted to the low voltage level VL. The pull-down switch Tpd1 is turned on so that the drive signal G[N] is stably maintained at the low voltage level VL. In an embodiment, the voltage level of each node in the pull-down phase ST6 can be expressed as follows: Q[N]=VL G[N]=VL A[N]=VL B[N]=VL C[N]= VH-VTH_Tin1-VTH_T2

In this embodiment, in addition to the above-mentioned effects, by the second switch T2 and the third switch T3 and the corresponding timing operation, the leakage current of the second reference voltage terminal to the first node NQ is also prevented, thereby avoiding The voltage level Q[N] is misaligned by the leakage of the second reference voltage terminal. In addition, the fourth switch T4 can be used to charge the storage node NA, and can also be used to regulate the storage node NA outside of the operation period, so that the number of components of the gate drive circuit 10_N is further reduced. See the subsequent description for details on voltage regulation. In this embodiment, most of the switching elements are only turned on once during one operation, which reduces the number of operations and alleviates the problem of aging of the respective switching elements.

In fact, as shown in FIG. 2, the gate driving circuit 10_N may further have a voltage stabilizing module 160. The voltage stabilizing module 160 has, for example, a capacitor C3 and voltage regulator switches TS1 and TS2. One end of the capacitor C3 is coupled to the clock signal end to receive the clock signal CK, and the other end of the capacitor C3 is coupled to one end of the voltage regulator switch TS1 and the control end of the voltage regulator switch TS2. The other end of the voltage regulator switch TS1 is coupled to the first reference voltage terminal to receive the first reference voltage VSS, and the control terminal of the voltage regulator switch TS1 is coupled to the first node NQ to receive the voltage level Q[N]. One end of the voltage regulator switch TS2 is coupled to the first node NQ, and the other end of the voltage regulator switch TS2 is coupled to the first reference voltage terminal to receive the first reference voltage VSS. The voltage regulator module 160 selectively turns on the first node NQ to the first reference voltage terminal according to the voltage level Q[N] and the voltage level of the clock signal CK. By the voltage regulator module 160, the gate driving circuit 10_N can keep the storage node NA and the output terminal NG corresponding to each other during operation, that is, when the gate driving circuits 10_1~10_N-1~... of other stages are activated. The voltage level, in order to avoid floating distortion caused by each node. The storage node NA is first selectively coupled to the first node NQ via the fourth switch T4, and further regulated by the voltage regulator module 160.

Please refer to FIG. 4 , which is a circuit diagram of another embodiment of one of the gate driving circuits according to FIG. 1 . In the embodiment shown in FIG. 4, the structure and operation of the gate driving circuit 10_N' are substantially similar to those of the gate driving circuit 10_N shown in FIG. 2, and details are not described herein again. Different from the embodiment corresponding to FIG. 2, in the embodiment shown in FIG. 4, the input module 120' has a plurality of first input switches and a plurality of second input switches, that is, the first input switch Tin1' , Tin3' and the second input switches Tin2', Tin4'. Further, the embodiment shown in FIG. 4 does not have the fourth switch T4 but has the fifth switch T5.

The coupling relationship between the first input switch Tin1' and the second input switch Tin2' with respect to other components is similar to the first input switch Tin1 and the second input switch Tin2 in FIG. 2, and details are not described herein again. The two ends of the first input switch Tin3' are respectively coupled to the storage node NA and the first input voltage U2D, and the control end of the first input switch Tin3' receives the driving signal G[N-1] of the previous stage. The two ends of the second input switch Tin4' are respectively coupled to the storage node NA and the second input voltage D2U, and the control end of the second input switch Tin4' receives the driving signal G[N+1] of the subsequent stage. The two ends of the fifth switch T5 are respectively coupled to the storage node NA and the first reference voltage end, and the control end of the fifth switch T5 is coupled to the second pull-down signal P[N].

In this embodiment, the input module 120' is configured to use the driving signal G[N-1] of the previous stage, the driving signal G[N+1] of the subsequent stage, the first input voltage U2D, and the second input voltage D2U. The input signal Sin' is supplied to the first node NQ, and the input signal Sin" is supplied to the storage node NA, thereby selectively adjusting the voltage level Q[N] and the voltage level A[N]. The input signal Sin" has The input signal Sin' is similar to the voltage level, so in the embodiment shown in FIG. 4, the voltage level Q[N] and the voltage level A[N] are also adjusted to a similar voltage in the pull-up phase ST1. Level. The subsequent relevant details are as described above and will not be described here.

In this embodiment, the second pull-down signal P[N] is the voltage level of a node in the voltage regulator module 160. However, as described above, the second pull-down signal P[N] may also be an external signal. In this embodiment, when the gate driving circuit 10_N is operated during operation, that is, when the gate driving circuits 10_1~10_N-1~... of other stages are activated, the storage node NA can be coupled via the fifth switch T5. To the first reference voltage terminal, the voltage level A[N] is kept at the low voltage level VL, and the storage node NA is prevented from floating to affect the voltage level of the driving signal G[N]. On the other hand, in this embodiment, each of the switching elements is turned on only once during one operation, which reduces the number of operations, and also alleviates the problem of aging of the respective switching elements.

In summary, the present invention provides a gate driving circuit for pre-existing a data voltage in a storage node, thereby enabling leakage in the touch sensing phase in addition to suspending the operation of the gate driving circuit. The voltage of at least one node is removed to prevent the component from being deteriorated by the long-term bias stress, thereby maintaining the charging capability of each switch. On the other hand, after the end of the touch sensing phase, the corresponding switch is driven by the voltage stored by the storage node to recharge the corresponding node to generate a drive signal that is consistent with the expectation. Therefore, the gate driving circuit and the touch circuit can be prevented from affecting each other as much as possible while integrating the touch function on the display panel, and at the same time, the components in the gate driving circuit can be prevented from being subjected to long-term bias stress. The effect is rapidly degraded.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1‧‧ ‧ gate driver

10_1~10_N..., 10_N’‧‧‧ gate drive circuit

120, 120'‧‧‧ input module

140‧‧‧Drawdown Module

160‧‧‧voltage regulator

C1, C2, C3‧‧‧ capacitors

CK‧‧‧ clock signal

Cha‧‧‧Charging signal

D2U‧‧‧ second input signal

U2D‧‧‧ first input signal

G[1], G[2], G[3]~ G[N-1], G[N], G[N+1]...‧‧‧ drive signals

NA‧‧‧ storage node

NB‧‧‧second node

NC‧‧‧ third node

NG‧‧‧ output

NQ‧‧‧ first node

P[N]‧‧‧Second pulldown signal

Q[N]‧‧‧voltage level

ST[1]‧‧‧ start signal

ST1‧‧‧ Pull-up stage

ST2‧‧‧ touch sensing stage

ST3‧‧‧Recharge phase

ST4‧‧‧Driver phase

ST5‧‧‧ transitional phase

ST6‧‧‧ pulldown stage

Sin, Sin’, Sin”‧‧‧ input signal

Srst‧‧‧Reset signal

T1‧‧‧ first switch

T2‧‧‧ second switch

T3‧‧‧ third switch

T4‧‧‧fourth switch

T5‧‧‧ fifth switch

Td‧‧‧ drive switch

Tin1, Tin1’, Tin3’‧‧‧ first input switch

Tin2, Tin2’, Tin4’‧‧‧ second input switch

Tpd1, Tpd2‧‧‧ pull-down switch

Trst‧‧‧Reset switch

Ts1, Ts2‧‧‧ voltage switch

VDD‧‧‧second reference voltage level

VSS‧‧‧first reference voltage level

XCK‧‧‧ first pulldown signal

FIG. 1 is a functional block diagram of a gate driver according to an embodiment of the invention. FIG. 2 is a circuit diagram showing an embodiment of one of the gate driving circuits according to FIG. FIG. 3 is a timing diagram of the gate driving circuit according to FIG. 2 . FIG. 4 is a circuit diagram showing another embodiment of one of the gate driving circuits according to FIG.

10_N‧‧‧ gate drive circuit

120‧‧‧Input module

140‧‧‧Drawdown Module

160‧‧‧voltage regulator

C1, C2, C3‧‧‧ capacitors

CK‧‧‧ clock signal

Cha‧‧‧Charging signal

D2U‧‧‧ first input voltage

U2D‧‧‧second input voltage

G[N-1], G[N], G[N+1]...‧‧‧ drive signals

NA‧‧‧ storage node

NB‧‧‧second node

NC‧‧‧ third node

NG‧‧‧ output

NQ‧‧‧ first node

P[N]‧‧‧Second pulldown signal

Q[N]‧‧‧voltage level

Sin‧‧‧ input signal

Srst‧‧‧Reset signal

T1‧‧‧ first switch

T2‧‧‧ second switch

T3‧‧‧ third switch

T4‧‧‧fourth switch

Td‧‧‧ drive switch

Tin1‧‧‧first input switch

Tin2‧‧‧Second input switch

Tpd1, Tpd2‧‧‧ pull-down switch

Trst‧‧‧Reset switch

Ts1, Ts2‧‧‧ voltage switch

VDD‧‧‧second reference voltage level

VSS‧‧‧first reference voltage level

XCK‧‧‧ first pulldown signal

Claims (9)

A gate driving circuit includes: a driving switch, selectively adjusting a voltage level of a driving signal to a voltage level of a clock signal according to a voltage level of a first node, and the first node is fed into a An input signal coupled to the first node for selectively adjusting a voltage level of the input signal according to the driving signal of the previous stage or the driving signal of the subsequent stage; a pull-down module coupled One end of the driving switch is configured to selectively couple the driving switch to a first reference voltage terminal according to a first pull-down signal or a second pull-down signal to adjust a voltage level of the driving signal; a switch, one end of the first switch is coupled to a charging signal end, and the other end is coupled to a second node, the control end is coupled to a storage node, the storage node is fed to the input signal; a second switch, the first One end of the second switch is coupled to a second reference voltage end, the other end is coupled to a third node, and the control end is coupled to the storage node; a third switch, one end of the third switch is coupled to the third node, and the other end is Coupled with a first node, the control end is coupled to the second node; a capacitor, the two ends of the capacitor are respectively coupled to the storage node and the second node; and a reset switch, one end of the reset switch is coupled to the first The other end of the node is coupled to the first reference voltage end, and the control end is coupled to a reset signal end. The gate driving circuit of claim 1, further comprising a fourth switch, one end of the fourth switch is coupled to the storage node, and the other end is coupled to the first node, and the fourth switch is configured according to the first pulldown A signal selectively couples the storage node to the first node. The gate driving circuit of claim 2, wherein the input module comprises: a first input switch, one end coupled to the first node, and selectively selecting the voltage of the first node according to the driving signal of the previous stage The level is adjusted to a first input voltage; and a second input switch is coupled to the first node at one end, and selectively adjusts the voltage level of the first node to a second input according to the driving signal of the subsequent stage. Voltage. The gate driving circuit of claim 1, wherein the input module comprises: a plurality of first input switches, wherein one end of the first input switch is coupled to the first node, and according to the driving signal of the previous stage Selectively adjusting the voltage level of the first node to a first input voltage, wherein one end of the other first input switch is coupled to the storage node, and selectively storing the memory according to the driving signal of the previous stage. Adjusting a voltage level of the node to the first input voltage; and a plurality of second input switches, wherein one end of the second input switch is coupled to the first node, and selectively, according to the driving signal of the subsequent stage The voltage level of the first node is adjusted to a second input voltage level, wherein one end of the other second input switch is coupled to the storage node, and selectively selects the voltage of the storage node according to the driving signal of the subsequent stage. The level is adjusted to the second input voltage. The gate driving circuit of claim 4, further comprising a fifth switch, the fifth switch having one end coupled to the storage node and the other end coupled to the first reference voltage end, the fifth switch being according to the second A pull down signal selectively turns the storage node to the first reference voltage terminal. The gate driving circuit of claim 1, wherein the first pull-down signal is the reverse clock signal. The gate driving circuit of claim 1, further comprising a voltage stabilizing module coupled to the first node, and the voltage regulator module is based on the voltage level of the first node and the time The voltage level of the pulse signal selectively turns the first node to the first reference voltage terminal. A gate driving circuit includes: a driving switch that selectively adjusts a voltage level of a driving signal by a voltage level of a first node, the driving signal being provided to an output terminal, the first node Is input to an input signal; an input module coupled to the first node for selectively adjusting a voltage level of the input signal according to the driving signal of the previous stage or the driving signal of the subsequent stage; a switch, the two ends are respectively coupled to the first node and a first reference voltage end, the control end of the reset switch is coupled to a reset signal end; a temporary storage module coupled to the first node, a charging signal And the second reference voltage end, the temporary storage module has a storage node; wherein, before a touch sensing phase, the input signal is fed to the storage node and the first node, and the touch In the sensing phase, the voltage level of the reset signal terminal is a high voltage level, the first node is turned on to the first reference voltage terminal, and the storage node temporarily stores the voltage level of the input signal, a charge level after the sensing phase The voltage level of the charging signal terminal is a high voltage level, and the voltage level of the reset signal terminal is a low voltage level, and the temporary storage module increases the voltage of the first node according to the voltage level of the storage node. Level. The gate driving circuit of claim 8, wherein the temporary storage module comprises a charging switch, and the two ends of the charging switch are respectively coupled to the second reference voltage terminal and the first node, in the recharging phase The temporary storage module conducts the control end of the charging switch to the charging signal end according to the voltage level of the storage node and the voltage level of the charging signal end, to conduct the first node to the second reference voltage end. .