TWI574415B - Semiconductor device and method of manufacturing the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor process, and more particularly to a semiconductor device having an air gap and a method of fabricating the same.

With the development of semiconductor components to the generation of nanometers, there are more and more difficulties, such as the line width reduction, line density increase, etc., in the pattern accuracy and process control have a severe test.

For example, when the process enters the 35 nm generation, not only is the line width reduced, but the distance between the lines is also reduced. In particular, when the aspect ratio of the trenches between the lines is too high, there is often a problem that the trench filling is not easy. In addition, if it is to be combined with a metal deuteration process, the problem of uneven height of the dielectric layer in the trench will be found. This is estimated to be difficult due to trench filling, so some holes in the dielectric layer in the trench are generated, which leads to etch back. After the dielectric layer, a hole is formed in the portion where the hole is formed. In addition, since the line width becomes small, the problem of line bending may occur due to stress during the trench filling process of the dielectric layer.

The present invention provides a semiconductor device having an air gap capable of avoiding the occurrence of a coupling effect between gates.

The present invention further provides a method of fabricating a semiconductor device capable of completing trench filling by reducing the aspect ratio of the trench and simultaneously forming an air gap.

A semiconductor component of the present invention includes a substrate, a plurality of stacked structures, a dielectric layer, and a plurality of dielectric spacers. The substrate has the above stacked structure, and the dielectric layer is located between the stacked structures, wherein there is an air gap between the two stacked structures. The dielectric spacer is between the sidewall of the stacked structure above the air gap and the dielectric layer.

In an embodiment of the invention, the aspect ratio of the trenches between the stacked structures is, for example, greater than 11.

In an embodiment of the invention, the aspect ratio of the trench between the dielectric spacers is, for example, between 7 and 11.

In an embodiment of the invention, the dielectric layer is a tensile oxide and the dielectric spacer is a compressed oxide.

In an embodiment of the invention, the dielectric layer is a compressed oxide and the dielectric spacer is a tensile oxide.

In an embodiment of the invention, the material of the dielectric spacer includes a low temperature oxide.

In an embodiment of the invention, each of the stacked structures includes a floating gate, a gate dielectric layer on the floating gate, a word line on the dielectric layer of the gate, And the top cover layer on the word line.

In an embodiment of the invention, the inter-gate dielectric layer is below the dielectric spacer.

In an embodiment of the invention, the inter-gate dielectric layer is flush with the bottom of the dielectric spacer.

A method of fabricating a semiconductor device of the present invention includes providing a substrate having a plurality of stacked structures, and coating a fluid material between the stacked structures, and then removing a portion of the fluid material to form a sacrificial layer exposing a portion of the stacked structure. Forming a plurality of dielectric spacers on sidewalls of the exposed stacked structure, completely removing the sacrificial layer, and forming a dielectric layer covering the stacked structure on the substrate, and having between the two stacked structures below the dielectric spacer Air gap.

In another embodiment of the invention, the step of forming the dielectric spacers includes conformally forming a layer of low temperature oxide on the exposed stacked structure and etching back the low temperature oxide layer until the sacrificial layer is exposed.

In another embodiment of the present invention, each of the stacked structures includes a floating gate, a gate dielectric layer formed on the floating gate, a word line formed on the dielectric layer of the gate, and is formed on The top layer on the word line.

In another embodiment of the invention, the thickness of the sacrificial layer is controlled such that the top surface of the sacrificial layer is above the location of the inter-gate dielectric layer.

Based on the above, the present invention reduces the aspect ratio of the trench by first forming a sacrificial layer at the bottom of the trench, so that the trench filling step of the dielectric layer can be successfully completed. In addition, the present invention can also utilize different oxide layers (with tensile stress and compressive stress, respectively). Make sure that the wires (that is, the stack structure) are not bent. Moreover, since the dielectric layer naturally forms an air gap at the bottom between the stacked structures after the trench filling, when the bottom of the stacked structure is a floating gate, the problem of coupling between the floating gates can be greatly improved.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Base

102‧‧‧ gate insulation

104‧‧‧Stack structure

106‧‧‧Floating gate

108‧‧‧Interruptor dielectric layer

110‧‧‧ character line

112‧‧‧Top cover

114‧‧‧ lining

116‧‧‧ Sacrifice layer

118‧‧‧Low temperature oxide layer

118a, 118b‧‧‧ dielectric gap

120, 120a‧‧‧ dielectric layer

122‧‧‧Air gap

200‧‧‧ metal layer

202‧‧‧metal telluride layer

D‧‧‧Deep

H1, H2‧‧‧ height

T‧‧‧ thickness

W1, W2‧‧‧ width

1A to 1F are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention.

2A to 2C are schematic cross-sectional views showing the application of the semiconductor device of FIG. 1F to a metal deuteration process.

1A to 1F are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, first, a film such as a gate insulating layer 102 is generally formed on the surface of the substrate 100, and then a stacked structure 104 is formed on the substrate 100, wherein the aspect ratio of the trench between the stacked structures 104 (height H1 and The ratio of the width W1 is, for example, greater than 11. When the aspect ratio of the trench between the stacked structures 104 is greater than 11, the current technology of the present invention will be difficult to face the problem of trench filling, and if the stacked structure 104 is a conductor line, it may be subjected to force bending in subsequent processes. .

In this embodiment, each stacked structure 104 has, for example, a floating gate 106, an inter-gate dielectric layer 108 formed on the floating gate 106, a word line 110 formed on the inter-gate dielectric layer 108, And a cap layer 112 formed on the word line 110. However, the present invention is not limited thereto, and the stacked structure 104 may be composed of other members. In addition, the surface of the conductor material (106 and 110) of the stacked structure 104 may also form a liner 114 such as an oxide layer. The floating gate 106 is, for example, a polysilicon, an inter-gate dielectric layer 108 such as an ONO layer, a word line 110 such as a polysilicon, and a cap layer 112 such as an oxide or a nitride.

Then, referring to FIG. 1B, a fluid material (not shown) is coated between the stacked structures 104, such as spin-on carbon (SOC) or photoresist (PR), so that the aspect ratio electrode can be easily filled. Between high stack structures 104. Since the SOC or photoresist exerts little stress on the stacked structure 104, the stacked structure 104 is not bent. Then, a portion of the fluid material is removed to form a sacrificial layer 116 that exposes a portion of the stacked structure 104, wherein the thickness T of the sacrificial layer 116 can be controlled at a particular location, such as the top surface of the sacrificial layer 116 at the location of the inter-gate dielectric layer 108. Above, this will facilitate controlling the position of the subsequently formed air gap. The aforementioned method of removing a portion of the fluid material is, for example, using oxygen (O ₂ ) plasma or burning at a high temperature. The process of removing a portion of the fluid material does not cause damage to the stack structure 104 itself.

Next, referring to FIG. 1C, a low-temperature oxide layer 118 is conformally formed on the exposed stacked structure 104, for example, a film having a thickness of about several tens of nanometers to several nanometers is formed by using a low-temperature oxidation process at a temperature of 200 ° C or lower. .

Then, referring to FIG. 1D, the low temperature oxide layer 118 is etched back until the sacrificial layer 116 is exposed, and a plurality of dielectric layers are formed on the sidewalls of the exposed stacked structure 104. Gap wall 118a. The material of the dielectric spacers 118a is, for example, a low temperature oxide. In the present embodiment, the inter-gate dielectric layer 108 is located below the dielectric spacers 118a, but the invention is not limited thereto. In another embodiment, the inter-gate dielectric layer 108 and the bottom of the dielectric spacers 118a may also be in the same plane.

Subsequently, referring to FIG. 1E, the sacrificial layer 116 of FIG. 1D is completely removed, wherein the method of completely removing the sacrificial layer 116 includes ashing or cleaning. At this time, the aspect ratio (ratio of the height H2 to the width W2) of the trench between the dielectric spacers 118a has been lowered to between 7 and 11, or even less than 7.

Next, referring to FIG. 1F, a dielectric layer 120 covering the stacked structure 104 is formed on the substrate 100, and an air gap 122 is naturally formed between the two stacked structures 104 below the dielectric spacers 118a. Since the aspect ratio of the trench has been reduced to a level suitable for trench filling when the dielectric layer 120 is deposited between the stacked structures 104, the dielectric layer 120 can be completely filled between the dielectric spacers 118a, and An air gap 122 is formed in a space below the dielectric spacer 118a. In addition, when the dielectric layer 120 in the embodiment is a tensile oxide and the dielectric spacers 118a are compressed oxides; or, the dielectric layer 120 is a compressed oxide and the dielectric spacers 118a are stretched and oxidized. The object can also protect the stack structure 104, reducing the occurrence of bending due to force during the process.

The process of the above embodiment can be applied to various semiconductor processes that may or may not encounter trench filling. For example, FIG. 2A to FIG. 2C are schematic cross-sectional views of the semiconductor device of FIG. 1F applied to the metal deuteration process, wherein The same component symbols as in the previous embodiment are used to denote the same or similar components.

Referring to FIG. 2A, the dielectric layer 120 is removed first until the cap layer 112 is exposed. Next, the cap layer 112, the portion of the liner 114 and a portion of the dielectric spacers 118a are removed, and the polysilicon germanium word lines 110 are exposed, wherein the depth D from the word lines 110 to the remaining dielectric layers 120a can be controlled at the gates. Above the dielectric layer 108.

Next, referring to FIG. 2B, a metal layer 200 is formed on the surface of the substrate 100 to cover the exposed word line 110, dielectric layer 120a, and dielectric spacers 118b. The metal layer 200 is, for example, cobalt.

Finally, referring to FIG. 2C, the metal layer 200 of FIG. 2B is reacted with the polysilicon germanium word line 110 to form a metal germanide layer 202. Thereafter, the unreacted metal layer (200) must be completely removed. In FIG. 2C, not only can the metal deuteration process be successfully completed (for example, the word lines are not bent during the process), but also an air gap 122 can be formed between the floating gates 106 to solve the floating gate coupling problem.

In summary, the present invention can not only improve the problem of coupling between floating gates by air gap, but also reduce the aspect ratio of the trench to perform the trench filling step of the dielectric layer to make the position above the sacrificial layer. The dielectric layer formed inside has no holes. In addition, the present invention also gives the tensile and compressive forces of the stacked structure by the dielectric spacer formed on the sidewall of the stacked structure and the dielectric layer subsequently deposited between the stacked structures, so that the stacked structure can be prevented from occurring during the process. Bend.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

102‧‧‧ gate insulation

104‧‧‧Stack structure

106‧‧‧Floating gate

108‧‧‧Interruptor dielectric layer

110‧‧‧ character line

112‧‧‧Top cover

118a‧‧‧ dielectric spacer

120‧‧‧ dielectric layer

122‧‧‧Air gap

Claims (12)

A semiconductor device comprising: a substrate having a plurality of stacked structures; a dielectric layer between the stacked structures, wherein two air gaps between the stacked structures; and a plurality of dielectric spacers, Located between the sidewalls of the stacked structures above the air gap and the dielectric layer; wherein the trenches between the dielectric spacers have an aspect ratio of between 7 and 11. The semiconductor device of claim 1, wherein the trench between the stacked structures has an aspect ratio greater than 11. The semiconductor device of claim 1, wherein the dielectric layer is a tensile oxide and the dielectric spacer is a compressed oxide. The semiconductor device of claim 1, wherein the dielectric layer is a compressed oxide and the dielectric spacer is a tensile oxide. The semiconductor device of claim 1, wherein the material of the dielectric spacer comprises a low temperature oxide. The semiconductor device of claim 1, wherein each of the stacked structures comprises a floating gate, an inter-gate dielectric layer on the floating gate, a word line on the dielectric layer of the gate, And a cap layer on the word line. The semiconductor device of claim 6, wherein the inter-gate dielectric layer is below the dielectric spacers. The semiconductor device according to claim 6, wherein the gate device The electrical layer is coplanar with the bottom of the dielectric spacers. A method of fabricating a semiconductor device, comprising: providing a substrate having a plurality of stacked structures; coating a fluid material between the stacked structures; removing a portion of the fluid material to form a sacrifice of exposing portions of the stacked structures a plurality of dielectric spacers are formed on sidewalls of the exposed stacked structures; the sacrificial layer is completely removed; and a dielectric layer covering the stacked structures is formed on the substrate and below the dielectric spacers There is an air gap between the two stacked structures. The method of fabricating a semiconductor device according to claim 9, wherein the forming the dielectric spacers comprises: conformally forming a low temperature oxide layer on the exposed stacked structures; and etching back the low temperature The oxide layer is exposed until the sacrificial layer is exposed. The method of fabricating a semiconductor device according to claim 9, wherein each of the stacked structures includes a floating gate, a gate dielectric layer formed on the floating gate, and is formed on the gate dielectric layer. The word line and the cap layer formed on the word line. The method of fabricating a semiconductor device according to claim 11, wherein the thickness of the sacrificial layer is controlled such that a top surface of the sacrificial layer is above a position of the inter-gate dielectric layer.