TWI572075B - Memory device and method for fabricating the same - Google Patents

Description

Memory element and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a memory device and a method of fabricating the same.

As technology advances, advances in electronic components have increased the need for greater storage capacity. In order to increase storage capacity, memory elements become smaller and more cumulative. Therefore, three-dimensional memory components have gradually received high attention from the industry.

However, as the degree of integration of three-dimensional memory elements increases, surface forces (such as capillary forces, friction, and adhesion) will seriously affect the stability of the three-dimensional memory element structure due to the high surface area to volume ratio. Sex. Especially for the extremely high aspect ratio component structure. Therefore, how to develop a memory element and its manufacturing method to avoid bending or collapse of the high-aspect ratio component structure will become an important issue in the future.

The present invention provides a memory element having a cap layer and a method of manufacturing the same, which can avoid a phenomenon in which a high aspect ratio element structure is bent or collapsed.

The invention provides a memory element comprising a stacked structure, a plurality of first cover layers and a plurality of second cover layers. The stacked structure is on the substrate. The stacked structure includes a plurality of first conductor layers and a plurality of dielectric layers stacked alternately with each other. The first cap layers are respectively located on the sidewalls of the first conductor layer. The second cap layers are respectively located on the sidewalls of the dielectric layer.

In an embodiment of the invention, the material of the first cap layer is the same as the material of the second cap layer.

In an embodiment of the invention, the material of the first cover layer is different from the material of the second cover layer.

In an embodiment of the invention, the material of the first cap layer and the material of the second cap layer comprise a nitrogen-containing material.

In an embodiment of the invention, the nitrogen-containing material comprises tantalum nitride, niobium oxynitride or a combination thereof.

In an embodiment of the invention, the memory element further includes a second conductor layer and a charge storage layer. The second conductor layer covers the stacked structure. The charge storage layer is between the stacked structure and the second conductor layer. The first cap layer is located between the first conductor layer and the charge storage layer, respectively. The second cap layer is located between the dielectric layer and the charge storage layer, respectively.

In an embodiment of the invention, the material of the first cap layer is the same as the material of the charge storage layer. The material of the second cap layer is different from the material of the charge storage layer.

In an embodiment of the invention, one of the first conductor layer and the second conductor layer is a plurality of gate layers. The other of the first conductor layer and the second conductor layer is a plurality of channel layers.

The present invention provides a memory element comprising a stacked structure, a second conductor layer, and a charge storage structure. The stacked structure is on the substrate. The stacked structure includes a plurality of first conductor layers and a plurality of dielectric layers stacked alternately with each other. The second conductor layer covers the stacked structure. A charge storage structure is between the stacked structure and the second conductor layer. The charge storage structure includes a plurality of first portions and a plurality of second portions. The first portion is located on the sidewall of the first conductor layer. The second portion is located on the sidewall of the dielectric layer. The structure of the first portion is at least partially different from the structure of the second portions.

In an embodiment of the invention, the first portion includes tantalum nitride/yttria/yttria/yttria.

In an embodiment of the invention, the second portion comprises bismuth oxynitride / cerium oxide / cerium nitride / cerium oxide.

The present invention provides a method of manufacturing a memory element, the steps of which are as follows. A stacked structure is formed on the substrate. The stacked structure includes a plurality of first conductor layers and a plurality of dielectric layers. The first conductor layer and the dielectric layer are alternately stacked one upon another. A plurality of first cap layers are respectively formed on sidewalls of the first conductor layer, and second cap layers are respectively formed on sidewalls of the dielectric layer.

In an embodiment of the invention, the first cap layer is respectively formed on the sidewall of the first conductor layer, and the method of forming the second cap layer on the sidewall of the dielectric layer respectively comprises performing a surface treatment process.

In an embodiment of the invention, the surface treatment process includes a nitridation treatment, an oxynitridation treatment, or a combination thereof.

In an embodiment of the invention, the nitriding treatment includes a plasma treatment, a chemical vapor deposition treatment, a physical vapor deposition treatment, or a combination thereof.

In an embodiment of the invention, the material of the first cover layer is different from the material of the second cover layer.

In an embodiment of the invention, the material of the first cap layer and the material of the second cap layer comprise a nitrogen-containing material.

In an embodiment of the invention, the nitrogen-containing material comprises tantalum nitride, niobium oxynitride or a combination thereof.

In an embodiment of the invention, the method of manufacturing the memory element further includes the following steps. A second conductor layer is formed on the surface of the stacked structure, the first cap layer, and the second cap layer. The second conductor layer covers the stacked structure. A charge storage layer is formed between the stacked structure and the second conductor layer.

In an embodiment of the invention, one of the first conductor layer and the second conductor layer is a plurality of gate layers. The other of the first conductor layer and the second conductor layer is a plurality of channel layers.

Based on the above, the present invention utilizes a first cap layer and a second cap layer overlying the first conductor layer and the sidewalls of the dielectric layer, respectively. Since the material of the first cap layer and the second cap layer is a nitrogen-containing material having a relatively large hardness, the first cap layer and the second cap layer can improve the hardness of the entire stack structure of the present invention to avoid a high aspect ratio. The stacking structure is bent or collapsed.

The above described features and advantages of the invention will be apparent from the following description.

1A-1F are schematic cross-sectional views showing a manufacturing process of a memory device according to an embodiment of the invention.

Referring to FIG. 1A, first, a substrate 100 is provided. The substrate 100 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide.

Then, a stacked layer 102 is formed on the substrate 100. The stacked layer 102 includes a plurality of conductor layers 104 and a plurality of dielectric layers 106. The conductor layer 104 and the dielectric layer 106 are alternately stacked. In an embodiment, the material of the conductor layer 104 may be, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition. The thickness of the conductor layer 104 may be, for example, 100 nm to 500 nm. The material of the dielectric layer 106 may be, for example, hafnium oxide, tantalum nitride or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition. The thickness of the dielectric layer 106 can be, for example, from 100 nm to 500 nm. Although FIG. 1A only shows the 12-layer conductor layer 104 and the 12-layer dielectric layer 106, the invention is not limited thereto. In other embodiments, the number of the conductor layers 104 may be, for example, 8 layers or 16 layers. , 32 or more layers. Similarly, the dielectric layer 106 is disposed between two adjacent conductor layers 104. Therefore, the dielectric layer 106 can also be, for example, 8 layers, 16 layers, 32 layers, or more.

Next, referring to FIG. 1A and FIG. 1B, a mask layer 108 and a patterned mask layer 110 are sequentially formed on the stacked layer 102. In an embodiment, the mask layer 108 can be, for example, an Advanced Patterning Film (APF). The material of the advanced patterned film (APF) includes a carbonaceous material, and the carbonaceous material may be, for example, amorphous carbon. The material of the patterned mask layer 110 can be, for example, a positive photoresist material or a negative photoresist material. The patterned mask layer 110 can be formed by a lithography process.

Referring to FIG. 1B and FIG. 1C, with the patterned mask layer 110 as a mask, the mask layer 108 is first etched to remove a portion of the mask layer 108 to form a patterned mask layer 108a. Thereafter, the patterned layer 102a is used as a mask, and the stacked layer 102 is etched to remove a portion of the conductor layer 104 and a portion of the dielectric layer 106 to form a plurality of openings 10 and a plurality of stacked structures 102a. In an embodiment, the opening 10 exposes the surface of the substrate 100. The stacked structure 102a extends in a first direction D1 (ie, perpendicular to the plane of the paper), and the stacked structure 102a and the opening 10 also alternate with each other along the second direction D2. In an embodiment, the first direction D1 is different from the second direction D2 and is perpendicular to each other. When the etching process described above is performed, the patterned mask layer 110 is consumed, so that the patterned mask layer 108a remains on the stacked structure 102a (as shown in FIG. 1C). In the present embodiment, the aspect ratio (H1/W1) of the stacked structure 102a may be between 10 and 50. The width W2 of the opening 10 can be less than 150 nm.

Referring to FIG. 1D, a surface treatment process 112 is performed to form a first cap layer 114 or a second cap layer 116 on the sidewalls of the conductor layer 104a in the opening 10, respectively. In one embodiment, the second cap layer 116 or the first cap layer 114 may be formed simultaneously and separately on the sidewalls of the dielectric layer 106a in the opening 10 when the surface treatment process 112 is performed. In addition, in another embodiment, when the surface treatment process 112 is performed, the third cap layer 117 may be simultaneously and separately formed on the surface of the substrate 100 at the bottom of the opening 10. Surface treatment process 112 includes a nitridation process, an oxynitride process, or a combination thereof. The nitridation treatment may be, for example, a plasma treatment, a chemical vapor deposition treatment, a physical vapor deposition treatment, or a combination thereof. In one embodiment, the surface treatment process 112 is a N ₂ plasma treatment, which can be introduced in a high-Vaccum Chamber at a reaction chamber temperature of 20 ° C to 70 ° C. A plasma containing nitrogen gas having a flow rate of 10 sccm to 500 sccm was subjected to plasma treatment. In the present embodiment, the nitrogen-containing gas may be, for example, nitrogen (N ₂ ), NH ₃ or a combination thereof. However, the present invention is not limited thereto as long as the surface treatment process does not substantially remove or remove only a small number of stacked structures 102a, and a cap layer is formed on the sidewalls of the stacked structure 102a. In an embodiment, the materials of the first cap layer 114, the second cap layer 116, and the third cap layer 117 may be the same or different. The material of the first cap layer 114, the second cap layer 116, and the third cap layer 117 includes a nitrogen-containing material, and the nitrogen-containing material may be, for example, tantalum nitride, hafnium oxynitride, or a combination thereof. In one embodiment, the conductor layer 104a is polysilicon; the dielectric layer 106a is tantalum oxide; the first cap layer 114 is tantalum nitride; the second cap layer 116 is tantalum oxynitride; and the third cap layer 117 is tantalum nitride. The thickness of the first cap layer 114 may be, for example, 1 nm to 5 nm. The thickness of the second cap layer 116 may be, for example, 1 nm to 5 nm. The thickness of the third cap layer 117 may be, for example, 1 nm to 5 nm.

Referring to FIG. 1D and FIG. 1E, the patterned mask layer 108a is removed. Thereafter, a charge storage layer 118 is formed on the stacked structure 102a, the first cap layer 114, the second cap layer 116, and the third cap layer 117. In an embodiment, the charge storage layer 118 is conformally formed along the surface of the stacked structure 102a, the first cap layer 114, the second cap layer 116, and the surface of the third cap layer 117. In one embodiment, the charge storage layer 118 can be, for example, a composite layer composed of an oxide layer/nitride layer/oxide layer (Oxide/Nitride/Oxide, ONO), and the composite layer can be three or more layers. The present invention is not limited thereto, and the formation method thereof may be, for example, a chemical vapor deposition method.

It is worth mentioning that, before removing the patterned mask layer 108a, the first cap layer 114 and the second cap layer 116 are separately formed on the sidewalls of the first conductor layer 104a and the dielectric layer 106a, respectively. The first cap layer 114 and the second cap layer 116 may strengthen the strength of the overall stack structure 102a. As such, when the patterned mask layer 108a is removed, it can reduce the influence of surface forces (eg, capillary force, friction, and adhesion) in the removal step on the stacked structure 102a to maintain the stacked structure 102a. Stability.

Then, referring to FIG. 1E and FIG. 1F, a conductor layer 120 is formed on the charge storage layer 118. In an embodiment, the conductor layer 120 is conformally formed on the charge storage layer 118. However, the present invention is not limited thereto. In other embodiments, the conductor layer 120 may also fill the opening 10. The material of the conductor layer 120 may be, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof may utilize a chemical vapor deposition method. The thickness of the conductor layer 120 may be, for example, 10 nm to 20 nm. Subsequent processes may include the steps of further patterning the conductor layer 120, and will not be described in detail herein.

Referring to FIG. 1F, the present invention provides a memory device including a plurality of stacked structures 102a, a charge storage layer 118, a conductor layer 120, a first cap layer 114, and a second cap layer 116. The stacked structure 102a is located on the substrate 100. The stacked structure 102a includes a plurality of conductor layers 104a and a plurality of dielectric layers 106a. The conductor layer 104a and the dielectric layer 106a are alternately stacked with each other. In an embodiment, the conductor layer 104a may be, for example, a gate layer (also referred to as a word line); the conductor layer 120 may be, for example, a channel layer (also referred to as a bit line). However, the present invention is not limited thereto. In other embodiments, the conductor layer 104a may also be, for example, a channel layer (also referred to as a bit line); the conductor layer 120 may be, for example, a gate layer (also referred to as a word element) line). The first cap layer 114 is on the sidewall of the conductor layer 104a. The second cap layer 116 is on the sidewall of the dielectric layer 106a. The charge storage layer 118 is on the surface of the stacked structure 102a, the first cap layer 114, and the second cap layer 116. The second conductor layer 120 is located on the charge storage layer 118. In an embodiment, the first cap layer 114 and a portion of the charge storage layer 118 overlying the first cap layer 114 can be considered as the first portion P1. The second cap layer 116 and a portion of the charge storage layer 118 overlying the second cap layer 116 can be considered as the second portion P2. The structure of the first portion P1 and the second portion P2 are at least partially different. In an embodiment, the structure of the first portion P1 may be, for example, composed of tantalum nitride 114 / tantalum oxide 118a / tantalum nitride 118b / tantalum oxide 118c (from the surface of the stacked structure 102a to the direction of extension of the charge storage layer 118) The structure of the second portion may be composed, for example, of yttrium oxynitride 116 / yttrium oxide 118a / tantalum nitride 118b / yttrium oxide 118c, but the invention is not limited thereto. The material of the first cap layer 114 and the second cap layer 116 has a relatively large hardness with respect to the dielectric layer 106a (its Young's modulus may be, for example, between 220 GPa and 270 GPa). Therefore, the first cover layer 114 and the second cover layer 116 can improve the hardness of the entire stack structure 102a of the embodiment to reduce the influence of surface forces (such as capillary force, friction and adhesion), thereby avoiding high and high width. The stacked structure is curved or collapsed.

Further, when the conductor layer 104a is a word line and the conductor layer 120 is a bit line. In the Erase operation, since the first cap layer 114 on the surface of the conductor layer 104a has a certain thickness, it can prevent gate injection of electrons into the charge storage layer 118, thereby elevating the erase operation. The margin on the window.

In summary, the present invention utilizes the first cap layer and the second cap layer to cover the first conductor layer and the sidewall of the dielectric layer, respectively. Since the materials of the first cover layer and the second cover layer have a large hardness (for example, a nitrogen-containing material), the first cover layer and the second cover layer can improve the hardness of the entire stack structure of the present invention to reduce the surface. The effects of forces, such as capillary forces, friction, and adhesion, prevent the high aspect ratio stack from bending or collapsing. In addition, the first cap layer on the surface of the conductor layer can also prevent the gate from injecting electrons into the charge storage layer, thereby increasing the margin of the erase operation.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ openings

100‧‧‧Base

102‧‧‧Stacking

102a‧‧‧Stack structure

104, 104a, 120‧‧‧ conductor layer

106, 106a‧‧‧ dielectric layer

108, 108a, 110‧‧ ‧ cover layer

112‧‧‧Surface treatment process

114‧‧‧First cover

116‧‧‧Second cover

117‧‧‧ third cover

118‧‧‧Charge storage layer

118a‧‧‧Oxide

118b‧‧‧ nitride

118c‧‧‧Oxide

H1‧‧‧ Height

P1, P2‧‧‧ part

W1, W2‧‧‧ width

1A-1F are schematic cross-sectional views showing a manufacturing process of a memory device according to an embodiment of the invention.

100: substrate 102a: stacked structure 104a, 120: conductor layer 106a: dielectric layer 114: first cap layer 116: second cap layer 117: third cap layer 118: charge storage layer 118a: yttrium oxide 118b: tantalum nitride 118c: yttrium oxide P1, P2: part

Claims (9)

A memory element comprising: a plurality of stacked structures on a substrate, each of the stacked structures comprising a plurality of first conductor layers and a plurality of dielectric layers alternately stacked with each other, and having an adjacent two stacked structures therebetween An opening; a plurality of first cover layers respectively located on sidewalls of the first conductor layers; a plurality of second cover layers respectively located on sidewalls of the dielectric layers; a second conductor layer along a first Extending and covering the stacked structures in two directions; and a charge storage layer between the substrate and the second conductor layer, and between the stacked structures and the second conductor layer, wherein the charge storage layer covers the a sidewall and a top surface of the stacked structure and a bottom of the openings to isolate the second conductor layer from the stacked structures and to isolate the second conductor layer from the substrate, wherein each of the stacked structures is along a first direction Extending, and the stacked structures and the openings are alternately arranged along the second direction, and the first direction is different from the second direction. The memory element of claim 1, wherein the materials of the first cover layers are the same as or different from the materials of the second cover layers. The memory device of claim 1, wherein the material of the first cap layer and the material of the second cap layers comprise a nitrogen-containing material. The memory element of claim 3, wherein the nitrogen-containing material comprises tantalum nitride, hafnium oxynitride or a combination thereof. The memory device of claim 1, wherein the first cap layers are respectively located between the first conductor layers and the charge storage layer, and the second cap layers are respectively located in the dielectric layers. Between this charge storage layer. A method of fabricating a memory device, comprising: forming a plurality of stacked structures on a substrate, each of the stacked structures comprising a plurality of first conductive layers and a plurality of dielectric layers, the first conductive layers and the dielectric layers Stacking alternately with each other, and having an opening between two adjacent stacked structures; and forming a plurality of first cap layers on the sidewalls of the first conductive layers, respectively, and forming on the sidewalls of the dielectric layers a plurality of second cap layers; forming a second conductor layer on the substrate, the second conductor layer extending along a second direction and covering the stacked structures; and forming a charge storage layer on the substrate, wherein the a charge storage layer is disposed between the substrate and the second conductor layer, and between the stacked structures and the second conductor layer, wherein the charge storage layer covers sidewalls and top surfaces of the stacked structures and bottoms of the openings Separating the second conductor layer from the stacked structures and isolating the second conductor layer from the substrate, wherein each of the stacked structures extends along a first direction, and the stacked structures and the openings are along The second Alternately arranged, different from the first direction and the second direction. The method of manufacturing the memory device of claim 6, wherein the first cap layers are respectively formed on sidewalls of the first conductor layers, and the sidewalls are formed on sidewalls of the dielectric layers. The second cover layer method includes performing a surface Process. The method of manufacturing a memory device according to claim 7, wherein the surface treatment process comprises a nitridation treatment, a nitrogen oxidation treatment, or a combination thereof. The method of manufacturing a memory device according to claim 8, wherein the nitriding treatment comprises a plasma treatment, a chemical vapor deposition treatment, a physical vapor deposition treatment, or a combination thereof.