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TWI567745B - So that the anti-gate flash memory has a multi-performance method - Google Patents

So that the anti-gate flash memory has a multi-performance method Download PDF

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TWI567745B
TWI567745B TW104129048A TW104129048A TWI567745B TW I567745 B TWI567745 B TW I567745B TW 104129048 A TW104129048 A TW 104129048A TW 104129048 A TW104129048 A TW 104129048A TW I567745 B TWI567745 B TW I567745B
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data storage
flash memory
block
read
data
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TW201711046A (en
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Yan-Nan Lai
Yu-Xian Wang
Chuan-Sheng Lin
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Description

使反及閘快閃記憶體具有讀多性能之方法 Method for making the anti-gate flash memory have read performance

本發明係有關一種使反及閘快閃記憶體具有讀多性能之方法,尤指一種具有增加可讀取次數以及提高資料存取可靠度之方法。 The present invention relates to a method for making a reverse flash memory having read performance, and more particularly to a method for increasing the number of readable times and improving data access reliability.

請參閱第4圖,其係為習知技術反及閘(NAND)快閃記憶體之實施例。反及閘快閃記憶體1包括一反及閘快閃記憶體控制器2以及複數個反及閘快閃記憶體晶片3,其中每一個反及閘快閃記憶體晶片包括複數個資料儲存區塊(Block)31,每一個資料儲存區塊包括複數個資料儲存頁(Page)311。反及閘快閃記憶體模組1在讀取資料或資料編程(Program)時,係以一個資料儲存頁311為單位來讀取或編程。然而抹除資料時,則必須一次抹除一整個資料儲存區塊31中之所有資料儲存頁311。另一方面,反及閘快閃記憶體有編程抹除循環的次數限制,一般商業用之單階儲存單元(Single Level Cell,SLC)反及閘快閃記憶體,其編程抹除循環的次數限制約為50,000次;而多階儲存單元(Multi Level Cell,MLC)反及閘快閃記憶體之編程抹除循環的次數限制則約為3,000次。 Please refer to FIG. 4, which is an embodiment of a conventional technology NAND flash memory. The anti-gate flash memory 1 includes a reverse flash memory controller 2 and a plurality of anti-gate flash memory chips 3, wherein each of the anti-gate flash memory chips includes a plurality of data storage areas. Block 31, each data storage block includes a plurality of data storage pages (Page) 311. The gate flash memory module 1 is read or programmed in units of a data storage page 311 when reading data or data programming. However, when erasing the data, all the data storage pages 311 in the entire data storage block 31 must be erased at one time. On the other hand, the anti-gate flash memory has a limit on the number of programming erase cycles, and the general commercial single-level storage unit (SLC) and the gate flash memory, the number of programming erase cycles The limit is about 50,000 times; the number of times the multi-level cell (MLC) and the gated flash memory programming erase cycle is about 3,000 times.

此外,反及閘快閃記憶體具有讀取之干擾以及編程之干擾之特性。例如,當多次讀取同一個資料儲存頁時,不僅會對該資料儲存頁本 身造成影響,與該資料儲存頁位於同一資料儲存區塊的其他資料儲存頁,也會因而是到干擾,因而造成儲存在同一資料儲存區塊的這些本身或是其他資料儲存頁內之資料產生錯誤。對一般商業用之單階儲存單元反及閘快閃記憶體,其讀取之干擾約在讀取1,000,000次後,即可能造成資料永久錯誤;而多階儲存單元反及閘快閃記憶體之讀取之干擾約在讀取100,000次後,即可能造成資料永久錯誤。通常一般的反及閘快閃記憶體之控制器會有一錯誤檢查及修正系統,當儲存的資料出現錯誤時,錯誤檢查及修正系統可以對每一筆資料進行計算而得到一錯誤修正碼(Error-Correcting Codes),用來檢查出錯誤並將錯誤更正。然而錯誤檢查及修正系統可以容許資料的錯誤有一定程度之極限,當超出此容錯極限時,該筆資料將無法被錯誤檢查及修正系統更正回來。而讀取之干擾以及編程之干擾所產生之資料錯誤亦必須在達到容錯極限之前被更正回來,否則將造成資料永久錯誤。 In addition, the anti-gate flash memory has the characteristics of read interference and programming interference. For example, when the same data storage page is read multiple times, not only will the page be stored for the data. As a result, other data storage pages in the same data storage block as the data storage page may also be disturbed, resulting in the generation of data stored in the same data storage block or in other data storage pages. error. For the general commercial single-stage storage unit and the gate flash memory, the interference of the reading may be caused by a permanent error after reading 1,000,000 times; and the multi-level storage unit is opposite to the gate flash memory. The interference of reading may be caused by a permanent error after about 100,000 readings. Generally, the general anti-gate flash memory controller will have an error checking and correction system. When the stored data is wrong, the error checking and correction system can calculate each data and obtain an error correction code (Error- Correcting Codes) to check for errors and correct errors. However, the error checking and correction system can tolerate a certain degree of error in the data. When the fault tolerance limit is exceeded, the data will not be corrected by the error checking and correction system. The data errors caused by the interference of the reading and the interference of the programming must also be corrected before the fault tolerance limit is reached, otherwise the data will be permanently wrong.

此外,反及閘快閃記憶體若是做為長時間的資料儲存之用途時,儲存在反及閘快閃記憶體上之資料究竟能儲存多久並無法明確知道。尤其是當這些資料當中,若有不常被編程的部分,或是長時間不被讀取的狀況,長時間下來這些資料有可能會損壞而沒被發現,使得資料之讀取之可靠度降低。 In addition, if the anti-gate flash memory is used for long-term data storage, it is not clear how long the data stored on the anti-gate flash memory can be stored. Especially when there is a part that is not frequently programmed, or if it is not read for a long time, the data may be damaged and not found for a long time, which makes the reliability of reading the data lower. .

有鑑於此,發明人開發出一種使反及閘快閃記憶體具有讀多性能之方法,可增加資料之可讀取次數,減少資料儲存區塊被抹除之頻率,以增強資料讀取之可靠性,並避免資料長時間沒被讀取而損壞,避免上述的缺點,因此遂有本發明之產生。 In view of this, the inventors have developed a method for making the anti-gate flash memory have read performance, which can increase the number of data readable times and reduce the frequency at which data storage blocks are erased, so as to enhance data reading. Reliability, and avoiding the data being damaged for a long time without being read, avoiding the above disadvantages, and thus the present invention.

本發明所欲解決之一問題是反及閘快閃記憶體之編程抹除循環的次數限制以及讀取及編程之干擾可能造成資料永久錯誤,以達到盡可能地增加資料之可讀取次數,並藉此減少資料儲存區塊被抹除之頻率之目的。 One problem to be solved by the present invention is that the number of times of programming erase cycles of the gate flash memory and the interference of reading and programming may cause permanent errors in the data, so as to increase the number of times the data can be read as much as possible. And thereby reducing the frequency of data storage blocks being erased.

本發明所欲解決之另一問題是在資料錯誤尚未超出容錯極限之前,將錯誤資料更正回來,以達到增強資料讀取之可靠度之目的。 Another problem to be solved by the present invention is to correct the error data before the data error has exceeded the fault tolerance limit, so as to enhance the reliability of data reading.

本發明所欲解決之又一問題是避免長時間未被讀取之資料在還沒被發現之前就已經永久損壞,以達到增強長時間資料儲存用途之資料讀取之可靠度之目的。 Another problem to be solved by the present invention is to prevent the data that has not been read for a long time from being permanently damaged before it is discovered, so as to achieve the purpose of enhancing the reliability of data reading for long-term data storage purposes.

為解決前述問題,以達到所預期之功效,本發明提供一種使反及閘快閃記憶體具有讀多性能之方法,其中該反及閘快閃記憶體包括複數個資料儲存區塊,每一個資料儲存區塊包括複數個資料儲存頁,該方法係為一讀取方法,包括以下步驟:A1:讀取一資料儲存區塊中之一資料儲存頁中之一資料,其中該資料儲存頁在本次被讀取後之被讀取次數為一已讀次數;以及A2:當一更新條件成立時,則結束A2步驟,否則則執行包括B1~B4步驟,其中該更新條件係為:該已讀次數小於一已讀次數門檻,其中B1~B4步驟如下:B1:將儲存於該資料儲存區塊中之一全區塊資料複製至空白之另一資料儲存區塊中,其中該全區塊資料係為儲存於該資料儲存區塊中之所有資料儲存頁中之所有資料;B2:更新一快閃轉換層映射表,使該全區塊資料之儲存位址連結指向該另一資料儲存區塊;B3:抹除儲存於該資料儲存區塊中之該全區塊資料;B4:將該已讀次數設定為0。 In order to solve the foregoing problems, in order to achieve the expected effect, the present invention provides a method for making a reverse flash memory having read performance, wherein the inverse gate flash memory includes a plurality of data storage blocks, each of which The data storage block includes a plurality of data storage pages, and the method is a reading method, comprising the following steps: A1: reading one of the data storage pages in a data storage block, wherein the data storage page is The number of times of reading after being read this time is one read number; and A2: when an update condition is established, the step A2 is ended; otherwise, the steps including B1 to B4 are performed, wherein the update condition is: The number of readings is less than the threshold of the number of readings, wherein the steps B1 to B4 are as follows: B1: copying the entire block data stored in the data storage block to another data storage block in the blank, wherein the full block The data is all the data stored in all the data storage pages in the data storage block; B2: updating a flash conversion layer mapping table, so that the storage address of the full block data is linked to the other data storage Block; B3: erase the whole block of the data stored in the data storage block; B4: The read frequency is set to 0.

於一實施例中,前述之使反及閘快閃記憶體具有讀多性能之 方法,其中A2步驟更包括計算該資料之一錯誤修正碼,其中該更新條件係為:該錯誤修正碼小於一錯誤修正碼門檻且該已讀次數小於該已讀次數門檻。 In one embodiment, the foregoing makes the anti-gate flash memory have read performance. The method, wherein the step A2 further comprises calculating one of the error correction codes of the data, wherein the update condition is that the error correction code is smaller than an error correction code threshold and the number of read times is less than the number of read times.

此外,本發明更提供一種使反及閘快閃記憶體具有讀多性能 之方法,其中該反及閘快閃記憶體包括複數個資料儲存區塊,每一個資料儲存區塊包括複數個資料儲存頁,每一個資料儲存區塊具有一區塊編號,該方法係為一讀取篩查方法,包括以下步驟:C1:令具有一起始區塊編號之資料儲存區塊為一篩查中資料儲存區塊;C2:對該篩查中資料儲存區塊執行包括D1~D2步驟:D1:讀取該篩查中資料儲存區塊之一資料儲存頁中之一資料,其中該資料儲存頁在本次被讀取後之被讀取次數為一已讀次數;D2:當一更新條件成立時,則執行C3步驟,否則則執行包括E1~E4步驟,其中該更新條件係為:該已讀次數小於一已讀次數門檻,其中E1~E4步驟如下:E1:將儲存於該篩查中資料儲存區塊之一全區塊資料複製至空白之另一資料儲存區塊中,其中該全區塊資料係為儲存於該篩查中資料儲存區塊之所有資料儲存頁中之所有資料;E2:更新一快閃轉換層映射表,使該全區塊資料之儲存位址連結指向該另一資料儲存區塊;E3:抹除儲存於該篩查中資料儲存區塊之該全區塊資料;E4:將該已讀次數設定為0以及執行C3步驟;C3:令該篩查中資料儲存區塊之區塊編號加1為一次一區塊編號;以及C4:當該次一區塊編號等於一結束區塊編號時,則執行C1步驟,否則則令具有該次一區塊編號之資料儲存區塊為該篩查中資料儲存區塊以及執行C2步驟。 In addition, the present invention further provides a read-back performance for the anti-gate flash memory. The method includes a plurality of data storage blocks, each data storage block includes a plurality of data storage pages, and each of the data storage blocks has a block number, and the method is The method for reading the screening includes the following steps: C1: the data storage block having a starting block number is a data storage block in the screening; C2: the data storage block in the screening includes D1~D2 Step: D1: reading one of the data storage pages of one of the data storage blocks in the screening, wherein the data storage page is read a number of times after being read; D2: When an update condition is met, the C3 step is performed; otherwise, the steps including E1~E4 are performed, wherein the update condition is: the read count is less than a read count threshold, wherein the E1~E4 steps are as follows: E1: will be stored in The entire block data of one of the data storage blocks in the screening is copied to another data storage block in the blank, wherein the full block data is stored in all data storage pages of the data storage block in the screening. All information; E2: a new flash conversion layer mapping table, such that the storage address of the full block data is linked to the other data storage block; E3: erasing the full block data stored in the data storage block of the screening; E4: setting the number of read times to 0 and performing step C3; C3: adding 1 to the block number of the data storage block in the screening; and C4: when the current block number is equal to When the block number is ended, the C1 step is performed. Otherwise, the data storage block having the next block number is the data storage block in the screening and the C2 step is performed.

於一實施例中,前述之使反及閘快閃記憶體具有讀多性能之 方法,其中D2步驟更包括計算該資料之一錯誤修正碼,其中該更新條件係為:該錯誤修正碼小於一錯誤修正碼門檻且該已讀次數小於該已讀次數門檻。 In one embodiment, the foregoing makes the anti-gate flash memory have read performance. The method, wherein the step D2 further comprises calculating one of the error correction codes of the data, wherein the update condition is that the error correction code is smaller than an error correction code threshold and the number of read times is less than the number of read times.

於一實施例中,前述之使反及閘快閃記憶體具有讀多性能之 方法,其中在D1步驟中係依序或隨機選取該篩查中資料儲存區塊之該篩查資料儲存頁。 In one embodiment, the foregoing makes the anti-gate flash memory have read performance. The method wherein the screening data storage page of the data storage block in the screening is sequentially or randomly selected in the step D1.

於一實施例中,前述之使反及閘快閃記憶體具有讀多性能之 方法,其中該反及閘快閃記憶體係為一獨立資料儲存體冗餘陣列,該獨立資料儲存體冗餘陣列係以至少一資料儲存體取代一標準獨立硬碟冗餘陣列(RAID)中之複數個硬碟所構成,其中該資料儲存體係為一固態硬碟、一反及閘快閃記憶體硬碟或一快閃記憶體,該固態硬碟、該反及閘快閃記憶體硬碟或該快閃記憶體包括至少一反及閘快閃記憶體晶片,該複數個資料儲存區塊係包含於每一該反及閘快閃記憶體晶片中。 In one embodiment, the foregoing makes the anti-gate flash memory have read performance. The method, wherein the anti-gate flash memory system is a redundant array of independent data storage, the redundant array of independent data storage being replaced by a standard independent hard disk redundant array (RAID) with at least one data storage body a plurality of hard disk drives, wherein the data storage system is a solid state hard disk, a reverse flash memory hard disk or a flash memory, the solid state hard disk, the anti-gate flash memory hard disk Or the flash memory includes at least one anti-gate flash memory chip, and the plurality of data storage blocks are included in each of the anti-gate flash memory chips.

於一實施例中,前述之使反及閘快閃記憶體具有讀多性能之 方法,其中該反及閘快閃記憶體係為一獨立資料儲存體冗餘陣列,該獨立資料儲存體冗餘陣列係以至少一資料儲存體取代一標準獨立硬碟冗餘陣列(RAID)中之複數個硬碟所構成,其中該資料儲存體係由至少一反及閘快閃記憶體晶片以及至少一資料儲存體控制器所構成,該複數個資料儲存區塊係包含於每一該至少一反及閘快閃記憶體晶片中。 In one embodiment, the foregoing makes the anti-gate flash memory have read performance. The method, wherein the anti-gate flash memory system is a redundant array of independent data storage, the redundant array of independent data storage being replaced by a standard independent hard disk redundant array (RAID) with at least one data storage body The data storage system is composed of at least one anti-gate flash memory chip and at least one data storage controller, and the plurality of data storage blocks are included in each of the at least one anti- And the gate flash memory chip.

此外,本發明又提供一種使反及閘快閃記憶體具有讀多性能 之方法,其中該反及閘快閃記憶體包括複數個資料儲存區塊,每一個資料 儲存區塊包括複數個資料儲存頁,該方法包括以下步驟:以前述之讀取方法來讀取一資料;以及以前述之讀取篩查方法逐一且循環地檢查每一個資料儲存區塊。 In addition, the present invention further provides a read-back performance of the anti-gate flash memory. The method, wherein the anti-gate flash memory comprises a plurality of data storage blocks, each data The storage block includes a plurality of data storage pages, and the method includes the steps of: reading a data by the foregoing reading method; and checking each of the data storage blocks one by one and cyclically by the aforementioned read screening method.

於一實施例中,前述之使反及閘快閃記憶體具有讀多性能之 方法,其中該反及閘快閃記憶體係為一獨立資料儲存體冗餘陣列,該獨立資料儲存體冗餘陣列係以至少一資料儲存體取代一標準獨立硬碟冗餘陣列(RAID)中之複數個硬碟所構成,其中該資料儲存體係為一固態硬碟、一反及閘快閃記憶體硬碟或一快閃記憶體,該固態硬碟、該反及閘快閃記憶體硬碟或該快閃記憶體包括至少一反及閘快閃記憶體晶片,該複數個資料儲存區塊係包含於每一該反及閘快閃記憶體晶片中。 In one embodiment, the foregoing makes the anti-gate flash memory have read performance. The method, wherein the anti-gate flash memory system is a redundant array of independent data storage, the redundant array of independent data storage being replaced by a standard independent hard disk redundant array (RAID) with at least one data storage body a plurality of hard disk drives, wherein the data storage system is a solid state hard disk, a reverse flash memory hard disk or a flash memory, the solid state hard disk, the anti-gate flash memory hard disk Or the flash memory includes at least one anti-gate flash memory chip, and the plurality of data storage blocks are included in each of the anti-gate flash memory chips.

於一實施例中,前述之使反及閘快閃記憶體具有讀多性能之 方法,其中該反及閘快閃記憶體係為一獨立資料儲存體冗餘陣列,該獨立資料儲存體冗餘陣列係以至少一資料儲存體取代一標準獨立硬碟冗餘陣列中之複數個硬碟所構成,其中該資料儲存體係由至少一反及閘快閃記憶體晶片以及至少一資料儲存體控制器所構成,該複數個資料儲存區塊係包含於每一該至少一反及閘快閃記憶體晶片中。 In one embodiment, the foregoing makes the anti-gate flash memory have read performance. The method, wherein the anti-gate flash memory system is a redundant array of independent data storage, the redundant array of independent data storages replacing at least one data storage body with a plurality of hard disks in a standard independent hard disk redundant array The data storage system is composed of at least one anti-gate flash memory chip and at least one data storage controller, and the plurality of data storage blocks are included in each of the at least one reverse gate In a flash memory chip.

為進一步了解本發明,以下舉較佳之實施例,配合圖式、圖號,將本發明之具體構成內容及其所達成的功效詳細說明如下。 In order to further understand the present invention, the specific embodiments of the present invention and the effects achieved thereby are described in detail below with reference to the drawings and drawings.

1‧‧‧反及閘快閃記憶體 1‧‧‧Anti-gate flash memory

2‧‧‧反及閘快閃記憶體控制器 2‧‧‧Anti-gate flash memory controller

3‧‧‧反及閘快閃記憶體晶片 3‧‧‧Anti-gate flash memory chip

31‧‧‧資料儲存區塊 31‧‧‧Data storage block

311‧‧‧資料儲存頁 311‧‧‧Data storage page

A1、A2‧‧‧步驟 A1, A2‧‧‧ steps

B1、B2、B3、B4‧‧‧步驟 B1, B2, B3, B4‧‧‧ steps

C1、C2、C3‧‧‧步驟 C1, C2, C3‧‧‧ steps

D1、D2‧‧‧步驟 D1, D2‧‧‧ steps

E1、E2、E3、E4‧‧‧步驟 E1, E2, E3, E4‧‧‧ steps

F1、F2、F3‧‧‧步驟 F1, F2, F3‧‧‧ steps

第1圖係為本發明使反及閘快閃記憶體具有讀多性能之方法之第一具體實施例之流程圖。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a flow diagram of a first embodiment of the method of the present invention for enabling the read-back performance of the anti-gate flash memory.

第1A圖係為本發明使反及閘快閃記憶體具有讀多性能之方法之第二具體實施例之流程圖。 Figure 1A is a flow diagram of a second embodiment of the method of the present invention for enabling the read-back performance of the anti-gate flash memory.

第2圖係為本發明使反及閘快閃記憶體具有讀多性能之方法之第三具體實施例之流程圖。 Fig. 2 is a flow chart showing a third embodiment of the method for making the gate flash memory have read performance.

第2A圖係為本發明使反及閘快閃記憶體具有讀多性能之方法之第四具體實施例之流程圖。 Fig. 2A is a flow chart showing a fourth embodiment of the method for making the anti-gate flash memory have read performance.

第3圖係為本發明使反及閘快閃記憶體具有讀多性能之方法之第五具體實施例之流程圖。 Figure 3 is a flow chart showing a fifth embodiment of the method for making the anti-gate flash memory have read performance.

第4圖係為習知技術反及閘快閃記憶體之實施例。 Figure 4 is an embodiment of a conventional technique against gate flash memory.

請參閱第1圖,其係為本發明使反及閘快閃記憶體具有讀多性能之方法之第一具體實施例之流程圖,其中反及閘快閃記憶體包括複數個資料儲存區塊,每一個資料儲存區塊包括複數個資料儲存頁。該方法係為一讀取方法,包括以下步驟:A1:讀取一資料儲存區塊中之一資料儲存頁中之一資料,其中資料儲存頁在本次被讀取後之被讀取次數為一已讀次數;以及A2:當一更新條件成立時,則結束A2步驟,否則則執行包括B1~B4步驟,其中更新條件係為:已讀次數小於一已讀次數門檻,其中B1~B4步驟如下:B1:將儲存於資料儲存區塊中之一全區塊資料複製至空白之另一資料儲存區塊中,其中全區塊資料係為儲存於資料儲存區塊中之所有資料儲存頁中之所有資料;B2:更新一快閃轉換層映射表,使全區塊資料之儲存位址連結指向另一資料儲存區塊;B3:抹除儲存於資料儲存區塊中之 全區塊資料;B4:將已讀次數設定為0。 Please refer to FIG. 1 , which is a flowchart of a first embodiment of a method for enabling a gate flash memory to have read performance, wherein the gate flash memory includes a plurality of data storage blocks. Each data storage block includes a plurality of data storage pages. The method is a reading method, comprising the following steps: A1: reading one of the data storage pages in a data storage block, wherein the data storage page is read after the current reading is A number of times read; and A2: when an update condition is established, the process of step A2 is ended; otherwise, the steps including B1 to B4 are performed, wherein the update condition is: the number of times read is less than the threshold of a number of read times, wherein steps B1 to B4 As follows: B1: Copy all the block data stored in the data storage block to another data storage block in the blank, wherein the whole block data is stored in all data storage pages in the data storage block. All the data; B2: update a flash conversion layer mapping table, so that the storage address of the entire block data link to another data storage block; B3: erase the data stored in the data storage block Full block data; B4: Set the number of times read to 0.

請參閱第1A圖,其係為本發明使反及閘快閃記憶體具有讀 多性能之方法之第二具體實施例之流程圖,該方法係為一讀取方法,其係與第一具體實施例大致相同,惟,步驟A2係由步驟A2’所取代,其中步驟A2’:計算資料之一錯誤修正碼,當更新條件成立時,則結束A2’步驟,否則則執行包括B1~B4步驟,其中更新條件係為:錯誤修正碼小於一錯誤修正碼門檻且已讀次數小於已讀次數門檻。 Please refer to FIG. 1A, which is a view of the present invention for making the anti-gate flash memory read. A flow chart of a second embodiment of the multi-performance method, which is a reading method, which is substantially the same as the first embodiment, except that step A2 is replaced by step A2', wherein step A2' : Calculate one of the error correction codes. When the update condition is met, the step A2' is ended. Otherwise, the steps including B1 to B4 are performed, wherein the update condition is: the error correction code is smaller than an error correction code threshold and the read count is less than The threshold has been read.

B4步驟中可更包括將資料儲存區塊中之所有資料儲存頁之 被讀取次數設定為0以及將另一資料儲存區塊中之所有資料儲存頁之被讀取次數設定為0。 In step B4, the data storage page in the data storage block may be further included. The number of times read is set to 0 and the number of times of reading of all data storage pages in another data storage block is set to zero.

在每次讀取一筆資料時,若只有檢查該筆資料之錯誤修正碼 是否已達錯誤修正碼門檻,則有可能發生以下狀況:該筆資料一直尚未達到錯誤修正碼門檻,然而該筆資料之已讀次數卻早已超過已讀次數門檻。 如此一來,將會造成該筆資料永久錯誤,再也無法回復之狀況。此外,若只檢查該筆資料之已讀次數是否已達已讀次數門檻,則有可能該筆資料一直尚未達到已讀次數門檻,而該筆資料之錯誤修正碼卻早已超過錯誤修正碼門檻。如此一來,亦會造成該筆資料永久錯誤。因此透過本發明之使反及閘快閃記憶體具有讀多性能之方法,在每次讀取一筆資料時,同時檢查該筆資料之已讀次數是否已達已讀次數門檻以及檢查該筆資料之錯誤修正碼是否已達錯誤修正碼門檻。當該筆資料之已讀次數尚未達到已讀次數門檻且該筆資料之錯誤修正碼尚未達到錯誤修正碼門檻時,則表示該筆資料尚在安全範圍內,可以繼續安全地被讀取,藉此盡可能地增多該筆資料在 該資料儲存區塊上可被讀取之次數,從而使反及閘快閃記憶體具有讀多之性能,並藉此減少資料儲存區塊被抹除之頻率。一旦該筆資料之已讀次數達到已讀次數門檻或該筆資料之錯誤修正碼達到錯誤修正碼門檻時,則表示該筆資料已經瀕臨資料永久錯誤之危險,因此在該筆資料在尚能更正回復時,將該筆資料重新寫在空白之另一個資料儲存區塊上,如此將使該筆資料之已讀次數重新歸零,並同時使該筆資料之錯誤修正碼重新歸零。 Every time you read a piece of data, if there is only an error correction code to check the data If the error correction code threshold has been reached, the following situation may occur: the data has not reached the error correction code threshold, but the number of times the data has been read has already exceeded the threshold of the number of readings. As a result, the information will be permanently wrong and will no longer be able to respond. In addition, if it is only checked whether the number of readings of the data has reached the threshold of reading, it is possible that the data has not yet reached the threshold of reading, and the error correction code of the data has already exceeded the threshold of the error correction code. As a result, this information will also cause permanent errors. Therefore, through the method of the present invention, the anti-gate flash memory has a multi-reading performance, and each time a piece of data is read, the number of times the read data has been read has been checked to the level of the read count and the data is checked. Whether the error correction code has reached the error correction code threshold. When the number of times the data has been read has not reached the threshold of the number of readings and the error correction code of the data has not reached the threshold of the error correction code, it indicates that the data is still within the safe range, and can continue to be safely read. This is as much as possible to increase the information in The number of times the data storage block can be read, so that the anti-gate flash memory has read performance and thereby reduces the frequency at which the data storage block is erased. Once the number of times the data has been read reaches the threshold of the number of readings or the error correction code of the data reaches the threshold of the error correction code, it indicates that the data is in danger of a permanent error of the data, so the data can still be corrected. When replying, the data is re-written in another data storage block of the blank, so that the number of times the data has been read is reset to zero, and the error correction code of the data is reset to zero.

但是,光是對每次要讀取的資料做檢查並不夠。許多被儲存 在同一個資料儲存區塊內之資料有可能在被儲存之後經過很長久的時間都不會被讀取,長時間下來這些資料有可能會損壞而沒被發現。為避免上述之狀況發生,請參閱第2圖,本發明另提供使反及閘快閃記憶體具有讀多性能之方法之第三具體實施例,其中反及閘快閃記憶體包括複數個資料儲存區塊,每一個資料儲存區塊包括複數個資料儲存頁,每一個資料儲存區塊具有一區塊編號。該方法係為一讀取篩查方法,包括以下步驟:C1:令具有一起始區塊編號之資料儲存區塊為一篩查中資料儲存區塊;C2:對篩查中資料儲存區塊執行包括D1~D2步驟:D1:讀取篩查中資料儲存區塊之一資料儲存頁中之一資料,其中資料儲存頁在本次被讀取後之被讀取次數為一已讀次數;D2:當一更新條件成立時,則執行C3步驟,否則則執行包括E1~E4步驟,其中更新條件係為:已讀次數小於一已讀次數門檻,其中E1~E4步驟如下:E1:將儲存於篩查中資料儲存區塊之一全區塊資料複製至空白之另一資料儲存區塊中,其中全區塊資料係為儲存於篩查中資料儲存區塊之所有資料儲存頁中之所有資料;E2:更新一快閃轉換層映射表,使全區塊資料之儲存位址連結指向另一資料儲存區塊;E3:抹除儲存於篩查 中資料儲存區塊之全區塊資料;E4:將已讀次數設定為0以及執行C3步驟;C3:令篩查中資料儲存區塊之區塊編號加1為一次一區塊編號;以及C4:當次一區塊編號等於一結束區塊編號時,則執行C1步驟,否則則令具有次一區塊編號之資料儲存區塊為篩查中資料儲存區塊以及執行C2步驟。透過此讀取篩查方法,在系統閒暇之時對所有的資料儲存區塊逐一且循環地做檢查。藉此,使得每一個資料儲存區塊在一段時間內就會被逐一讀取並檢查,以避免發生資料長時間沒被讀取而損壞之狀況。 However, it is not enough to check the data to be read every time. Many are stored The data in the same data storage block may not be read after a long period of time after being stored. The data may be damaged and not found for a long time. In order to avoid the above situation, please refer to FIG. 2, which further provides a third embodiment of a method for enabling the read-back performance of the anti-gate flash memory, wherein the anti-gate flash memory includes a plurality of data. The storage block, each data storage block includes a plurality of data storage pages, and each of the data storage blocks has a block number. The method is a read screening method, comprising the following steps: C1: making a data storage block having a starting block number a data storage block in a screening; C2: performing a data storage block in the screening Including D1~D2 steps: D1: reading one of the data storage pages in one of the data storage blocks in the screening, wherein the number of times the data storage page is read after being read this time is one read number; D2 : When an update condition is met, the C3 step is performed; otherwise, the steps including E1~E4 are performed, wherein the update condition is: the number of read times is less than the threshold of the number of read times, wherein the steps of E1~E4 are as follows: E1: will be stored in The entire block data of one of the data storage blocks in the screening is copied to another data storage block in the blank. The whole block data is all the data stored in all the data storage pages of the data storage block in the screening. ; E2: update a flash conversion layer mapping table, so that the storage address of the entire block data link to another data storage block; E3: erase and store in the screening The total block data of the middle data storage block; E4: set the number of read times to 0 and perform the C3 step; C3: increase the block number of the data storage block in the screening by one for one block number; and C4 : When the next block number is equal to an end block number, the C1 step is performed; otherwise, the data storage block having the next block number is the data storage block in the screening and the C2 step is performed. Through this read screening method, all data storage blocks are checked one by one and cyclically while the system is idle. In this way, each data storage block is read and checked one by one for a period of time to avoid the situation that the data is not damaged after being read for a long time.

請參閱第2A圖,其係為本發明使反及閘快閃記憶體具有讀 多性能之方法之第四具體實施例之流程圖,該方法係為一讀取篩查方法,其係與第三具體實施例大致相同,惟,步驟D2係由步驟D2’所取代,其中步驟D2’:計算資料之一錯誤修正碼,當更新條件成立時,則結束D2’步驟,否則則執行包括E1~E4步驟,其中更新條件係為:錯誤修正碼小於一錯誤修正碼門檻且已讀次數小於已讀次數門檻。 Please refer to FIG. 2A, which is a method for making the anti-gate flash memory read. A flow chart of a fourth embodiment of the multi-performance method, which is a read screening method, which is substantially the same as the third embodiment, except that step D2 is replaced by step D2', wherein the step D2': Calculate one of the error correction codes. When the update condition is met, the D2' step is ended. Otherwise, the steps including E1~E4 are performed, wherein the update condition is: the error correction code is smaller than an error correction code threshold and has been read. The number of times is less than the threshold of the number of readings.

E4步驟中可更包括將篩查中資料儲存區塊之所有資料儲存 頁之被讀取次數設定為0以及將另一資料儲存區塊之所有資料儲存頁之被讀取次數設定為0。 The E4 step may further include storing all data in the data storage block in the screening. The number of times the page is read is set to 0 and the number of times the data storage page of another data storage block is read is set to zero.

D1步驟中係可依序或隨機選取篩查中資料儲存區塊之篩查 資料儲存頁。 In the D1 step, the screening of the data storage block in the screening can be selected sequentially or randomly. Data storage page.

此外,請參閱第3圖,本發明另提供使反及閘快閃記憶體具 有讀多性能之方法之第五具體實施例,其中反及閘快閃記憶體包括複數個資料儲存區塊,每一個資料儲存區塊包括複數個資料儲存頁,該方法包括以下步驟:以本發明之第一具體實施例或第二具體實施例之讀取方法來讀 取一資料;以及在系統閒暇時於背景中以本發明之第三具體實施例或第四具體實施例之讀取篩查方法逐一且循環地檢查每一個資料儲存區塊。當在一般需要讀取資料時,係使用該讀取方法來讀取資料;而在系統閒暇時,則在背景中以該讀取篩查方法逐一且循環地檢查每一個資料儲存區塊。藉此,盡可能地增多該筆資料在該資料儲存區塊上可被讀取之次數,以增進資料讀取之可靠性,且每一個資料儲存區塊在一段時間內就會被逐一讀取並檢查,以避免發生資料長時間沒被讀取而損壞之狀況。 In addition, referring to FIG. 3, the present invention further provides an anti-gate flash memory device. A fifth embodiment of the method for reading multi-performance, wherein the anti-gate flash memory comprises a plurality of data storage blocks, each of the data storage blocks comprising a plurality of data storage pages, the method comprising the following steps: Reading the first embodiment of the invention or the reading method of the second embodiment A data is taken; and each data storage block is inspected one by one and cyclically in the background with the third embodiment of the present invention or the read screening method of the fourth embodiment when the system is idle. When the data is generally required to be read, the reading method is used to read the data; and when the system is idle, each of the data storage blocks is checked one by one and cyclically in the background by the reading screening method. Thereby, the number of times the data can be read in the data storage block is increased as much as possible, so as to improve the reliability of data reading, and each data storage block is read one by one for a period of time. And check to avoid the situation that the data is not damaged after being read for a long time.

本發明之使反及閘快閃記憶體具有讀多性能之方法之第一 ~第五具體實施例亦可搭配應用在一般標準之獨立硬碟冗餘陣列(RAID)架構上。原本一般標準之獨立硬碟冗餘陣列所使用的是複數個一般的硬碟,而這複數個一般的硬碟係可以至少一資料儲存體來取代,而形成一獨立資料儲存體冗餘陣列,其中每一資料儲存體中包括複數個資料儲存區塊。在獨立資料儲存體冗餘陣列的架構上使用本發明之一種使反及閘快閃記憶體具有讀多性能之方法,更能強化資料存取的可靠度及完整性。 The first method for making the anti-gate flash memory have read performance The fifth embodiment can also be applied to a standard hard disk redundancy array (RAID) architecture. The conventional standard hard disk redundant array uses a plurality of general hard disks, and the plurality of general hard disk systems can be replaced by at least one data storage to form a redundant array of independent data storage. Each of the data stores includes a plurality of data storage blocks. The use of a method of the present invention to enable the anti-gate flash memory to have read performance on the architecture of the redundant array of independent data storages further enhances the reliability and integrity of data access.

前述取代一般的硬碟之資料儲存體係可為一固態硬碟、一反 及閘快閃記憶體硬碟或一快閃記憶體。而固態硬碟、反及閘快閃記憶體硬碟或快閃記憶體中包括至少一反及閘快閃記憶體晶片,而每一反及閘快閃記憶體晶片中包括複數個資料儲存區塊。 The above-mentioned data storage system for replacing a general hard disk may be a solid state hard disk or a reverse And the flash memory hard disk or a flash memory. The solid state hard disk, the anti-gate flash memory hard disk or the flash memory includes at least one anti-gate flash memory chip, and each of the anti-gate flash memory chips includes a plurality of data storage areas. Piece.

前述取代一般的硬碟之資料儲存體係亦可使用至少一反及 閘快閃記憶體晶片以及至少一資料儲存體控制器來取代,其中每一反及閘快閃記憶體晶片中包括複數個資料儲存區塊。 The above-mentioned data storage system replacing the general hard disk may also use at least one The gate flash memory chip and at least one data storage controller are replaced, wherein each of the anti-gate flash memory chips includes a plurality of data storage blocks.

前述之一般標準之獨立硬碟冗餘陣列架構包括例如RAID 0 或RAID 5之架構。 The aforementioned general standard independent hard disk redundant array architecture includes, for example, RAID 0 Or the architecture of RAID 5.

以上所述乃是本發明之具體實施例及所運用之技術手段,根 據本文的揭露或教導可衍生推導出許多的變更與修正,仍可視為本發明之構想所作之等效改變,其所產生之作用仍未超出說明書及圖式所涵蓋之實質精神,均應視為在本發明之技術範疇之內,合先陳明。 The above is a specific embodiment of the present invention and the technical means applied thereto, Many variations and modifications can be derived from the present disclosure or the teachings of the present invention. The equivalents of the present invention are still considered to be equivalent to the spirit of the present invention. In the technical scope of the present invention, it is first known.

綜上所述,依上文所揭示之內容,本發明確可達到發明之預 期目的,提供一種使反及閘快閃記憶體具有讀多性能之方法,增加資料之可讀取次數,減少資料儲存區塊被抹除之頻率,增強資料讀取之可靠性以及避免資料長時間沒被讀取而損壞,極具產業上利用之價植,爰依法提出發明專利申請。 In summary, the present invention can achieve the pre-invention according to the above disclosure. The purpose is to provide a method for making the anti-gate flash memory have read performance, increase the number of data readable, reduce the frequency of data storage blocks being erased, enhance the reliability of data reading and avoid data length. The time has not been read and damaged, and it is very expensive to use in the industry.

A1、A2‧‧‧步驟 A1, A2‧‧‧ steps

B1、B2、B3、B4‧‧‧步驟 B1, B2, B3, B4‧‧‧ steps

Claims (10)

一種使反及閘快閃記憶體具有讀多性能之方法,其中該反及閘快閃記憶體包括複數個資料儲存區塊,每一個資料儲存區塊包括複數個資料儲存頁,該方法係為一讀取方法,包括以下步驟:A1:讀取一資料儲存區塊中之一資料儲存頁中之一資料,其中該資料儲存頁在本次被讀取後之被讀取次數為一已讀次數;以及A2:當一更新條件成立時,則結束A2步驟,否則則執行包括B1~B4步驟,其中該更新條件係為:該已讀次數小於一已讀次數門檻,其中B1~B4步驟如下:B1:將儲存於該資料儲存區塊中之一全區塊資料複製至空白之另一資料儲存區塊中,其中該全區塊資料係為儲存於該資料儲存區塊中之所有資料儲存頁中之所有資料;B2:更新一快閃轉換層映射表,使該全區塊資料之儲存位址連結指向該另一資料儲存區塊;B3:抹除儲存於該資料儲存區塊中之該全區塊資料;B4:將該已讀次數設定為0。 A method for making a reverse flash memory having read performance, wherein the inverse flash memory comprises a plurality of data storage blocks, each data storage block comprising a plurality of data storage pages, wherein the method is A reading method comprises the following steps: A1: reading one of the data storage pages in a data storage block, wherein the data storage page is read one time after being read. The number of times; and A2: when an update condition is established, the process of step A2 is ended; otherwise, the steps including B1 to B4 are performed, wherein the update condition is: the number of read times is less than the threshold of a number of read times, wherein the steps B1 to B4 are as follows :B1: Copying the entire block data stored in the data storage block to another data storage block in the blank, wherein the full block data is all data stored in the data storage block. All the information in the page; B2: update a flash conversion layer mapping table, so that the storage address of the full block data is linked to the other data storage block; B3: erasing and storing in the data storage block The whole block Material B4: Set the number of readings to 0. 如申請專利範圍第1項所述之使反及閘快閃記憶體具有讀多性能之方法,其中A2步驟更包括計算該資料之一錯誤修正碼,其中該更新條件係為:該錯誤修正碼小於一錯誤修正碼門檻且該已讀次數小於該已讀次數門檻。 For example, in the method of claim 1, the method for making the anti-gate flash memory have read performance, wherein the step A2 further comprises calculating an error correction code of the data, wherein the update condition is: the error correction code It is less than an error correction code threshold and the number of read times is less than the threshold of the read number. 一種使反及閘快閃記憶體具有讀多性能之方法,其中該反及閘快閃記憶體包括複數個資料儲存區塊,每一個資料儲存區塊包括複數個資料儲存頁,每一個資料儲存區塊具有一區塊編號,該方法係為一讀取篩查方法, 包括以下步驟:C1:令具有一起始區塊編號之資料儲存區塊為一篩查中資料儲存區塊;C2:對該篩查中資料儲存區塊執行包括D1~D2步驟:D1:讀取該篩查中資料儲存區塊之一資料儲存頁中之一資料,其中該資料儲存頁在本次被讀取後之被讀取次數為一已讀次數;D2:當一更新條件成立時,則執行C3步驟,否則則執行包括E1~E4步驟,其中該更新條件係為:該已讀次數小於一已讀次數門檻,其中E1~E4步驟如下:E1:將儲存於該篩查中資料儲存區塊之一全區塊資料複製至空白之另一資料儲存區塊中,其中該全區塊資料係為儲存於該篩查中資料儲存區塊之所有資料儲存頁中之所有資料;E2:更新一快閃轉換層映射表,使該全區塊資料之儲存位址連結指向該另一資料儲存區塊;E3:抹除儲存於該篩查中資料儲存區塊之該全區塊資料;E4:將該已讀次數設定為0以及執行C3步驟;C3:令該篩查中資料儲存區塊之區塊編號加1為一次一區塊編號;以及C4:當該次一區塊編號等於一結束區塊編號時,則執行C1步驟,否則則令具有該次一區塊編號之資料儲存區塊為該篩查中資料儲存區塊以及執行C2步驟。 A method for making a reverse flash memory having read performance, wherein the inverse flash memory comprises a plurality of data storage blocks, each data storage block comprising a plurality of data storage pages, each data storage The block has a block number, and the method is a read screening method. The method includes the following steps: C1: the data storage block having a starting block number is a data storage block in the screening; C2: performing the D1~D2 step in the data storage block in the screening: D1: reading One of the data storage pages of the data storage block in the screening, wherein the data storage page is read a number of times after being read; D2: when an update condition is established, Then, the step C3 is performed; otherwise, the steps including E1~E4 are performed, wherein the update condition is: the read count is less than a read count threshold, wherein the E1~E4 steps are as follows: E1: the data stored in the screening is stored. The entire block data of one of the blocks is copied to another data storage block of the blank, wherein the full block data is all the data stored in all the data storage pages of the data storage block in the screening; E2: Updating a flash translation layer mapping table to link the storage address of the full block data to the another data storage block; E3: erasing the full block data stored in the data storage block of the screening; E4: Set the number of readings to 0 and execute Step C3: C3: Add 1 to the block number of the data storage block in the screening; and C4: When the current block number is equal to an ending block number, perform the C1 step. Otherwise, the data storage block having the current block number is the data storage block in the screening and the C2 step is performed. 如申請專利範圍第3項所述之使反及閘快閃記憶體具有讀多性能之方法,其中D2步驟更包括計算該資料之一錯誤修正碼,其中該更新條件係為:該錯誤修正碼小於一錯誤修正碼門檻且該已讀次數小於該已讀次數門檻。 For example, in the method of claim 3, the anti-gate flash memory has a read multi-performance method, wherein the D2 step further comprises calculating an error correction code of the data, wherein the update condition is: the error correction code It is less than an error correction code threshold and the number of read times is less than the threshold of the read number. 如申請專利範圍第3項所述之使反及閘快閃記憶體具有讀多性能之方法,其中在D1步驟中係依序或隨機選取該篩查中資料儲存區塊之該資料儲存頁。 For example, in the method of claim 3, the anti-gate flash memory has a read multi-performance method, wherein the data storage page of the data storage block in the screening is sequentially or randomly selected in the D1 step. 如申請專利範圍第1項至第5項中任一項所述之使反及閘快閃記憶體具有讀多性能之方法,其中該反及閘快閃記憶體係為一獨立資料儲存體冗餘陣列,該獨立資料儲存體冗餘陣列係以至少一資料儲存體取代一標準獨立硬碟冗餘陣列中之複數個硬碟所構成,其中該資料儲存體係為一固態硬碟、一反及閘快閃記憶體硬碟或一快閃記憶體,該固態硬碟、該反及閘快閃記憶體硬碟或該快閃記憶體包括至少一反及閘快閃記憶體晶片,該複數個資料儲存區塊係包含於每一該反及閘快閃記憶體晶片中。 The method for making the anti-gate flash memory have read performance as described in any one of claims 1 to 5, wherein the anti-gate flash memory system is an independent data storage redundancy. The array, the redundant array of independent data storages is formed by replacing at least one data storage body with a plurality of hard disks in a standard independent hard disk redundant array, wherein the data storage system is a solid state hard disk, a reverse gate a flash memory hard disk or a flash memory, the solid state hard disk, the reverse flash memory hard disk or the flash memory body including at least one anti-gate flash memory chip, the plurality of data A storage block is included in each of the anti-gate flash memory chips. 如申請專利範圍第1項至第5項中任一項所述之使反及閘快閃記憶體具有讀多性能之方法,其中該反及閘快閃記憶體係為一獨立資料儲存體冗餘陣列,該獨立資料儲存體冗餘陣列係以至少一資料儲存體取代一標準獨立硬碟冗餘陣列中之複數個硬碟所構成,其中該資料儲存體係由至少一反及閘快閃記憶體晶片以及至少一資料儲存體控制器所構成,該複數個資料儲存區塊係包含於每一該至少一反及閘快閃記憶體晶片中。 The method for making the anti-gate flash memory have read performance as described in any one of claims 1 to 5, wherein the anti-gate flash memory system is an independent data storage redundancy. The array, the redundant array of independent data storages is formed by replacing at least one data storage body with a plurality of hard disks in a standard independent hard disk redundant array, wherein the data storage system is composed of at least one anti-gate flash memory The chip and the at least one data storage controller are configured, and the plurality of data storage blocks are included in each of the at least one anti-gate flash memory chips. 一種使反及閘快閃記憶體具有讀多性能之方法,其中該反及閘快閃記憶體包括複數個資料儲存區塊,每一個資料儲存區塊包括複數個資料儲存頁,該方法包括以下步驟:以如申請專利範圍第1項所述之讀取方法來讀取一資料;以及以如申請專利範圍第4項所述之讀取篩查方法逐一且循環地檢查每一個資料儲存區塊。 A method for making a reverse flash memory having read performance, wherein the inverse flash memory comprises a plurality of data storage blocks, each data storage block comprising a plurality of data storage pages, the method comprising the following Step: reading a data by a reading method as described in claim 1 of the patent application; and checking each data storage block one by one and cyclically by a reading screening method as described in claim 4 of the patent application scope . 如申請專利範圍第8項所述之使反及閘快閃記憶體具有讀多性能之方法,其中該反及閘快閃記憶體係為一獨立資料儲存體冗餘陣列,該獨立資料儲存體冗餘陣列係以至少一資料儲存體取代一標準獨立硬碟冗餘陣列中之複數個硬碟所構成,其中該資料儲存體係為一固態硬碟、一反及閘快閃記憶體硬碟或一快閃記憶體,該固態硬碟、該反及閘快閃記憶體硬碟或該快閃記憶體包括至少一反及閘快閃記憶體晶片,該複數個資料儲存區塊係包含於每一該反及閘快閃記憶體晶片中。 For example, in the method of claim 8, the anti-gate flash memory has a read multi-performance method, wherein the anti-gate flash memory system is a redundant array of independent data storage, and the independent data storage is redundant. The remaining array is formed by replacing at least one data storage body with a plurality of hard disks in a standard independent hard disk redundant array, wherein the data storage system is a solid state hard disk, a reverse flash memory hard disk or a The flash memory, the solid-state hard disk, the anti-gate flash memory hard disk or the flash memory includes at least one anti-gate flash memory chip, and the plurality of data storage blocks are included in each The reverse gate flash memory chip. 如申請專利範圍第8項所述之使反及閘快閃記憶體具有讀多性能之方法,其中該反及閘快閃記憶體係為一獨立資料儲存體冗餘陣列,該獨立資料儲存體冗餘陣列係以至少一資料儲存體取代一標準獨立硬碟冗餘陣列中之複數個硬碟所構成,其中該資料儲存體係由至少一反及閘快閃記憶體晶片以及至少一資料儲存體控制器所構成,該複數個資料儲存區塊係包含於每一該至少一反及閘快閃記憶體晶片中。 For example, in the method of claim 8, the anti-gate flash memory has a read multi-performance method, wherein the anti-gate flash memory system is a redundant array of independent data storage, and the independent data storage is redundant. The remaining array is formed by replacing at least one data storage body with a plurality of hard disks in a standard independent hard disk redundant array, wherein the data storage system is controlled by at least one anti-gate flash memory chip and at least one data storage body The plurality of data storage blocks are included in each of the at least one anti-gate flash memory chips.
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