TWI665679B - Method for accessing flash memory module and associated flash memory controller and memory device - Google Patents

Abstract

The invention discloses a method for accessing a flash memory module, wherein the flash memory module is a three-dimensional flash memory module including a plurality of flash memory chips, and each flash memory The body chip includes a plurality of blocks, each block includes a plurality of data pages; and the method includes: planning the plurality of flash memory chips so that the plurality of flash memory chips have at least one first A superblock and at least one second superblock; and assigning the at least one second superblock to store a plurality of sets of temporary codes generated during a process of writing data to the at least one first superblock. Checksum.

Description

Method for accessing flash memory module and related flash memory controller and memory device

The invention relates to a flash memory, in particular to a method for accessing a flash memory module and a related flash memory controller and memory device.

In order to enable flash memory to have higher density and larger capacity, the process of flash memory is also moving towards three-dimensional development, and several different three-dimensional NAND-type flash memories (3D NAND-type flash). In the three-dimensional NAND flash memory, due to the difference in the overall structure and the change in the shape and position of the floating gate, it also has a little more problems in writing and reading data than the traditional flat NAND flash memory. . For example, in some three-dimensional NAND-type flash memories, multiple word lines are defined as a word line group, and the word line group will have a part of the control circuit in common. When the writing of data to a floating transistor on one of the character line groups fails (write failure), the data of the floating transistor on the other character lines of the character line group will be accompanied. An error occurred; in addition, if a character line in the character line group is broken or shorted, the data of the floating transistor on the other character lines of the character line group will also be incorrect. Therefore, how to propose an error correction method for the above problems to maintain the correctness of the data as much as possible without wasting memory space to save costs is an important issue.

Therefore, one of the objectives of the present invention is to provide a method for accessing a flash memory module and a related flash memory controller and memory device, which use similar Redundant Array of Independent Disks, RAID) error correction method, but it will not significantly waste flash memory space, and only a small amount of buffer memory space is required during the processing of the flash memory controller to solve the problems in the prior art .

In one embodiment of the present invention, a method for accessing a flash memory module is disclosed, wherein the flash memory module is a three-dimensional flash memory module, and the flash memory module Contains multiple flash memory chips, each flash memory chip contains multiple multi-layer storage blocks and multiple single-layer storage blocks, each block contains multiple data pages; each area The block contains multiple floating transistor transistors controlled by multiple word lines and bit lines respectively located on multiple different planes, and the floating transistor transistors on each character line constitute at least one of the multiple data pages. A data page; and the method includes: encoding a data to generate at least one set of check codes, wherein the data is ready to be written into a first super block of the plurality of flash memory chips, wherein The first super block includes a multi-layer storage block of each of the plurality of flash memory chips; writing the data to the first super block; and the at least one Write a check code to a second super Block, wherein the second super block comprises the plurality of flash memory chips in a single-level storage blocks each flash memory chip.

In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory module is A three-dimensional flash memory module. The flash memory module includes a plurality of flash memory chips. Each flash memory chip includes a plurality of multi-layer storage blocks and a plurality of single-layer storage areas. Block, each block contains multiple data pages; each block contains multiple word lines and bit lines respectively located on multiple different planes to control multiple floating gate transistors, and each character The floating transistor on the line constitutes at least one data page of the plurality of data pages; and the flash memory controller includes: a memory, a microprocessor, and a codec. The memory is used to store a program code; the microprocessor is used to execute the program code to control access to the flash memory module; and in the operation of this embodiment, the codec performs data processing on a piece of data. Encoding to generate at least one set of check codes, wherein the data is ready to be written into a first super block of the plurality of flash memory chips, wherein the first super block contains the plurality of flash memories A multi-level storage block of each flash memory chip in the body chip; and the microprocessor writes the data to the first super block, and writes the at least one set of check codes to a first Among the two super blocks, the second super block includes a single-layer storage block of each of the plurality of flash memory chips.

In another embodiment of the present invention, a memory device is disclosed, which includes a flash memory module and a flash memory controller, wherein the flash memory module is a three-dimensional flash memory. Module, the flash memory module contains multiple flash memory chips, each flash memory chip contains multiple multi-layer storage blocks and multiple single-layer storage blocks, each block Contains multiple data pages; each block contains multiple word lines and bit lines that are located on multiple different planes to control multiple floating gate transistors, and each block has floating gate transistors Constitutes at least one data page of the plurality of data pages; and the flash memory controller receives a write command from a host to request data to be written into the flash memory module, Encode the data to generate at least one set of check codes, and write the data into a first super block of the plurality of flash memory chips, wherein the first super block includes the plurality of Every flash in the flash memory chip A multi-layer storage block of a memory chip; and writing the at least one set of check codes into a second super block, wherein the second super block includes each of the plurality of flash memory chips A single-layer storage block of a flash memory chip.

In another embodiment of the present invention, a method for accessing a flash memory module is disclosed, wherein the flash memory module is a three-dimensional flash memory module, and the flash memory module The group contains multiple flash memory chips, each flash memory chip contains multiple blocks, each block contains multiple data pages, and each block contains a number of different planes. Word lines and bit lines to control a plurality of floating transistors, and each floating transistor on each word line constitutes at least one of the plurality of data pages; and the method includes: planning The plurality of flash memory chips so that the plurality of flash memory chips have at least a first super block and at least a second super block; and assign the at least one second super block to It is used to store a plurality of temporary check codes generated during the process of writing data into the at least one first superblock.

In another embodiment of the present invention, a flash memory controller is disclosed. The flash memory controller is used to access a flash memory module, wherein the flash memory module is A stereo flash memory module, the flash memory module includes multiple flash memory chips, each flash memory chip contains multiple blocks, and each block contains multiple data pages ; Each block contains multiple word lines and bit lines that are located on multiple different planes to control multiple floating gate transistors, and the floating gate transistors on each word line constitute the multiple data At least one data page in the page; and the flash memory controller includes a memory, a microprocessor, and a codec. The memory is used to store a program code; the microprocessor is used to execute the program code to control access to the flash memory module; and in the operation of this embodiment, the microprocessor plans the multiple A flash memory chip so that the plurality of flash memory chips have at least a first super block and at least a second super block; and assign the at least one second super block for storing a data write A plurality of sets of temporary check codes generated during encoding into the at least one first superblock.

In another embodiment of the present invention, a memory device is disclosed, which includes a flash memory module and a flash memory controller. The flash memory module is a three-dimensional flash memory module. The flash memory module includes a plurality of flash memory chips. Each flash memory chip includes a plurality of blocks. One block contains multiple data pages; each block contains multiple character lines and bit lines that are located on multiple different planes to control multiple floating gate transistors, and the floating on each character line The gate transistor constitutes at least one of the plurality of data pages; and the flash memory controller plans the plurality of flash memory chips so that the plurality of flash memory chips have at least one first super chip Block and at least one second superblock, and a plurality of sets of temporary codes generated during the process of writing a data into the at least one first superblock and assigning the at least one second superblock Check code.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 in this embodiment is particularly a portable memory device (for example: SD / MMC, CF, MS, XD standard memory card). The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory system is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the flash memory module 120 (Access).

Under typical conditions, the flash memory module 120 includes multiple flash memory chips, and each flash memory chip includes a plurality of blocks, and the controller (for example, through a microprocessor 112 Flash memory controller executing code 112C 110) The operations of copying, erasing, and merging data to the flash memory module 120 are copying, erasing, and merging data in units of blocks. In addition, a block can record a specific number of data pages (Page), in which the controller (for example, the memory controller 110 executing the code 112C through the microprocessor 112) writes to the flash memory module 120 The operation of data is written in units of data pages.

In practice, the flash memory controller 110 that executes the code 112C through the microprocessor 112 can use its own internal components to perform many control operations, such as: using the control logic 114 to control the flash memory module 120 Access operation (especially access operation of at least one block or at least one data page), using buffer memory 116 to perform required buffer processing, and using interface logic 118 to communicate with a host device.

On the other hand, in this embodiment, the control logic 114 includes a first codec 132 and a second codec 134. The first codec 132 is used to write to the flash memory. The data in one block of the memory module 120 is encoded to generate a corresponding error correction code. The error correction code generated by the first codec 132 is only based on writing to a data page. The content of the secondary sector (sector) is generated, and the error correction code generated is written into the data page together with the data content of the sector. In addition, the second codec 134 is a fault-tolerant disk array (RAID) codec, which is used to encode data written into multiple flash memory chips to generate corresponding check codes. Its operation will be detailed in the following.

In this embodiment, the flash memory module 120 is a three-dimensional NAND-type flash memory module. Please refer to FIG. 2, which is a three-dimensional NAND-type flash memory module. An example schematic, as shown in Figure 2. The three-dimensional NAND flash memory includes a plurality of floating gate transistors 202, which pass through multiple bit lines (only BL1 to BL3 are shown in the figure) and multiple characters. Lines (eg, WL0 ~ WL2, WL4 ~ WL6 as shown) constitute a three-dimensional NAND-type flash memory architecture. In Figure 2, using the top plane as an example, all floating transistors on the word line WL0 constitute at least one data page, and all floating transistors on the word line WL1 constitute at least one piece of information. Page, and all the floating transistors of the word line WL2 constitute at least one other information page ... and so on. In addition, depending on the flash memory writing method, the definition between the character line WL0 and the data page (logical data page) will be different. In detail, when using a single-level cell (Single-Level Cell (SLC), all floating gate transistors on the word line WL0 correspond to only a single logical data page; when using multi-level cell (MLC) writing, the word line All floating transistors on WL0 correspond to two, three, or four logical data pages. The situation where all floating transistors on word line WL0 correspond to three logical data pages can be called a three-layer type. A triple-level cell (TLC) architecture, and a situation where all floating transistor transistors on the word line WL0 correspond to four logical data pages can be referred to as a quad-level cell (QLC) architecture. Since a person having ordinary knowledge in the technical field should be able to understand the structure of the three-dimensional NAND-type flash memory and the relationship between the word lines and the data pages, the relevant details are not repeated here. In addition, in the operation of the flash memory controller 110, the "data page" is a minimum writing unit, and the "block" is a minimum erasing unit.

Please refer to FIG. 3, which is a conceptual diagram of the structure of the floating transistor 202. As shown in FIG. 3, the gate and floating gate of each floating transistor are gate all around ) To enhance channel sensing capabilities.

It should be noted that the illustrations in Figs. 2 and 3 are only examples of the stereo NAND flash memory and the floating transistor 202, and are not intended as limitations of the present invention. Those skilled in the art should be able to It is understood that there are other types of three-dimensional NAND flash memory, for example, some word lines can be connected to each other, etc., and the design of the floating transistor 202 can also be slightly changed.

As described in the prior art, in some three-dimensional NAND-type flash memories, a plurality of word lines are defined as a word line group, and the word line group will have a part of the control circuit in common, which will result in When data fails to write to the floating transistor on one of the character line groups (write failure), it will cause data on the floating transistor on the other character lines of the character line group to occur. error. In one embodiment, the character lines on the same plane are set as a character line group. Referring to FIG. 2, the character lines WL0 to WL2 are classified as the first character line group, and the character lines WL4 ~ WL6 will be classified as the second character line group ... and so on. Please refer to FIG. 4, which is a schematic diagram of multiple word line groups in a block. In FIG. 4, it is assumed that the block contains all floating transistor transistors on 192 word lines, and one word line The group contains 4 character lines. Therefore, the block system in Figure 4 contains 48 character line groups WL_G0 ~ WL_G47. In addition, the block is a three-level storage (TLC) area in the diagram. The block, that is, the floating transistor on each character line can be used to store the data of three data pages. As shown in Figure 4, taking the character line group WL_G0 as an example, it contains the floating on the character line WL0 The gate transistor can be used to store the low data page P0L, the middle data page P0M, and the high data page P0U. The floating gate transistor on the character line WL1 can be used to store the low data page P1L, the middle data page P1M, and the high data page P1U. Floating transistor on element line WL2 can be used to store low data page P2L, intermediate data page P2M and high data page P2U, and floating transistor on word line WL3 can be used to store low data page P3L, intermediate data page P3M And high profile page P3U. When the controller writes data to the data page of the character line group WL_G0, it sequentially writes data to the floating transistor in the character line WL0, WL1, WL2, and WL3, and it is assumed that the character line WL0 Both the data on WL1 and WL1 were successfully written, but when a writing error occurs when the data is written into the character line WL2, the original data that was successfully written on the character lines WL0 and WL1 will also cause an error.

In addition, in some cases, even if the data has been successfully written, in the subsequent reading, there may still be situations where reading or reading errors may occur, such as when the word line is open. As a result, data cannot be read. In addition, as mentioned earlier, as long as one character line breaks in a character line group, the data of the entire character line group will be incorrect. On the other hand, if two word lines in different word line groups are short-circuited, for example, the short-circuit of the word lines WL3 and WL4 in FIG. 4 will cause the two word line groups. The data on WL_G0 and WL_G1 cannot be read successfully.

As mentioned above, because the flash memory encounters the above-mentioned write failure, broken character lines, and short-circuited character lines during data writing and subsequent reading, the data of the entire character line group is incorrect. Therefore, in the following embodiments of the present invention, a method for accessing the flash memory module 120 that can surely solve the above problem is proposed, and only requires very few resources (that is, very little memory space). can be completed. The details are as follows.

Referring first to FIG. 5, FIG. 5 is a schematic diagram of the flash memory controller 110 writing data to the flash memory module 120. As shown in FIG. 5, the flash memory module 120 includes multiple channels (in this embodiment, two channels 510 and 520 are taken as an example), and each channel is in the flash memory controller 110. There are respective sequencers in each and each includes multiple flash memory chips, and in this embodiment, channel 510 includes flash memory chips 512 and 514, and channel 520 includes flash memory. Wafers 522, 524. In addition, one block in each of the flash memory chips 512, 514, 522, and 524 will be configured as a super block, and the flash memory controller 110 will divide the data into super blocks. Write in units. In this embodiment, the super block 530 includes a three-tier storage block of each of the flash memory chips 512, 514, 522, and 524, and the super block 540 includes each of the flash memory chips. A single layer storage block in 512, 514, 522, and 524. It should be noted that, in other embodiments of the present invention, the super block 530 may also be a four-layer storage block in each of the flash memory chips 512, 514, 522, and 524.

Please refer to FIGS. 5 and 6 at the same time. FIG. 6 is a schematic diagram of writing data to the super block 530 by the flash memory controller 110 according to a first embodiment of the present invention. In the following description, each A piece of data is written to a data page of the flash memory chips 512, 514, 522, 524, that is, the first piece of data is written to each of the flash memory chips 512, 514, 522, 524 The first data page P0, the second data will be written to the second data page P1, ... in each flash memory chip 512, 514, 522, 524, and the Nth data will be written to The N-th data page P (N-1) in each flash memory chip 512, 514, 522, 524. Referring to FIG. 6, when the flash memory controller 110 needs to write the first data into the super block 530, first, the first codec 132 encodes the first data to generate a corresponding error. Correct the code, and write the first data and the error correction code generated by the first codec 132 into the first data page P0 in each flash memory chip 512, 514, 522, 524 In detail, the first codec 132 encodes the first part of the first piece of data to generate an error correction code, and writes the first part of the data and its error correction code to the first of the flash memory chip 512 Data page P0; the first codec 132 encodes the second part of the first data to generate an error correction code, and writes the second part of the data and its error correction code to the first of the flash memory chip 514 Data page P0; the first codec 132 encodes the third part of the first data to generate an error correction code, and writes the third part of the data and its error correction code to the first part of the flash memory chip 522 A profile page P0; and the first The decoder 132 encodes the fourth part of the first data (the last part of the data) to generate an error correction code, and writes the fourth part of the data and its error correction code to the first data of the flash memory chip 524 Page P0. It should be noted that the operation required by the first codec 132 may be performed in a sector unit, where each data page is composed of multiple sectors. Before the first data and the error correction code generated by the first codec 132 are written to the super block 530, the second codec 134 in the flash memory controller 110 will The error correction code is encoded to generate a first set of check codes S0. In an embodiment, the second codec 134 may use a Reed Solomon (RS) encoding method or an exclusive-OR (XOR) operation to write to each flash memory. The data of the first data page P0 in the chips 512, 514, 522, and 524 are encoded to generate the first group of error correction codes S0. For example, but not as a limitation of the present invention, the second codec 134 may interact with each other on the first bit of the first data page P0 in the flash memory chip 512, 514, 522, and 524 together. Exclusive OR operation to obtain the first bit of the first set of check codes S0, and interact with each other on the second bit of the first data page P0 in the flash memory chip 512, 514, 522, 524 Exclusive OR operation to get the second bit of the first set of check codes S0 ... and so on.

The first check code S0 generated by the second codec 134 is used to generate data when the first data page P0 of one of the flash memory chips 512, 514, 522, or 524 Error correction is performed when an error occurs. For example, suppose that when the data of the first data page P0 in the flash memory chip 512 fails to correct with its own data (that is, the first codec cannot be used). 132 error correction code generated for correction), the second codec 134 can read all the data on the first data page P0 in the flash memory chip 514, 522, 524, plus the first set of corrections The check code S0 is used for error correction to determine the data of the first data page P0 in the flash memory chip 512.

In addition, the first set of check codes S0 generated by the second codec 134 is temporarily stored in the buffer memory 116 of the flash memory controller 110 first.

In addition, during the writing of the first data, the flash memory controller 110 performs a read check operation on the written data to determine whether the data is successfully written. When data is written incorrectly, the second codec 134 can directly use the first set of check codes S0 stored in the buffer memory 116 to correct the read data, and because the flash memory module 120 It is not possible to directly modify the written data. The corrected data (the first data after correction) can wait for a suitable subsequent time to be written into another super block together with other data in super block 530. . After the flash memory controller 110 determines that the first data has been successfully written to the first data page P0 in the flash memory chip 512, 514, 522, 524, the flash memory controller 110 will The first group of check codes S0 is moved from the buffer memory 116 to the super block 540.

Next, when the flash memory controller 110 needs to write the second piece of data into the super block 530, first, the first codec 132 encodes the second piece of data to generate corresponding error correction codes. The second data is written into the second data page P1 in each of the flash memory chips 512, 514, 522, and 524 together with the error correction code generated by the first codec 132. Before the second data and the error correction code generated by the first codec 132 are written to the super block 530, the second codec 134 in the flash memory controller 110 will The error correction code is encoded to generate a second set of check codes S1. In an embodiment, the second codec 134 may adopt a Reed-Solomon encoding method or a mutually exclusive OR operation to write the second one to each of the flash memory chips 512, 514, 522, and 524. The data on the data page P1 is encoded to generate a second set of error correction codes S1.

In addition, the second set of check codes S1 generated by the second codec 134 is temporarily stored in the buffer memory 116 of the flash memory controller 110 first.

Similarly, during the writing of the second data, the flash memory controller 110 also performs a read check operation on the written data to determine whether the data is successfully written. When the data is written incorrectly, the second codec 134 can directly use the second set of check codes S1 stored in the buffer memory 116 to correct the read data, and the corrected data (corrected The second data) can wait for a suitable subsequent time to be written into another super block together with other data in the super block 530. After the flash memory controller 110 determines that the second data has been successfully written to the second data page P1 in the flash memory chip 512, 514, 522, 524, the flash memory controller 110 will The second set of check codes S1 is moved from the buffer memory 116 to the super block 540.

It should be noted that when a writing error occurs during the writing of the second data, the data pages P1 and P0 belong to the same word line group WL_G0. Therefore, the flash memory chip 512, The data page P0 in 514, 522, 524 may also be damaged. For example, assuming that an error occurs in the data page P1 of the flash memory chip 514 during the data writing process, the data page P0 of the flash memory chip 514 that has been successfully written in the past may also fail. At this time, since the buffer memory 116 itself does not store the first group of check codes S0, the flash memory controller 110 reads the first group of check codes S0 from the super block 540 to check the self-super Correct the first data read in block 530.

Based on the same operation, the flash memory controller 110 continues to write the third data to the third data page P2 in the flash memory chips 512, 514, 522, and 524, and generates a corresponding third Group check code S2; and write the fourth piece of data into the fourth data page P3 in the flash memory chip 512, 514, 522, 524, and generate a corresponding fourth group check code S3, The data writing operation on the word line group WL_G0 is completed.

Then, similar to the above steps, the flash memory controller 110 writes the next 5 to 184 records into the flash memory chips 512, 514, 522, and 524, and the second codec 134 performs the fifth The ~ 184 pieces of data are encoded to generate the 5th to 183th sets of check codes S4 to S183, and the 5th to 183th sets of check codes S4 to S183 are stored in the super block 540.

For the 185th data, the flash memory controller 110 will only write the 185th data with the error correction code generated by the first codec 132 to the data in the flash memory chip 512, 514, 522 Page P184 without writing data to data page P184 in flash memory chip 524. Before the 185th data is written into the super block 530, the second codec 134 encodes the 185th data and its error correction code to generate the 185th set of check codes S184. Then, the flash memory controller 110 reads the first set of check codes S0, S8, S16, ..., S176 of each word line group WL_G0 ~ WL_G45 from the super block 540, and the second codec pair The check codes S0, S8, S16, ..., S176 and the check code S184 are mutually exclusive or calculated with each other to obtain a first set of final check codes SF0. Next, the flash memory controller 110 writes the 185th data to the data page P184 in the flash memory chip 512, 514, and 522, and writes the first set of final verification codes SF0 to the flash memory. Data sheet P184 in wafer 524. In an embodiment, the second codec 134 performs a mutually exclusive OR operation on the first bits in the check codes S0, S8, S16, ..., S184 to generate the first bit of the final check code SF0. Mutually exclusive OR operation on the second bit of the check codes S0, S8, S16, ..., S184 to generate the second bit of the final check code SF0 ... and so on, until the final calibration is completed The last bit of the check code SF0. In addition, the check code S184 may be stored in the super block 540.

For the 186th data, the flash memory controller 110 only writes the 186th data together with the error correction code generated by the first codec 132 to the data in the flash memory chip 512, 514, 522 Page P185 without writing data to data page P185 in flash memory chip 524. Before the 186th piece of data is written into the super block 530, the second codec 134 encodes the 186th piece of data and its error correction code to generate a 186th set of check codes S185. Next, the flash memory controller 110 reads the second set of check codes S1, S9, S17, ..., S177 of each word line group WL_G0 ~ WL_G45 from the super block 540, and the second codec pair The check codes S1, S9, S17, ..., S177, and the check code S185 are mutually exclusive or calculated with each other to obtain a second set of final check codes SF1. Next, the flash memory controller 110 writes the 186th data to the data page P185 in the flash memory chip 512, 514, and 522, and writes the second set of final check codes SF1 to the flash memory. Data sheet P185 in wafer 524. In an embodiment, the second codec 134 performs a mutually exclusive OR operation on the first bits in the check codes S1, S9, S17, ..., S185 to generate the first bit of the final check code SF1. Mutually exclusive OR operation is performed on the second bit of the check codes S1, S9, S17, ..., S185 to generate the second bit of the final check code SF1 ... and so on, until the final calibration is completed The last bit of the check code SF1. In addition, the check code S185 can be stored in the super block 540.

Based on similar operations, for the 187th to 192th data, the flash memory controller 110 writes the 187th to 192th data together with the error correction code generated by the first codec 132 to the flash memory chip 512 Data pages P186 ~ P191 in 514, 522; and the second codec 134 also generates the third to eight sets of final check codes SF2 to SF7 according to the similar operation described above, and performs the third to eight sets of final check codes The codes SF2 ~ SF7 are written into the data pages P186 ~ P191 in the flash memory chip 524, respectively.

The concept of generating the eight final check codes SF0 to SF7 based on the first to 192 sets of check codes S0 to S191 can be referred to the content shown in FIG. 7.

In this embodiment, the check code stored in the super block 540 is only a temporary check code, that is, the multiple sets of check codes S0 to S191 stored in the super block 540 are only written to the data. Only used when an error occurs during the process of superblock 530. Therefore, after the final check codes SF0 to SF7 are written to the super block 530, the multiple sets of check codes S0 to S191 stored in the super block 540 do not need to be used again. Therefore, in the subsequent super block 530 In the case where the data stored in the data is still valid, the flash memory controller 110 may erase or mark the content of the super block 540 as invalid.

It should be noted that, because the final check codes SF0 to SF7 are generated by the check codes S0 to S191, the final check codes SF0 to SF7 essentially carry each previous set of check codes S0 to S191 information. That is, in the subsequent reading operation, each set of check codes S0 ~ S191 can be obtained again according to the corresponding data page content (for example, reading the flash memory chip 512, 514, 522, 524). Get the check code S1) on the data page P1 of the data sheet. If an error occurs, you can also use the corresponding final check code SF0 ~ SF7 to correct it. For example, if a character line in the character line group WL_G0 is disconnected, for example, the character line corresponding to the data page P0 of the flash memory chip 514 is disconnected, the flash memory controller 110 can read The data in the other character line groups are used to regenerate the check codes S8, S16, ..., S184 and the final check code SF0 to regenerate the check code S0, and then use the check code S0 and self-flash memory. The content read from the data page P0 of the body chip 512, 522, 524 to regenerate the data of the data page P0 of the flash memory chip 514; the flash memory controller 110 reads the data in the other character line groups to Regenerate the check codes S9, S17, ..., S185 and the final check code SF1 to regenerate the check code S1, and then use the check code S1 and the data from the flash memory chip 512, 522, 524 The content read by the page P1 is used to regenerate the data of the data page P1 of the flash memory chip 514; and the data of the data pages P2 and P3 of the flash memory chip 514 are regenerated according to the similar operation described above. As described above, through the above operations, as long as multiple data lines are not disconnected in the super block 530, the data can be corrected and restored smoothly without the situation that the data cannot be repaired.

In addition, if the two data lines are short-circuited between the character line groups WL_G0 and WL_G1, such as the situation where the character lines corresponding to the data pages P3 and P4 of the flash memory chip 514 are short-circuited, it can also be detected through the previous paragraph. The mentioned method is to restore and correct the data in the character line groups WL_G0 and WL_G1, and the data cannot be repaired.

It should be noted that each of P0 ~ P191 shown in Figure 6 does not limit to three data pages, but may be two or four data pages.

In addition, in the embodiment shown in FIGS. 6 to 7, the final check codes SF0 to SF7 are generated by reading the check codes previously stored in the super block 540. However, the present invention does not This is limited. In another embodiment, during the generation process, the check code stored in the super block 540 may also be used for encoding together with the check code of the previous character line group. For example, the second codec 134 can encode the 9th data (the 9th data page P8 written in each flash memory chip 512, 514, 522, 524) and the first set of check code S0 to generate the 9th set The check code S8 is generated by encoding the 17th data (the 17th data page P16 written in each flash memory chip 512, 514, 522, 524) and the 9th set of check code S8. The 17th group of check codes S16, ..., for the 185th data (written to the 185th data page P184 in each flash memory chip 512, 514, 522, 524) and the 177th group of check codes S176 Encoding is performed together to generate the 185th group of check codes S184. In this way, since the check code S184 of the 185th group already carries the information of the previous check codes S0, S8, S16, ..., S176, the check code S184 of the 185th group can be directly used as the first final calibration. The check code SF0 is stored in the data page P184 of the super block 530 corresponding to the flash memory chip 524. Similarly, the final check codes SF1 to SF7 can also be generated through the above methods, and stored in the data pages P185 to P191 of the super block 530 corresponding to the flash memory chip 524, respectively.

In addition, in FIG. 5, the super block 530 includes only one three-tier storage block in each of the flash memory chips 512, 514, 522, and 524. However, in other embodiments, for example, the flash In the case where the memory module 120 is configured as two block planes, the super block 530 may include two three-tier storage areas in each of the flash memory chips 512, 514, 522, and 524. Blocks, and the two three-layer storage blocks in each flash memory chip 512, 514, 522, 524 are controlled by different chip enable signals. Similarly, the super block 540 may also include two single-layer storage blocks in each of the flash memory chips 512, 514, 522, and 524.

Please refer to FIG. 8, which is a flowchart of a method for accessing a flash memory module according to an embodiment of the present invention. With reference to the content disclosed above, the process is as follows:

Step 800: The process starts.

Step 802: Plan a plurality of flash memory chips so that the plurality of flash memory chips have at least a first super block and at least a second super block.

Step 804: Write a piece of data into the at least one superblock.

Step 806: encode the data to generate multiple sets of temporary check codes, and store the multiple sets of temporary check codes to the at least one second superblock.

Step 808: Generate a final check code according to the plurality of sets of temporary check codes.

Step 810: Write the final check code to the at least one first super block.

Step 812: Erase or mark the at least one second superblock as invalid.

Step 814: The process ends.

The present invention is briefly summarized. In the embodiment of the method for accessing a flash memory module of the present invention, the second codec sequentially encodes multiple pieces of data written into the multi-level storage superblock. The temporary check code generated is stored in the single-level storage super block, and then the temporary check code stored in the single-level storage super block is read to generate a low amount of data. The final check code, and store the final check code in the multi-level storage super block. Through the above access methods, in addition to correcting data writing errors, broken character lines, and short-circuited data lines due to character line shorts, it can also greatly reduce the amount of buffer memory in the flash memory controller. The capacity requirement, and the flash memory module does not need to waste too much space to store the check code, so the cost of the flash memory controller and the use efficiency of the flash memory module can be greatly reduced. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

100‧‧‧memory device

110‧‧‧Flash Memory Controller

112‧‧‧Microprocessor

112C‧‧‧Code

112M‧‧‧Read Only Memory

114‧‧‧Control logic

116‧‧‧Buffer memory

118‧‧‧ Interface Logic

120‧‧‧Flash Memory Module

132‧‧‧The first codec

134‧‧‧Second codec

202‧‧‧Floating Gate Transistor

510, 520‧‧‧ channels

512, 514, 516, 518‧‧‧Flash memory chips

530, 540‧‧‧ Super Block

800 ~ 814‧‧‧step

B1 ~ B3‧‧‧Bit line

WL0 ~ WL47‧‧‧Character line

WL_G0 ~ WL_G47‧‧‧Character line group

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention. FIG. 2 is an exemplary diagram of a three-dimensional NAND flash memory. Figure 3 is a conceptual diagram of the floating gate transistor structure. FIG. 4 is a schematic diagram of multiple word line groups in a block. FIG. 5 is a schematic diagram of a flash memory controller writing data to a flash memory module and a super block. FIG. 6 is a schematic diagram of writing data to a super block by a flash memory controller according to a first embodiment of the present invention. FIG. 7 is a schematic diagram of generating 8 sets of final check codes SF0 to SF7 according to the 1 to 192 sets of check codes S0 to S191. FIG. 8 is a flowchart of a method for accessing a flash memory module according to an embodiment of the present invention.

Claims (24)

A method for accessing a flash memory module, wherein the flash memory module is a 3D NAND-type flash module, and the flash memory module includes a plurality of Flash memory chip, each flash memory chip is a three-dimensional flash memory chip and contains multiple blocks, the multiple blocks include multiple multi-layer storage blocks and multiple single-layer storage Block, each block contains multiple data pages; each block contains multiple word lines and bit lines that are located on multiple different planes to control multiple floating gate transistors, and each word The floating gate transistor on the element line constitutes at least one data page of the plurality of data pages; and the method includes: encoding a data to generate at least one set of check codes, wherein the data is to be written into the data In a first super block of the plurality of flash memory chips, the first super block includes a multi-layer storage of each of the plurality of flash memory chips. Block; write this data to the first super area ; And writing the at least one set of check codes into a second super block, wherein the second super block includes a single layer of each of the plurality of flash memory chips Block; each of the first super block and the second super block includes a plurality of blocks respectively located in the plurality of flash memory chips. The method according to item 1 of the scope of patent application, further comprising: before the data is written into the first superblock, the data is encoded to generate the at least one set of check codes, and the at least one A set of check codes is stored in a buffer memory of a flash memory controller; and when a data write error occurs, the at least one set of check codes stored in the buffer memory is directly used To correct the information. The method according to item 1 of the scope of patent application, further comprising: in the process of writing the data to the at least one first super block: reading the data from the first super block has been written to Part of the content of the at least one first super block; when an uncorrectable error occurs during the reading of part of the content, read at least a part of the check code from the second super block and use The at least part of the check code is used to correct errors in the read data. The method according to item 1 of the scope of patent application, wherein the at least one set of check codes is a temporary check code, and the method further comprises: reading the at least one set of calibration codes from the second super block. Check code, and generate a set of final check codes according to the at least one set of check codes; write the set of final check codes into the first superblock. The method according to item 1 of the scope of patent application, wherein the step of encoding the data to generate the at least one set of check codes includes: sequentially encoding the first to N records to generate the first to N groups A check code; and the step of writing the data to the first super block includes: writing the first to N pieces of data to the first super block respectively corresponding to the plurality of flashes The first to N data pages of the memory chip; and the steps of writing the set of verification codes to the second superblock include: writing the first to N sets of verification codes to the second Superblock. The method according to item 1 of the scope of patent application, wherein the at least one set of check codes is a temporary check code, and the method further includes: reading the first to N from the second super block Set of check codes, and generate multiple sets of final check codes according to the first to N sets of check codes; write the multiple sets of final check codes into the first superblock. The method as described in item 6 of the scope of patent application, wherein a plurality of word lines located on the same plane in each block constitute a word line group, and the plurality of sets of final check codes are written to the first The step of a super block includes: writing the plurality of sets of final check codes to the data pages included in the first two super block corresponding to the last two word line groups of the plurality of flash memory chips. in. The method according to item 7 of the scope of the patent application, wherein the P ~ N pieces of data are also written into the first super block corresponding to the last two word line groups of the plurality of flash memory chips In the included information page, N is a positive integer greater than 1, and P is a positive integer greater than 1 and less than N. The method described in item 1 of the patent application scope further includes: after writing the final check code to the first super block, the data stored in the first super block is still If it is valid, the content of the second superblock is erased or marked as invalid. The method according to item 1 of the scope of patent application, wherein the multilayer storage block is a triple-level cell (TLC) block or a quad-level cell (QLC) block . A flash memory controller is used to access a flash memory module, wherein the flash memory module is a 3D NAND-type flash memory. ) Module, the flash memory module includes a plurality of flash memory chips, each flash memory chip is a three-dimensional flash memory chip and includes a plurality of blocks, and the plurality of blocks include Multiple multi-level storage blocks and multiple single-level storage blocks, each block contains multiple data pages; each block contains multiple character lines and bits located on multiple different planes, respectively Multiple floating transistor transistors controlled by lines, and the floating transistor transistors on each character line constitute at least one of the plurality of data pages; and the flash memory controller includes: a memory To store a code; a microprocessor to execute the code to control access to the flash memory module; and a codec; the codec encodes data to generate At least one set of check codes, where the data is to be written to In a first super block of the plurality of flash memory chips, the first super block includes a multi-layer storage of each of the plurality of flash memory chips. Block; and the microprocessor writes the data to the first super block, and writes the at least one set of check codes to a second super block, where the second super block includes A single-layer storage block of each flash memory chip in the plurality of flash memory chips; wherein each of the first super block and the second super block includes the plurality of flash memory chips, respectively. Multiple blocks in a flash memory chip. The flash memory controller according to item 11 of the scope of patent application, wherein before the data is written into the first superblock, the codec first encodes the data to generate the at least one set of checks Code, and stores the set of check codes in a buffer memory of a flash memory controller; and when a write error occurs in the data, the codec directly uses the stored code in the buffer memory The at least one set of check codes to correct the data. The flash memory controller according to item 11 of the scope of patent application, wherein in the process of writing the data to the at least one first super block: the microprocessor reads the data from the first super block Part of the data has been written into the at least one first superblock; and when an uncorrectable error occurs during the reading of the part of the data, the microprocessor reads from the second superblock At least a part of the check code, and the codec uses the at least part of the check code to correct errors in the read data. The flash memory controller according to item 11 of the scope of patent application, wherein the at least one set of check codes is a temporary check code, and the microprocessor reads the at least one from the second super block. A set of check codes, and the codec generates a set of final check codes according to the at least one set of check codes, and writes the set of final check codes into the first superblock. The flash memory controller according to item 11 of the scope of patent application, wherein the codec sequentially encodes the first to N records to generate the first to N sets of check codes, and the first to N N pieces of data are respectively written into the first to N data pages of the first super block corresponding to the plurality of flash memory chips; and the microprocessor writes the first to N sets of check codes Into the second superblock. The flash memory controller according to item 11 of the scope of patent application, wherein the at least one set of check codes is a temporary check code, and the microprocessor reads the first check code from the second super block. 1 ~ N sets of check codes, and generate multiple sets of final check codes according to the 1 ~ N sets of check codes, and then write the multiple sets of final check codes into the first super block. The flash memory controller according to item 16 of the scope of patent application, wherein a plurality of word lines located on the same plane in each block constitute a word line group, and the microprocessor sets the plurality of groups The final check code is written into the data page included in the first super block corresponding to the last two word line groups of the plurality of flash memory chips. The flash memory controller according to item 17 of the scope of the patent application, wherein the P ~ N records are also written into the first two super blocks corresponding to the last two of the plurality of flash memory chips. In the data pages included in the character line group, N is a positive integer greater than 1, and P is a positive integer greater than 1 and less than N. The flash memory controller according to item 11 of the scope of patent application, wherein after writing the set of final check codes to the first super block, the data stored in the first super block If it is still valid, the microprocessor erases or marks the content of the second superblock as invalid. The flash memory controller according to item 11 of the scope of patent application, wherein the multi-layer storage block is a triple-level cell (TLC) block or a quad-level cell , QLC) block. A memory device includes: a flash memory module, wherein the flash memory module is a 3D NAND-type flash module, and the flash memory module includes Multiple flash memory chips, each flash memory chip is a three-dimensional flash memory chip and contains multiple blocks, the multiple blocks include multiple multi-layer storage blocks and multiple Layered storage block, each block contains multiple data pages; each block contains multiple word lines and bit lines respectively located on multiple different planes to control multiple floating gate transistors, and The floating transistor on each character line constitutes at least one data page of the plurality of data pages; and a flash memory controller for accessing the flash memory module; When a host writes a request to write data into the flash memory module, the flash memory controller encodes the data to generate at least one set of check codes, and writes the data. Into a first super area of the plurality of flash memory chips (super block), wherein the first super block includes a multi-layer storage block of each of the plurality of flash memory chips; and writing the at least one set of check codes To a second super block, wherein the second super block includes a single-layer storage block of each of the plurality of flash memory chips; wherein the first super block And each of the second super blocks includes a plurality of blocks respectively located in the plurality of flash memory chips. The memory device according to item 21 of the scope of patent application, wherein before the data is written into the first superblock, the flash memory controller encodes the data to generate the at least one check code. And store the set of check codes into a buffer memory of the flash memory controller; and when a data write error occurs, the flash memory controller directly uses the stored in the buffer memory The at least one set of check codes in the body to correct the data. The memory device according to item 21 of the scope of patent application, wherein in the process of writing the data to the at least one first super block: the flash memory controller reads the data from the first super block Part of the content that has been written into the at least one first superblock; and when an uncorrectable error occurs during the reading of the partial content of the data, the flash memory controller starts from the second superblock Read at least a part of the check code, and use the at least part of the check code to correct errors in the read data. The memory device according to item 21 of the patent application scope, wherein the at least one set of check codes is a temporary check code, and the flash memory controller reads the at least one from the second super block. A set of check codes, and generate a set of final check codes according to the at least one set of check codes, and write the set of final check codes into the first superblock.