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TWI562159B - Integrated circuit and method for establishing scah test architecture in integrated circuit - Google Patents

Integrated circuit and method for establishing scah test architecture in integrated circuit

Info

Publication number
TWI562159B
TWI562159B TW104113475A TW104113475A TWI562159B TW I562159 B TWI562159 B TW I562159B TW 104113475 A TW104113475 A TW 104113475A TW 104113475 A TW104113475 A TW 104113475A TW I562159 B TWI562159 B TW I562159B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
scah
establishing
test architecture
architecture
Prior art date
Application number
TW104113475A
Other languages
Chinese (zh)
Other versions
TW201633325A (en
Inventor
Jianguo Ren
Original Assignee
Mediatek Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mediatek Singapore Pte Ltd filed Critical Mediatek Singapore Pte Ltd
Publication of TW201633325A publication Critical patent/TW201633325A/en
Application granted granted Critical
Publication of TWI562159B publication Critical patent/TWI562159B/en

Links

TW104113475A 2015-03-03 2015-04-28 Integrated circuit and method for establishing scah test architecture in integrated circuit TWI562159B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510093374.7A CN105988080A (en) 2015-03-03 2015-03-03 Integrated circuit and electronic device, and method for establishing scanning test architecture

Publications (2)

Publication Number Publication Date
TW201633325A TW201633325A (en) 2016-09-16
TWI562159B true TWI562159B (en) 2016-12-11

Family

ID=57038095

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104113475A TWI562159B (en) 2015-03-03 2015-04-28 Integrated circuit and method for establishing scah test architecture in integrated circuit

Country Status (2)

Country Link
CN (1) CN105988080A (en)
TW (1) TWI562159B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI697773B (en) * 2019-01-09 2020-07-01 瑞昱半導體股份有限公司 Circuit testing system and circuit testing method
CN112305404B (en) * 2020-09-29 2022-11-08 上海兆芯集成电路有限公司 Core Partition Circuits and Test Sets

Citations (10)

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Publication number Priority date Publication date Assignee Title
US7823034B2 (en) * 2007-04-13 2010-10-26 Synopsys, Inc. Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit
US7831876B2 (en) * 2007-10-23 2010-11-09 Lsi Corporation Testing a circuit with compressed scan chain subsets
US8566658B2 (en) * 2011-03-25 2013-10-22 Lsi Corporation Low-power and area-efficient scan cell for integrated circuit testing
US8650524B1 (en) * 2012-11-09 2014-02-11 Cadence Design Systems, Inc. Method and apparatus for low-pin count testing of integrated circuits
US20140101501A1 (en) * 2012-10-05 2014-04-10 Lsi Corporation Scan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testing
US20140143621A1 (en) * 2012-11-21 2014-05-22 Lsi Corporation Scan circuitry for testing input and output functional paths of an integrated circuit
US20140143623A1 (en) * 2012-11-20 2014-05-22 Syntest Technologies, Inc. Method and apparatus for low-pin-count scan compression
US8904256B1 (en) * 2012-11-09 2014-12-02 Cadence Design Systems, Inc. Method and apparatus for low-pin count testing of integrated circuits
US20140359386A1 (en) * 2010-09-10 2014-12-04 Advanced Micro Devices, Inc. Scan or jtag controllable capture clock generation
US20150036783A1 (en) * 2013-07-30 2015-02-05 Industrial Technology Research Institute Device and method for generating input control signals of a serialized compressed scan circuit

Family Cites Families (7)

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Publication number Priority date Publication date Assignee Title
JP2004093351A (en) * 2002-08-30 2004-03-25 Matsushita Electric Ind Co Ltd Built-in self-test circuit
CN1548974A (en) * 2003-05-16 2004-11-24 中国科学院计算技术研究所 VLSI Test Channel Compression Method and Circuit
US7707467B2 (en) * 2007-02-23 2010-04-27 Micron Technology, Inc. Input/output compression and pin reduction in an integrated circuit
CN101226228B (en) * 2008-02-01 2010-06-02 清华大学 A deterministic self-test test data compression device and method
US20090265596A1 (en) * 2008-04-22 2009-10-22 Mediatek Inc. Semiconductor devices, integrated circuit packages and testing methods thereof
CN102305912B (en) * 2011-07-29 2014-06-04 清华大学 Low power consumption integrated circuit testing device with compressible data and method using same
EP2608039B1 (en) * 2011-12-22 2014-05-21 Nxp B.V. Secure low pin count scan

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7823034B2 (en) * 2007-04-13 2010-10-26 Synopsys, Inc. Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit
US7831876B2 (en) * 2007-10-23 2010-11-09 Lsi Corporation Testing a circuit with compressed scan chain subsets
US20140359386A1 (en) * 2010-09-10 2014-12-04 Advanced Micro Devices, Inc. Scan or jtag controllable capture clock generation
US8566658B2 (en) * 2011-03-25 2013-10-22 Lsi Corporation Low-power and area-efficient scan cell for integrated circuit testing
US20140101501A1 (en) * 2012-10-05 2014-04-10 Lsi Corporation Scan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testing
US8650524B1 (en) * 2012-11-09 2014-02-11 Cadence Design Systems, Inc. Method and apparatus for low-pin count testing of integrated circuits
US8904256B1 (en) * 2012-11-09 2014-12-02 Cadence Design Systems, Inc. Method and apparatus for low-pin count testing of integrated circuits
US20140143623A1 (en) * 2012-11-20 2014-05-22 Syntest Technologies, Inc. Method and apparatus for low-pin-count scan compression
US20140143621A1 (en) * 2012-11-21 2014-05-22 Lsi Corporation Scan circuitry for testing input and output functional paths of an integrated circuit
US20150036783A1 (en) * 2013-07-30 2015-02-05 Industrial Technology Research Institute Device and method for generating input control signals of a serialized compressed scan circuit

Also Published As

Publication number Publication date
TW201633325A (en) 2016-09-16
CN105988080A (en) 2016-10-05

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MM4A Annulment or lapse of patent due to non-payment of fees