JP2004093351A - Built-in self-test circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate the narrowing-down of suspected scan paths and failure observation timing which are required at failure diagnosis in a semiconductor integrated circuit using a built-in self-test circuit. <P>SOLUTION: A test pattern is supplied to a plurality of scan paths 21-29 from a pattern generator 1. Output responses are stored in output response compressors. By comparing stored values with expected values, failures are detected in this BIST type built-in self-test circuit in the semiconductor integrated circuit. The output response compressors are constituted of a plurality of output response compressors 4a-4c for storing the output responses from the plurality of scan paths 21-29 in a state divided into a plurality of groups. By a scan path electing circuit 3 interposed between the suspected scan paths and the output response compressors 4a-4c, the state of connection between the plurality of scan paths and the plurality of output response compressors is switched. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a built-in self-test circuit for a semiconductor integrated circuit.
[0002]
[Prior art]
In the inspection of an LSI, application of a test sequence and observation of an output response are performed using a tester. In recent years, the scale and speed of LSIs have been increasing, and problems such as the operating frequency of the tester cannot keep up with the operating frequency of the LSI and the problem that the test sequence data is too large to be stored in the tester memory and so forth have arisen. ing. Accordingly, a built-in self-test (BIST: Built-in Self Test) method has been proposed as one of the testability design methods for avoiding these problems.
[0003]
Built-in self-test means that the test circuit is built in the LSI, the test sequence is generated inside the LSI, and the output response is compared with the expected value. ("Computer Science Press", 1990, "Digital Systems Testing and Testable DESIGN", Chapter 11, Built-In Self-Test (Build-In Self-Test)). reference).
[0004]
In the inspection of a semiconductor integrated circuit with a built-in self-inspection circuit, the generation of the inspection sequence and the observation of the output response are performed inside the circuit, so that the inspection can be performed at the circuit's original operating frequency. There is an advantage that inspection can be performed by observing only the pass / fail judgment signal.
[0005]
In the built-in self-test circuit, the output of the scan path to be inspected is connected to the output response compressor, and the output response for each pattern supplied to the scan path from the pattern generator is compressed by the output response compressor. You. The pass / fail judgment is made by comparing the value remaining in the output response compressor after application of all the patterns and the expected value with the expected value comparator based on the timing signal from the clock counter. In this case, the values stored in the output response compressor are obtained by compressing the output responses of a plurality of scan paths for all patterns.
[0006]
[Problems to be solved by the invention]
When diagnosing a failure and identifying the location of the failure, it is necessary to obtain information on which scan path the effect of the failure was observed on, and which pattern to apply the effect of the failure on. It is.
[0007]
However, in the above-mentioned conventional method, the output response compressor is single, and the output responses of a plurality of scan paths for all patterns are compressed and stored in a single output response compressor. It has become. Therefore, it is difficult to obtain information on which scan path corresponds to the failure and which pattern corresponds to the failure.
[0008]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a built-in self-inspection circuit capable of narrowing down a scan path or a pattern corresponding to a failure.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention takes the following measures. As a premise, the system includes a plurality of scan paths for performing an LSI test, a pattern generator for supplying a test pattern to the plurality of scan paths, and an output response compressor for storing an output response from the scan path. . In the built-in self-inspection circuit having such a configuration, the output response compressor is divided into a plurality of output response compressors that store output responses from the plurality of scan paths in several groups. Further, a scan path selection circuit for switching a connection state between the plurality of scan paths and the plurality of output response compressors is provided.
[0010]
The operation of this configuration is as follows. A test pattern is applied to a plurality of scan paths from the pattern generator, and output responses from the plurality of scan paths are divided into groups and stored in a state compressed to a plurality of output response compressors. Then, the value stored in the output response compressor is compared with the expected value to discriminate between a value that matches the expected value and a value that does not match. If the match with the expected value is not realized in any of the output response compressors, it is considered that the effect of the failure has occurred in any of the plurality of scan paths connected to the output response compressor. Such a scan path is a suspected scan path. Although there may actually be one or more problematic scan paths, there are a plurality of suspected scan paths as candidates. By controlling the scan path selection circuit, the output response compressor to which the suspected scan path is to be connected is switched and distributed to individual output response compressors. Prior to this switch, the suspected scan paths were connected to the same output response compressor. The output response compressor connected to the plurality of suspected scan paths is switched by the scan path selection circuit. It is switched so that it can be distributed to different output response compressors. That is, the output responses of the plurality of suspected scan paths can be observed by different output response compressors. Thereby, the plurality of suspected scan paths can be separately observed in an independent state without affecting each other. By performing the expected value comparison again in the plurality of output response compressors, the suspected scan path can be further narrowed down. Therefore, it is possible to easily distinguish a scan path corresponding to a failure from a normal scan path and easily identify which scan path is affected by the failure.
[0011]
As another solution, the present invention takes the following measures. That is, the above configuration further includes a timing signal generator that controls the scan path selection circuit and generates a timing signal for switching a connection state between the scan path and the output response compressor. A clock counter can be used as the timing signal generator.
[0012]
The operation of this configuration is as follows. The timing signal from the timing signal generator is supplied to the scan path selection circuit, and each time a test pattern is applied, the output response compressor to which each scan path is to be connected is automatically switched, and the output response during the test is individually separated. Store it in the output response compressor. As a result, the value of the output response compressor during the inspection is stored, and the output response for each test pattern can be observed. Therefore, the failure location can be estimated by specifying the timing at which the effect of the failure appears. That is, it is possible to narrow down the failure detection patterns.
[0013]
As another solution, the present invention takes the following measures. A plurality of scan paths for performing an LSI test; a pattern generator for supplying a test pattern to the plurality of scan paths; an output response compressor for storing output responses from the plurality of scan paths; A timing signal generator for generating a pass / fail judgment timing signal for a value stored by the device and a programmable number of clock cycles for generating the timing signal.
[0014]
The operation of this configuration is as follows. When the timing signal generator generates a pass / fail judgment timing signal, the value of the test result stored in the output response compressor is compared with an expected value to make a pass / fail judgment. In this case, the timing signal generator is configured as a timing signal generator that can program the number of clock cycles for generating the timing signal. Therefore, by performing the inspection while changing the timing of performing the pass / fail determination, the pass / fail determination can be performed for the entire test by dividing the entire test into a plurality of timings, and the output response for each of a plurality of patterns can be tested. . That is, the suspected pattern can be narrowed down while discriminating between the pattern in which the influence of the failure appears and the pattern showing the normal response.
[0015]
As another solution, the present invention takes the following measures. A plurality of scan paths for performing an LSI test; a pattern generator for supplying a test pattern to the plurality of scan paths; an output response compressor for storing output responses from the plurality of scan paths; And a temporary register connected to the output side of the compressor and operating on a different clock cycle from the output response compressor.
[0016]
The operation of this configuration is as follows. The temporary register periodically stores a value during the operation of the output response compressor. This stored value can be observed regardless of the operation of the output response compressor. That is, it is possible to narrow down the failure detection patterns. Furthermore, since the value in the middle can be observed without temporarily stopping the operation of the output response compressor, the timing at which the influence of the failure appears can be narrowed down. In this case, even when the output response compressor is operating, the contents of the temporary register are not overwritten until the next data storage cycle, and the value can be easily observed. As a result, the fault diagnosis can be executed at high speed.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a built-in self-test circuit according to the present invention will be described in detail with reference to the drawings.
[0018]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a built-in self-test circuit according to the first embodiment (corresponding to claim 1) of the present invention. In FIG. 1, 1 is a pattern generator, 2 is a circuit under test, 2 _i (I = 1, 2,..., 9) are a plurality of scan paths in the circuit under test 2, 3 is a scan path selection circuit, and 4a, 4b, 4c are output response compressors. The scan path selection circuit 3 includes a plurality of selectors M _i (I = 1, 2,... 9), and each selector M _i Is the scan path 2 connected to the input based on the selection control signal. _i And outputs the selected one. Each of the output response compressors 4a, 4b, and 4c is configured by a register called a MISR (Multiple-Input Signature Register). 9 scan paths 2 _i (I = 1, 2,..., 9) are stored in three output response compressors 4a, 4b, 4c in a state of being divided into three groups. Then, the combination of the components of the group is repeated by the scan path selection circuit 3.
[0019]
The first selector M1 in the scan path selection circuit 3 selects one of the scan paths 21, 24, and 27 and outputs the selected one to the first output response compressor 4a. The second selector M2 selects one of the scan paths 22, 25, and 28 and outputs it to the first output response compressor 4a. The third selector M3 selects one of the scan paths 23, 26, and 29 and outputs the selected scan path to the first output response compressor 4a. The fourth selector M4 selects any one of the scan paths 21, 24, 27 and outputs it to the second output response compressor 4b. The fifth selector M5 selects one of the scan paths 22, 25, and 28 and outputs the selected one to the second output response compressor 4b. The sixth selector M6 selects any one of the scan paths 23, 26, and 29 and outputs the selected one to the second output response compressor 4b. The seventh selector M7 selects any one of the scan paths 21, 24, 27 and outputs it to the third output response compressor 4c. The eighth selector M8 selects one of the scan paths 22, 25, and 28 and outputs it to the third output response compressor 4c. The ninth selector M9 selects any one of the scan paths 23, 26, and 29 and outputs it to the third output response compressor 4c.
[0020]
FIG. 2 shows the relationship between the selection control signals S1 and S2 of the first selector M1 in the scan path selection circuit 3 of FIG. 1 and the selected scan path. AND gates A11, A12, A13 for connecting scan paths 21, 24, 27 and selection control signals S1, S2 to inputs, and inverter I11 for logically inverting selection control signals S1, S2 and inputting them to AND gates A11, A12, An I12 and an OR gate B11 for calculating the logical sum of the outputs of the AND gates A11, A12, and A13. When the input combination of the selection control signals S1 and S2 is (0, 0) and (0, 1), the scan path 21 is selected. When the input combination is (1, 0), the scan path 24 is selected. In the case of ()), the scan path 27 is selected. By switching the selection control signals S1 and S2 in this way, the scan path connected to the first output response compressor 4a is changed. The second to ninth selectors M2 to M9 also have a circuit configuration based on the same concept.
[0021]
Now, in the state of FIG. 1, the scan paths 21, 22, and 23 are sent to the first output response compressor 4a, and the scan paths 24, 25, and 26 are sent to the second output response compressor 4b by the scan path selection circuit 3. , Scan paths 27, 28 and 29 are respectively connected to the third output response compressor 4c.
[0022]
All scan paths 2 in the circuit under test 2 from the pattern generator 1 _i A pattern is applied to (i = 1, 2,... 9). Next, the value stored in the first output response compressor 4a is compared with the expected value, the value stored in the second output response compressor 4b is compared with the expected value, and the third output response compression is performed. The value stored in the unit 4c is compared with the expected value. As a result, it is possible to distinguish between those that match the expected value and those that do not. Although the expected value comparator is not shown, it is assumed that the expected value comparator is connected to each of the output response compressors 4a, 4b, 4c.
[0023]
Here, it is assumed that the value of the first output response compressor 4a does not match the expected value, and the values of the second output response compressors 4b and 4c match. In this case, it can be seen that the effect of the failure appears on any of the scan paths 21, 22, and 23 connected to the first output response compressor 4a. However, this alone cannot identify whether the failure is in the scan path 21, the scan path 22, or the scan path 23. These three scan paths 21, 22, and 23 are suspect scan paths.
[0024]
Therefore, a mismatch occurs in the expected value comparison in the first output response compressor 4a, and the scan path selection is performed based on the information that the suspected scan path connected at that time is the scan paths 21, 22, 23. In the circuit 3, the selection control signal is switched so that the suspected scan paths 21, 22, and 23 are separately connected to the first, second, and third output response compressors 4a, 4b, and 4c, respectively. Perform switching.
[0025]
FIG. 3 is a diagram showing a circuit state after the connection of the scan path is switched. In FIG. 3, the suspected scan path 21 is connected to the first output response compressor 4a, the suspected scan path 22 is connected to the second output response compressor 4b, and the suspected scan path 23 is connected to the third output response compressor 4c. It has been switched. That is, the three suspicious scan paths 21, 22, and 23 which may correspond to the failure are connected and switched to the output response compressors 4a, 4b, and 4c which are different from each other. Accordingly, each of the suspected scan paths 21, 22, and 23 can be independently observed without affecting the output response compressor to which another scan path is connected.
[0026]
As described above, according to the present embodiment, when there are a plurality of suspected scan paths, by switching the selection control signal of the scan path selection circuit, each suspected scan path is divided and connected to a separate output response compressor. It is possible to easily identify which suspected scan path is affected by the failure.
[0027]
(Embodiment 2)
FIG. 4 is a block diagram showing a configuration of a built-in self-test circuit according to a second embodiment (corresponding to claim 2) of the present invention. In FIG. 4, reference numeral 5 denotes a 2-bit clock counter. The output of the clock counter 5 is a selection control signal for the scan path selection circuit 3. The connection relationship between the scan path 2 and the output response compressor 4 is switched according to the output of the clock counter 5. The clock counter 5 is an example of the timing signal generator according to claim 2. Other configurations are the same as those in FIG. 1 in the first embodiment, and therefore, the same portions are denoted by the same reference numerals and description thereof will be omitted.
[0028]
FIG. 5 is a circuit diagram showing the connection relationship between the first, fourth, and seventh selectors M1, M4, and M7 of the scan path selection circuit 3 and the 2-bit clock counter 5. The outputs S1 and S2 of the clock counter 5 change as (S1, S2) = (0, 0), (0, 1), (1, 0), (1, 1) every time a clock is input.
[0029]
In the first cycle, the output (S1, S2) of the clock counter 5 is (0, 1). At this time, in the first selector M1, only the AND gate A11 conducts, and the scan path 21 is connected to the first output response compressor 4a. In the fourth selector M4, only the AND gate A41 becomes conductive, and the scan path 27 is connected to the second output response compressor 4b. In the seventh selector M7, only the AND gate A71 becomes conductive, and the scan path 24 is connected to the third output response compressor 4c.
[0030]
In the second cycle, the output (S1, S2) of the clock counter 5 is (1, 0). At this time, in the first selector M1, only the AND gate A12 conducts, and the scan path 24 is connected to the first output response compressor 4a. In the fourth selector M4, only the AND gate A42 becomes conductive, and the scan path 21 is connected to the second output response compressor 4b. In the seventh selector M7, only the AND gate A72 is turned on, and the scan path 27 is connected to the third output response compressor 4c.
[0031]
In the third cycle, the output (S1, S2) of the clock counter 5 is (1, 1). At this time, in the first selector M1, only the AND gate A13 conducts, and the scan path 27 is connected to the first output response compressor 4a. In the fourth selector M4, only the AND gate A43 becomes conductive, and the scan path 24 is connected to the second output response compressor 4b. In the seventh selector M7, only the AND gate A73 is turned on, and the scan path 21 is connected to the third output response compressor 4c.
[0032]
In the process of transitioning from the first cycle to the third cycle via the second cycle, the connection destination of the scan path 21 is the first output response compressor 4a → the second output response compressor 4b → the second output response compressor 4b. 3 and the output response compressor 4c. Similarly, the connection destination of the scan path 24 changes in the order of the third output response compressor 4c → the first output response compressor 4a → the second output response compressor 4b. Similarly, the connection destination of the scan path 27 changes in the order of the second output response compressor 4b → the third output response compressor 4c → the first output response compressor 4a.
[0033]
As described above, according to the present embodiment, the connection relationship between the plurality of scan paths and the plurality of output response compressors is switched according to the selection control signal from the clock counter, and the scan path to be inspected is automatically set for each time. And switched to separate output response compressors. As a result, it is possible to observe the output response for each test pattern application, and it is possible to easily estimate the location of the failure and the pattern by specifying the timing at which the effect of the failure appears.
[0034]
(Embodiment 3)
FIG. 6 is a block diagram showing a configuration of a built-in self-test circuit according to the third embodiment (corresponding to claim 3) of the present invention. In FIG. 6, 1 is a pattern generator, 2 is a circuit under test, 4 is an output response compressor, 6 is an expected value comparator, 7 is a timing signal generator, 8 is a 2-bit clock counter, and 9 is a 4-bit clock counter. It is a decoder. The circuit under test 2 includes a plurality of scan paths as in the case of the first embodiment.
[0035]
The timing signal generator 7 includes a clock counter 8, a decoder 9, AND gates G1 to G4, and an OR gate G5. In the clock counter 8, the number of applied clocks is counted, and each digit of the 4-bit output is sequentially increased. In the 4-bit decoder 9, "1" is output to one bit of the 4-bit output according to the input. The least significant bit a of the clock counter 8 and the bit a of the decoder 9 are taken as two inputs of the AND gate G1, and the second bit b of the clock counter 8 and the bit b of the decoder 9 are taken as two inputs of the AND gate G2. The third bit c of the clock counter 8 and the bit c of the decoder 9 are used as two inputs of the AND gate G3, and the most significant bit d of the clock counter 8 and the bit d of the decoder 9 are used as two inputs of the AND gate G4. Outputs of the four AND gates G1 to G4 are input to an OR gate G5. The output of the OR gate G5 is the output of the timing signal generator 7, and this is the timing signal for the expected value comparator 6. That is, when the bit of the clock counter 8 corresponding to the bit selected by the decoder 9 causes a carry, the timing signal output from the OR gate G5 of the timing signal generator 7 becomes "1".
[0036]
The least significant bit a of the clock counter 8 outputs a reference clock having the same cycle as that of the clock signal CLK, but ON / OFF is controlled by the bit a of the decoder 9 in the AND gate G1. When the input signal (C1, C2) = (0, 0) to the decoder 9, the bit a of the decoder 9 becomes "1", and the reference clock is selected as the timing signal.
[0037]
The second bit b of the clock counter 8 outputs a clock obtained by dividing the reference clock by two, and ON / OFF is controlled by the bit b of the decoder 9 in the AND gate G2. When the input signal (C1, C2) = (0, 1) to the decoder 9, the bit b of the decoder 9 becomes "1", and the clock divided by 2 is selected as the timing signal.
[0038]
The third bit c of the clock counter 8 outputs a clock obtained by dividing the reference clock by 4, and ON / OFF is controlled by the bit c of the decoder 9 in the AND gate G3. FIG. 7 shows the operation of the timing signal generator 7 at this time. When the input signal (C1, C2) = (1, 0) to the decoder 9, the bit c of the decoder 9 becomes “1”, and a clock divided by 4 is selected as a timing signal.
[0039]
The most significant bit d of the clock counter 8 outputs a clock obtained by dividing the reference clock by 8, and ON / OFF is controlled by the bit d of the decoder 9 in the AND gate G4. When the input signal (C1, C2) = (1, 1) to the decoder 9, the bit d of the decoder 9 becomes "1", and the clock of divide-by-8 is selected as the timing signal.
[0040]
In any case, when the timing signal output from the OR gate G5 of the timing signal generator 7 becomes "1", the control for the expected value comparator 6 becomes active, and the expected value comparator 6 The value stored in the container 4 is compared with the expected value.
[0041]
As described above, according to the present embodiment, the number of clock cycles of the timing signal can be changed by switching the decoder input. That is, the expected value comparison can be performed a plurality of times, and it becomes easy to narrow down the timing at which the influence of the failure appears.
[0042]
(Embodiment 4)
FIG. 8 is a block diagram showing a configuration of a built-in self-test circuit according to the fourth embodiment (corresponding to claim 4) of the present invention. In FIG. 8, 1 is a pattern generator, 2 is a circuit under test, 4 is an output response compressor, 10 is a temporary register, and 11 is a clock frequency dividing circuit. The output of each bit of the output response compressor 4 is connected to each bit input of the temporary register 10. The clock frequency dividing circuit 11 divides the frequency of the clock signal CLK supplied to the output response compressor 4, converts it into a low-frequency timing signal CLK 1, and supplies it to the temporary register 10. The circuit under test 2 includes a plurality of scan paths as in the case of the first embodiment.
[0043]
FIG. 9 is a timing chart when a quarter frequency divider circuit is used as the clock frequency divider circuit 11 in FIG. T1 and T2 are timings for storing temporary data. The timing signal CLK1 supplied to the temporary register 10 becomes active once every time the reference clock enters the output response compressor 4 four times. Therefore, the data stored in the temporary register 10 is data after the output response compressor 4 operates for four clocks. Therefore, by outputting the value of the temporary register 10 to an external terminal in synchronization with the timing signal CLK1 from the clock frequency dividing circuit 11 and observing the value, it is possible to observe the output response during the inspection. Further, since the temporary register 10 does not affect the data of the output response compressor 4, the output response compressor 4 can be operated normally and concurrently without stopping while observing the data of the temporary register 10. Can be.
[0044]
As described above, according to the present embodiment, it is possible to periodically observe the value of the output response compressor during the inspection, and it is possible to easily narrow down the timing at which the effect of the failure appears. Further, when observing the value of the temporary register, the observation can be performed without stopping the operation of the output response compressor, and efficient processing can be performed.
[0045]
【The invention's effect】
According to the present invention, output responses from a plurality of scan paths are divided into groups and stored in a plurality of output response compressors, and when a suspected scan path occurs, the scan path selection circuit is controlled to control the suspected scan path. Is configured to switch the output response compressor to be connected and to distribute it to individual output response compressors, so that multiple suspected scan paths can be separately observed without affecting each other. can do. Then, by comparing expected values again in the plurality of output response compressors, the suspected scan path can be further narrowed down. Therefore, it is possible to easily distinguish a scan path corresponding to a failure from a normal scan path and easily identify which scan path is affected by the failure.
[0046]
Further, based on the timing signal from the timing signal generator, each time a test pattern is applied, the output response compressor to which each scan path is to be connected is automatically switched and the output response is stored in a separate output response compressor. Therefore, the output response of the scan path during the inspection can be stored in each output response compressor without being overwritten, and the timing at which the influence of the failure appears can be narrowed down. Therefore, the failure pattern can be narrowed down easily.
[0047]
Further, by changing the timing cycle of the pass / fail judgment execution, the pass / fail judgment can be performed by dividing the entire inspection into a plurality of timings, and a pattern showing the influence of a failure and a pattern showing a normal response can be determined. The suspected pattern can be narrowed down while being determined.
[0048]
In addition, by connecting a temporary register that operates in a different clock cycle from the output response compressor, it is possible to observe the output response during the scan path inspection, and efficiently narrow down the timing at which the effect of the failure appears. It can be carried out.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a built-in self-test circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of one selector of a scan path selection circuit according to the first embodiment.
FIG. 3 is a block diagram showing a circuit state after connection switching of a scan path according to the first embodiment;
FIG. 4 is a block diagram showing a configuration of a built-in self-test circuit according to a second embodiment of the present invention;
FIG. 5 is a circuit diagram showing a configuration of three selectors of a scan path selection circuit according to a second embodiment.
FIG. 6 is a block diagram showing a configuration of a built-in self-test circuit according to a third embodiment of the present invention.
FIG. 7 is a circuit diagram showing one circuit state of the timing signal generator according to the third embodiment.
FIG. 8 is a block diagram showing a configuration of a built-in self-test circuit according to a fourth embodiment of the present invention.
FIG. 9 is a timing chart of the built-in self-test circuit according to the fourth embodiment;
[Explanation of symbols]
1 Pattern generator
2 Circuit under test
2 _i (I = 1,2,9) Scan path
3 Scan path selection circuit
4a, 4b, 4c output response compressor
5 Clock counter (timing signal generator)
6 expected value comparator
7 Timing signal generator
8 clock counter
9 Decoder
10 Temporary register
11 Clock frequency divider
M _i (I = 1,2,9) selector

Claims (4)

A plurality of scan paths for performing an LSI test;
A pattern generator that supplies a test pattern to the plurality of scan paths;
A plurality of output response compressors storing the output responses from the plurality of scan paths in a state divided into several groups,
A built-in self-test circuit, comprising: a scan path selection circuit interposed between the scan path and the output response compressor to switch a connection state between the plurality of scan paths and the plurality of output response compressors. 2. The built-in self test according to claim 1, further comprising a timing signal generator for controlling the scan path selection circuit to generate a timing signal for switching a connection state between the scan path and the output response compressor. circuit. A plurality of scan paths for performing an LSI test;
A pattern generator that supplies a test pattern to the plurality of scan paths;
An output response compressor that stores output responses from the plurality of scan paths;
A built-in self-inspection circuit, comprising: a timing signal generator for generating a timing signal for a pass / fail judgment with respect to a value stored by the output response compressor and a programmable number of clock cycles for generating the timing signal. A plurality of scan paths for performing an LSI test;
A pattern generator that supplies a test pattern to the plurality of scan paths;
An output response compressor that stores output responses from the plurality of scan paths;
A built-in self-test circuit, comprising: a temporary register connected to the output side of the output response compressor and operating on a different clock cycle from the output response compressor.

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