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TWI560841B - Wafer level package and fabrication method thereof - Google Patents

Wafer level package and fabrication method thereof

Info

Publication number
TWI560841B
TWI560841B TW104128257A TW104128257A TWI560841B TW I560841 B TWI560841 B TW I560841B TW 104128257 A TW104128257 A TW 104128257A TW 104128257 A TW104128257 A TW 104128257A TW I560841 B TWI560841 B TW I560841B
Authority
TW
Taiwan
Prior art keywords
fabrication method
wafer level
level package
package
wafer
Prior art date
Application number
TW104128257A
Other languages
English (en)
Other versions
TW201701443A (zh
Inventor
Shing-Yih Shih
Neng-Tai Shih
Hsu Chiang
Original Assignee
Inotera Memories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inotera Memories Inc filed Critical Inotera Memories Inc
Application granted granted Critical
Publication of TWI560841B publication Critical patent/TWI560841B/zh
Publication of TW201701443A publication Critical patent/TW201701443A/zh

Links

Classifications

    • H10W74/137—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H10P72/74—
    • H10W70/60—
    • H10W70/611—
    • H10W70/635—
    • H10W70/685—
    • H10W70/69—
    • H10W70/692—
    • H10W74/014—
    • H10W74/117—
    • H10W90/701—
    • H10P72/7412—
    • H10P72/7424—
    • H10P72/744—
    • H10W72/0198—
    • H10W72/072—
    • H10W72/07207—
    • H10W72/241—
    • H10W74/019—
    • H10W74/142—
    • H10W74/15—
    • H10W90/724—
    • H10W90/734—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW104128257A 2015-06-22 2015-08-28 Wafer level package and fabrication method thereof TWI560841B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/745,473 US9520333B1 (en) 2015-06-22 2015-06-22 Wafer level package and fabrication method thereof

Publications (2)

Publication Number Publication Date
TWI560841B true TWI560841B (en) 2016-12-01
TW201701443A TW201701443A (zh) 2017-01-01

Family

ID=57483987

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104128257A TWI560841B (en) 2015-06-22 2015-08-28 Wafer level package and fabrication method thereof

Country Status (3)

Country Link
US (1) US9520333B1 (zh)
CN (2) CN106257658A (zh)
TW (1) TWI560841B (zh)

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US10522449B2 (en) * 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
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US11101209B2 (en) * 2017-09-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures in semiconductor packages and methods of forming same
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KR102055595B1 (ko) * 2017-12-15 2019-12-16 삼성전자주식회사 반도체 패키지
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US10727204B2 (en) 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration
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US10923421B2 (en) 2019-04-23 2021-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US11296062B2 (en) * 2019-06-25 2022-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimension large system integration
CN113451140A (zh) * 2020-03-24 2021-09-28 合肥晶合集成电路股份有限公司 封装结构的形成方法
TWI739413B (zh) * 2020-05-04 2021-09-11 力成科技股份有限公司 半導體裝置及其製造方法
KR102792183B1 (ko) * 2020-09-07 2025-04-09 삼성전자주식회사 반도체 패키지
KR102901937B1 (ko) * 2021-03-31 2025-12-18 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판
US12033947B2 (en) * 2021-04-15 2024-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package structure and method for forming the same
US11973058B2 (en) 2021-11-25 2024-04-30 International Business Machines Corporation Multiple die assembly
CN119542149A (zh) * 2023-08-29 2025-02-28 矽磐微电子(重庆)有限公司 半导体结构的制造方法及半导体结构

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TW201417197A (zh) * 2012-09-28 2014-05-01 史達晶片有限公司 形成支撐層於薄扇出晶圓級晶片尺寸封裝中之半導體晶粒之上的半導體裝置和方法
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TW201526125A (zh) * 2013-12-23 2015-07-01 史達晶片有限公司 半導體裝置和在扇出封裝中於半導體晶粒上形成細節距重新分佈層之方法

Also Published As

Publication number Publication date
CN113113365B (zh) 2025-01-28
CN113113365A (zh) 2021-07-13
TW201701443A (zh) 2017-01-01
US20160372395A1 (en) 2016-12-22
US9520333B1 (en) 2016-12-13
CN106257658A (zh) 2016-12-28

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