TWI559531B - Insulated gate bipolar transistor and method of manufacturing the same - Google Patents

Description

Insulated gate bipolar transistor and manufacturing method thereof

Embodiments of the present invention relate to semiconductor technology, and in particular to insulated gate bipolar transistors and methods of fabricating the same.

Power components are widely used in home appliances and automotive applications for driving and controlling high power. This power component includes a power transistor that performs a large output of the switching operation. The power transistor includes an insulated gate bipolar transistor (IGBT) in addition to a power MOS field-effect transistor (MOSFET) and a power bipolar transistor. The insulated gate bipolar transistor has both the high input impedance of the gold oxide half field effect transistor and the low on resistance of the bipolar transistor.

An embodiment of the present invention provides an insulated gate bipolar transistor, comprising: a collector electrode; a collector layer electrically connected to the collector electrode and having a second conductivity type; and a first conductivity type drift layer disposed on the collector layer The first conductivity type is different from the second conductivity type; the first emitter layer is disposed on the first conductivity type drift layer and has a second conductivity type; a trench, from the first emitter layer The surface extends into the first conductive type drift layer, wherein the trench has opposite first and second sides; the gate electrode fills the trench and extends over the surface of the first emitter layer, wherein The extension of the gate electrode on the side and the second side on the surface of the first emitter layer Different; the gate dielectric layer is disposed between the gate electrode and the trench, and between the gate electrode and the first emitter layer; and the second emitter region is disposed on the first side of the gate electrode In the pole layer, the second emitter region has a first conductivity type; the interlayer dielectric layer is disposed on the first emitter layer; and the emitter electrode is electrically connected to the first emitter layer and the second emitter region The interlayer dielectric layer is disposed between the gate electrode and the emitter electrode.

The embodiment of the present invention further provides a method for manufacturing an insulated gate bipolar transistor, comprising: providing a substrate having a first conductivity type and having an upper surface and a lower surface; forming a first emitter region having a second conductivity type, And extending from the upper surface of the substrate into the substrate, and the second conductivity type is different from the first conductivity type; forming a trench extending from the upper surface of the substrate through the first emitter region to the substrate, wherein the trench has a first gate and a second side; forming a gate structure including a gate dielectric layer and a gate electrode, wherein the gate electrode is filled in the trench and extends to the upper surface of the substrate, wherein the first side The gate electrode on the second side has a different extension distance on the upper surface of the substrate, and the gate dielectric layer is disposed between the gate electrode and the trench, and between the gate electrode and the first emitter region; The second emitter region is in the first emitter region on both sides of the gate electrode, wherein the second emitter region has a first conductivity type; an interlayer dielectric layer is formed on the gate electrode; an emitter electrode is formed, and the emitter electrode is formed The first emitter region and the second emitter region are electrically connected, and The dielectric layer is disposed between the gate electrode and the emitter electrode; forming a collector region, having a second conductivity type, and extending from the lower surface of the substrate into the substrate, wherein the substrate is not formed with the first emitter region, The portions of the second emitter region and the collector region are used as the first conductivity type drift region; and the collector electrode is formed, and the collector electrode is electrically connected to the collector region.

The embodiment of the invention further provides a method for manufacturing an insulated gate bipolar transistor, comprising: providing a substrate having a second conductivity type, wherein the substrate system As a collector region; forming an epitaxial layer on the substrate, the epitaxial layer has a first conductivity type, and the first conductivity type is different from the second conductivity type; forming a first emitter region extending from the surface of the epitaxial layer into the Lei In the crystal layer, and having a second conductivity type; forming a trench extending from the surface of the first emitter region through the first emitter region to the epitaxial layer, wherein the trench has a first side and a first Forming a gate structure comprising a gate dielectric layer and a gate electrode, wherein the gate electrode is filled in the trench and extends to a surface of the first emitter region, wherein the gates on the first side and the second side The pole electrode has a different extension distance on the surface of the first emitter region, and the gate dielectric layer is disposed between the gate electrode and the trench, and between the gate electrode and the first emitter region; forming a second shot The pole region is in the first emitter region on both sides of the gate electrode, wherein the second emitter region has a first conductivity type, wherein the portion of the epitaxial layer not formed with the first emitter region and the second emitter region is a first conductivity type drift region; forming an interlayer dielectric layer on the gate electrode; forming an emitter electrode, an emitter electrode and the first Region, a second region of the radio link, and the interlayer dielectric layer disposed between the gate electrode and the emitter electrodes; and forming a collector electrode, a collector electrode electrically connected to collector region.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments of the present invention are described in detail below.

100‧‧‧Substrate

100A‧‧‧Upper surface

100B‧‧‧ lower surface

110‧‧‧First emitter area/layer

120‧‧‧ trench

S1‧‧‧ first side

S2‧‧‧ second side

130‧‧‧ gate structure

130P‧‧‧Horizontal gate section

130V‧‧‧vertical gate

140‧‧‧ dielectric material layer

150‧‧‧ Conductive layer

160‧‧‧ gate dielectric layer

170‧‧‧gate electrode

180‧‧‧second emitter area

190‧‧‧Interlayer dielectric layer

200‧‧‧Contact opening

210‧‧‧The third emitter area

220‧‧ ‧ emitter electrode

230‧‧‧Positive reservation area

240‧‧‧ Scheduled drift zone

250‧‧‧ heavily doped buffer layer

260‧‧‧ Collector Zone/Layer

255/270‧‧‧First Conductive Drift Zone/Layer

280‧‧ ‧ collector electrode

300‧‧‧Insulated gate bipolar transistor

T1‧‧‧ thickness

T2‧‧‧ thickness

T3‧‧‧ thickness

W1‧‧‧Width

W2‧‧‧Width

W3‧‧‧Width

W4‧‧‧Width

W5‧‧‧Width

1-8 are cross-sectional views showing stages of an insulated gate bipolar transistor of an embodiment of the present invention in a method of manufacturing the same; and FIG. 9 is a cross-sectional view showing an insulating gate bipolar transistor of another embodiment of the present invention; Figure 10 shows the current density and voltage analysis of an insulated gate bipolar transistor Figure 11 is a partial enlarged view of Figure 10; Figure 12 is a safe operating region and conduction voltage analysis diagram of the insulated gate bipolar transistor; Figure 13 is the switching performance of the insulated gate bipolar transistor Fig. 14 is a partial enlarged view of Fig. 13; Fig. 15 is an electric field analysis diagram of an insulated gate bipolar transistor; and Fig. 16 is a collapse voltage analysis diagram of an insulated gate bipolar transistor.

The insulated gate bipolar transistor of the embodiment of the present invention will be described in detail below. It will be appreciated that the following description provides many different embodiments or examples for implementing the invention. The specific elements and arrangements described below are merely illustrative of the invention. Of course, these are by way of example only and not as a limitation of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not to be construed as a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more layers of other materials interposed, in which case there may be no direct contact between the first layer of material and the second layer of material.

It is to be understood that the elements specifically described or illustrated may be in various forms well known to those skilled in the art. In addition, when a layer is "on" another layer or substrate, it may mean "directly" on another layer or substrate, or a layer on another layer or substrate, or between other layers or substrates. Other layers.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element to another. It will be understood that if the illustrated device is flipped upside down, the component described on the "lower" side will be the component on the "higher" side.

Herein, the terms "about" and "about" are used in some embodiments to generally mean within 20% or other values of a given value or range, preferably within 10%, and more preferably 5%. Inside. The quantity given here is an approximate quantity, meaning that the meaning of "about" or "about" may be implied without specific explanation.

Embodiments of the present invention may utilize an asymmetric gate structure to reduce the current density and turn-off loss of the insulated gate bipolar transistor while maintaining its turn on voltage.

Referring to Figure 1, a substrate 100 is first provided. The substrate 100 may include: a single crystal structure, a polycrystalline structure or an amorphous structure of germanium or germanium elemental semiconductor; gallium nitride (GaN), silicon carbide, gallium arsenic, gallium phosphide Compound semiconductors such as (gallium phosphide), indium phosphide, indium arsenide or indium antimonide; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP or others Suitable materials and/or combinations of the above. This substrate 100 has a first conductivity type. For example, when the first conductivity type is an N-type, the substrate 100 may be a lightly doped N-type substrate. Further, the substrate 100 has an upper surface 100A and a lower surface 100B.

Next, a first emitter region 110 (also referred to as a first emitter layer 110) is formed in the substrate 100. The first emitter region 110 extends from the upper surface 100A of the substrate 100 (also referred to as the surface 100A of the first emitter layer 110) into the substrate 100. As shown in FIG. 1, the first emitter region 110 is only A portion of the depth extending into the substrate 100, that is, the thickness T1 of the first emitter region 110 is less than the thickness T2 of the substrate 100. The first emitter region 110 has a second conductivity type, and the second conductivity type is different from the first conductivity type. The first emitter region 110 can be formed by an ion implantation step. For example, in an embodiment, when the second conductivity type is a P-type, the region can be implanted in a region where the first emitter region 110 is predetermined to be formed. Boron ion, indium ion or boron difluoride ion (BF ₂ ⁺ ).

Next, referring to FIG. 2, a trench 120 is formed. The trench 120 extends from the upper surface 100A of the substrate 100 through the first emitter region 110 and into the substrate 100 (ie, into the subsequent first conductive type drift layer or in the epitaxial layer of another embodiment) And the trench 120 has a first side S1 and a second side S2 opposite to each other.

Referring next to FIGS. 3 and 4, a gate structure 130 is formed. In some embodiments, this gate structure 130 can be formed by the following steps. First, referring to FIG. 3, a dielectric material layer 140 is formed on the sidewalls and the bottom of the trench 120 and the upper surface 100A of the substrate 100 in compliance. Next, a conductive layer 150 is blanket deposited on the dielectric material layer 140 and filled into the trenches 120. Thereafter, as shown in FIG. 4, the dielectric material layer 140 and the conductive layer 150 are patterned by a lithography and etching step to form the gate dielectric layer 160 and the gate electrode 170, respectively, and complete the gate structure 130. In other words, the gate structure 130 includes a gate dielectric layer 160 and a gate electrode 170.

The dielectric material layer 140 (to form the gate dielectric layer 160) may be tantalum oxide, tantalum nitride, hafnium oxynitride, high-k dielectric material, or any other suitable dielectric. Material, or a combination of the above. The high-k dielectric material may be a metal oxide, a metal nitride, a metal halide, a transition metal oxide, a transition metal nitride, a transition metal telluride, a metal oxynitride, a metal aluminate, or a zirconium Acid salt, zirconium aluminate. For example, the high-k dielectric material may be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO. ₂ , HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , other high dielectric constants of other suitable materials Dielectric material, or a combination of the above. The dielectric material layer 140 can be formed by chemical vapor deposition (CVD) or spin coating. The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (LPCVD), low temperature. Low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), Atomic layer deposition (ALD) or other commonly used methods of atomic layer chemical vapor deposition.

The material of the conductive layer 150 (that is, the material of the gate electrode 170) may be amorphous germanium, a germanium germanium or a combination thereof. The material of the conductive layer 150 can be formed by the aforementioned chemical vapor deposition (CVD) or any other suitable deposition method. For example, in one embodiment, low pressure chemical vapor deposition (LPCVD) can be used at 525-650. An amorphous germanium conductive material layer or a germanium germanium conductive layer 150 is deposited between ° C and may have a thickness ranging from about 1000 Å to about 10000 Å.

In addition, the top of the gate electrode 170 may further include a metal telluride layer (not shown), which may include, but is not limited to, nickel silicide, cobalt silicide, tungsten tungsten silicide. ), titanium silicide, tantalum silicide, platinum telluride (platinum silicide) and erbium silicide.

As shown in FIG. 4, the gate structure 130 includes a horizontal gate portion 130P disposed outside the trench 120 and a vertical gate portion 130V disposed in the trench 120 as shown in FIG. Since the vertical gate portion 130V is disposed away from the center of the gate structure 130, the axis of the vertical gate portion 130V is not aligned with the central axis of the horizontal gate portion 130P, so the gate structure 130 may also be referred to as a non- Symmetrical gate structure 130.

Continuing to refer to FIG. 4, the gate dielectric layer 160 directly contacts the first emitter region 110 and the substrate 100, and extends to the upper surface 100A of the substrate 100, and the gate electrode 170 is disposed on the gate dielectric layer 160. And filling the groove 120. The gate dielectric layer 160 electrically insulates the gate electrode 170 from the first emitter region 110, the substrate 100, and the subsequently formed second emitter region. In other words, in the gate structure 130, the gate electrode 170 is filled in the trench 120 and extends to the upper surface 100A of the substrate 100 (that is, extends to the surface of the first emitter region/layer 110). The gate electrodes 170 on the first side S1 and the second side S2 have different extension distances on the upper surface 100A of the substrate 100 (or the first emitter region/layer 110). The gate dielectric layer 160 is disposed between the gate electrode 170 and the trench 120 and between the gate electrode 170 and the first emitter region 110.

The horizontal gate portion 130P of the asymmetric gate structure 130 can extend the channel region of the finally formed insulating gate bipolar transistor to reduce the current density and shutdown loss of the device, for example, to reduce the current density by about 20%, and Reduce the shutdown time from 435ns to 295ns.

On the other hand, in the asymmetric gate structure 130, when the vertical gate portion 130V is deviated from the center of the gate electrode 170, it indicates that the closer to the second emitter region which is formed on both sides of the gate electrode 170. . In the horizontal gate While the sub-130P reduces the current density and the turn-off loss, if the vertical gate portion 130V is closer to the second emitter region, the amount of increase in the turn-on voltage of the finally formed insulating gate bipolar transistor is lower. In some embodiments, if the vertical gate portion 130V of the gate structure 130 directly contacts the second emitter region, the increase in the turn-on voltage of the insulated gate bipolar transistor is almost zero, that is, the turn-on voltage is almost Will not rise. Thus, the vertical gate portion 130V of the asymmetric gate structure 130 maintains the turn-on voltage of the finally formed insulated gate bipolar transistor so that it does not rise too much, or even rises.

Therefore, since the asymmetric gate structure 130 of the present invention has the horizontal gate portion 130P and the vertical gate portion 130V at the same time, it can reduce the turn-off loss and reduce the current density without affecting the turn-on voltage, thereby solving the conventional insulating gate. There is a trade-off problem between the turn-on voltage and the current density or turn-off loss in a bipolar transistor.

Next, as shown in FIG. 5, a second emitter region 180 is formed in the first emitter region 110 on both sides of the gate electrode 170, and the second emitter region 180 has a first conductivity type. For example, in one embodiment, the second emitter region 180 is heavily doped with a first conductivity type. The second emitter region 180 extends from the upper surface 100A of the substrate 100 (also referred to as the surface 100A of the first emitter layer 110) into the first emitter region 110. In the embodiment of the invention, the second emitter The region 180 extends only a portion of the depth of the first emitter region 110, that is, the thickness T3 of the second emitter region 180 is less than the thickness T1 of the first emitter region 110. In an embodiment, the second emitter region 180 can be formed by an ion implantation step. For example, when the first conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the second emitter region 180 is predetermined to be formed.

With continued reference to FIG. 5, in some embodiments, located in trench 120 The second emitter region 180 of the second side S2 can directly contact the trench 120. As can be seen from the foregoing, when the second emitter region 180 on the second side S2 directly contacts the trench 120, the amount of increase in the turn-on voltage of the insulated gate bipolar transistor can be almost zero. In addition, in the embodiment, the gate electrode 170 does not extend to the upper surface 100A of the substrate 100 of the second side S2, that is, the gate electrode 170 of the second side S2 is on the substrate 100 or the first emitter region. The extension distance on the upper surface 100A of the layer 110 is zero. However, those skilled in the art can understand that the gate electrode 170 can also extend onto the upper surface 100A of the substrate 100 on the second side S2, and the second emitter region 180 on the second side S2 may not directly Contact trench 120, which will be described in detail in another embodiment that follows.

Furthermore, the second emitter region 180 at the first side S1 of the trench 120 is spaced apart from the trench 120 by a width W2. This width W2 is approximately the distance W3 of the horizontal gate portion 130P minus the width W4 of the trench 120 and the width of the second emitter region 180 diffused to the width W5 below the horizontal gate portion 130P. In some embodiments, the width W2 is 0.05-0.2 times the width W1 of the first emitter region 110. In one embodiment, if the width W2 is too wide, for example, 0.2 times wider than the width W1 of the first emitter region 110, the current density of the finally formed insulated gate bipolar transistor is excessively reduced (eg, reduced by more than about The current density of 20%) makes it difficult to apply the finally formed insulating gate bipolar transistor to practical semiconductor devices. However, if the width W2 is too narrow, for example, 0.05 times smaller than the width W1 of the first emitter region 110, the current density of the finally formed insulated gate bipolar transistor cannot be effectively reduced (for example, the current density is reduced less than About 5%), the characteristics of the finally formed insulated gate bipolar transistor short circuit test are not good.

Next, continue to refer to FIG. 5 to form an interlayer dielectric layer 190 at the gate. On the pole electrode 170. The interlayer dielectric layer 190 covers the top and sidewalls of the portion of the gate structure 130 that is outside the trench 120. The interlayer dielectric layer 190 is used to electrically insulate the gate electrode 170 from the subsequently formed emitter electrode. The interlayer dielectric layer 190 can be tantalum oxide, tantalum nitride, hafnium oxynitride, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), spin on glass (SOG), or any other suitable dielectric material, Or a combination of the above. The interlayer dielectric layer 190 can be formed by the aforementioned chemical vapor deposition (CVD), spin coating or high density plasma (HDP) deposition and patterning steps.

Next, referring to FIG. 6, a contact etching step is performed to etch through the interlayer dielectric layer 190 and the second emitter region 180 to form the contact openings 200. This etching step can include reactive ion etch (RIE), plasma etching, or other suitable etching steps. Next, an ion implantation step can be selectively performed to form a third emitter region 210 in the first emitter region 110. The third emitter region 210 can be heavily doped second conductivity type. The step of forming the third emitter region 210 in the embodiment of the present invention does not use an additional mask, thereby reducing production costs. In the foregoing embodiment, the trench is formed first and then the doping process is performed to form the third emitter region 210. In other embodiments, only the doping process may be used to form the third emitter region in the predetermined region. The depth of the third emitter region formed will be comparable to the depth of the second emitter region 180.

Next, referring to Fig. 7, an emitter electrode 220 is formed. The emitter electrode 220 is electrically connected to the second emitter region 180 and the third emitter region 210. The emitter electrode 220 is coupled (electrically coupled) to the first emitter region 110 through the third emitter region 210. In some embodiments, the emitter electrode 220 is formed on the interlayer dielectric layer 190 and filled into the contact opening 200. The emitter electrode 220 can be a single layer or multiple layers of gold, Chromium, nickel, platinum, titanium, aluminum, ruthenium, iridium, copper, combinations of the above or other highly conductive metal materials (for example, aluminum-copper alloy (AlCu), aluminum-bismuth copper alloy (AlSiCu)). The emitter electrode 220 can be formed by, for example, sputtering, electroplating, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process. In addition, the interlayer dielectric layer 190 is disposed between the gate electrode 170 and the emitter electrode 220. The interlayer dielectric layer 190 can electrically insulate the gate electrode 170 from the emitter electrode 220.

Next, after the emitter electrode 220, the substrate 100 can be selectively thinned (the thinning step is not illustrated in the drawings). The thickness of the thinned substrate 100 varies depending on the operating voltage and the structure of the device.

As shown in FIG. 7, the bottom of the substrate 100 is a collector predetermined region 230, and the substrate 100 has a first emitter region 110, a second emitter region 180, a third emitter region 210, and a collector predetermined region 230. The area is defined as a predetermined drift area 240.

Then, after forming the emitter electrode 220 or after thinning the substrate 100 (if there is a step of thinning the substrate 100), the heavily doped buffer layer 250 may be selectively formed in the predetermined drift region 240 (ie, formed in the subsequent In the first conductivity type drift region/layer). The heavily doped buffer layer 250 has a first conductivity type and can be used to further reduce the size of the finally formed insulating gate bipolar transistor. This heavily doped buffer layer 250 can be formed by an ion implantation step. For example, when the first conductivity type is an N-type, phosphorus ions or arsenic ions may be implanted in a region where the heavily doped buffer layer 250 is to be formed. In another embodiment, the heavily doped buffer layer having the first conductivity type may be formed by thermal diffusion in the bottom surface of the substrate 100 in FIG. 1 (for example, the weight of the seventh to eighth figures). Doping buffer layer 250), the temperature of the thermal diffusion process is about 1100 ° C ~ 1200 ° C. In this way, a doping process can be used in conjunction with a thermal diffusion process to form a desired buffer layer having a predetermined thickness. for example, First, a semiconductor substrate (for example, an N-type substrate) is subjected to a process of doping and thermal diffusion, and a buffer layer is formed on the opposite surfaces of the semiconductor substrate to form a buffer layer, and then the semiconductor substrate is followed by The parallel direction of the surface is cut into two semiconductor substrates, the buffered layer is provided on one side of the cut substrate, and the buffer layer is not provided on the other side, and then the subsequent steps are performed on the surface without the buffer layer (for example, 1 step in the figure).

Next, referring to FIG. 8, an ion implantation step is performed to implant a second conductivity type dopant to form a collector region 260 (also referred to as a collector layer 260) at the collector predetermined region 230, and the collector region 260 has the The second conductivity type extends into the substrate 100 from the lower surface 100B of the substrate 100. The portion of the substrate 100 that is not formed with the first emitter region 110, the second emitter region 180, the third emitter region 210, the collector region 260, and the heavily doped buffer layer 250 is used as the first conductivity type drift region 255 (also It is called a first conductivity type drift layer 255). The heavily doped buffer layer 250 is located between the first conductivity type drift region 255 and the collector region 260. It should be noted that if the heavily doped buffer layer 250 is not formed, the substrate 100 is not formed with the first emitter region 110, the second emitter region 180, the third emitter region 210, and the portion 270 of the collector region 260. As the first conductivity type drift region 270 (also referred to as a first conductivity type drift layer 270).

Next, continuing to refer to FIG. 8, a collector electrode 280 is formed to complete the fabrication of the insulated gate bipolar transistor 300. The collector electrode 280 is electrically connected to the collector region 260. The collector electrode 280 may be a single layer or a plurality of layers of gold, chromium, nickel, platinum, titanium, aluminum, tantalum, niobium, copper, combinations thereof, or other highly conductive metal materials such as titanium nickel silver (TiNiAg). The collector electrode 280 can be formed by, for example, sputtering, electroplating, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process.

The foregoing embodiment forms the collector region after the formation of the emitter region, but the present invention is not limited to this manufacturing method. For example, a semiconductor substrate having a second conductivity type (eg, P+) may be provided, the dopant concentration of the semiconductor substrate conforming to the dopant concentration of the collector region 260 in the IGBT 300 to be formed, and then on the semiconductor substrate. The buffer layer (for example, the heavily doped buffer layer 250 of FIGS. 7 to 8) is selectively formed by, for example, epitaxial growth. Then, a drift region of the IGBT (for example, the first conductivity type drift region 255 of FIG. 8) is further formed by, for example, epitaxial growth. Then, other portions of the IGBT are formed by, for example, the relevant steps of the first to seventh embodiments. In this embodiment, the drift region which is epitaxially grown is equivalent to the substrate 100 in FIG. 1, similar to the first to seventh embodiments. In the step of the figure, other portions such as the first emitter region 110 and the like are sequentially formed in the drift region.

The insulated gate bipolar transistor 300 of the embodiment of the present invention includes a collector electrode 280. The collector layer 260 is electrically connected to the collector electrode 280 and has a second conductivity type. The first conductive type drift layer 255 is disposed on the collector layer 260, wherein the first conductive type is different from the second conductive type. The first emitter layer 110 is disposed on the first conductive type drift layer 255 and has a second conductivity type. A trench 120 extends from the surface 100A of the first emitter layer 110 into the first conductive type drift layer 255, wherein the trench 120 has a first side S1 and a second side S2 opposite to each other. The gate electrode 170 is filled in the trench 120 and extends on the surface 100A of the first emitter layer 110. The gate electrode 170 on the first side S1 and the second side S2 is on the surface of the first emitter layer 110. The extension distance on the 100A is different. The gate dielectric layer 160 is disposed between the gate electrode 170 and the trench 120 and between the gate electrode 170 and the first emitter layer 110. The second emitter region 180 is disposed in the first emitter layer 110 on both sides of the gate electrode 170, wherein the second emitter region 180 has a first conductivity type. An interlayer dielectric layer 190 disposed on the first emitter layer 110 on. The emitter electrode 220 is electrically connected to the first emitter layer 110 and the second emitter region 180 , wherein the interlayer dielectric layer 190 is disposed between the gate electrode 170 and the emitter electrode 220 . The insulated gate bipolar transistor 300 further includes a heavily doped buffer layer 250 having a first conductivity type and disposed between the first conductivity type drift layer 255 and the collector layer 260.

In some embodiments, the second emitter region 180 on the second side S2 of the trench 120 directly contacts the trench 120. Moreover, in some embodiments, the gate electrode 170 does not extend onto the upper surface 100A of the substrate 100 of the second side S2. Furthermore, the second emitter region 180 on the first side S1 of the trench 120 is spaced apart from the trench 120 by a width W2. In some embodiments, this width W2 can be about 0.05-0.2 times the width W1 of the first emitter region 110.

It should be noted that although in the embodiment shown in FIG. 8, the second emitter region on the second side of the trench directly contacts the trench, and the gate electrode does not extend to the upper surface of the substrate on the second side. on. However, those of ordinary skill in the art will appreciate that the second emitter region on the second side of the trench may also not directly contact the trench, and when the second emitter region on the second side does not directly contact the trench, The gate electrode must extend to the upper surface of the substrate on the second side to make the circuit of the device operational.

In detail, as shown in FIG. 9, the second emitter region 180 on the second side S2 may also not directly contact the trench 120, which is located in the second emitter region 180 and the trench on the second side S2 of the trench 120. The slots 120 are spaced apart by a width W6. The width W2 is greater than the width W6, and the width W6 is greater than or equal to 0. When the width W6 is equal to 0, it means that the second emitter region 180 on the second side S2 directly contacts the trench 120. When the second emitter region 180 of the second side S2 does not directly contact the trench 120, the gate electrode 170 needs to be extended. To the upper surface 100A of the substrate 100 of the second side S2. Thereafter, after the thermal diffusion process, the right emitter region 180 will diffuse and directly contact the second side S2 of the trench 120 to form a vertical channel.

It should be noted that, in the above embodiments, the first conductivity type is N type, and the second conductivity type is P type description. However, those skilled in the art can understand the first conductivity type. It can be P type, and the second conductivity type is N type at this time.

Table 1 shows the performance comparison between the insulated gate bipolar transistor of the embodiment of the present invention and the comparative example, and the 10th figure shows the current density and voltage analysis diagram of the insulated gate bipolar transistor, and Fig. 11 is the 10th figure. A partial enlargement of Part A. This analysis was simulated by Computer Computer Aided Design (TCAD). This embodiment is tested in the structure shown in Fig. 8, wherein the ratio of W2/W1 is about 0.9/6.0 to about 1.0/5.9, for example, about 0.95/5.95, and the trench insulating gate of the comparative example is double. The difference between the polar transistor (the trench IGBT of the comparative example) and the insulated gate bipolar transistor of the embodiment of the present invention is that The gate structure has only a vertical gate 130V portion without a horizontal gate 130P portion, and its second emitter region 180 directly contacts the vertical gate 130V portion of the first side S1. Figure 10 shows that the current density of the insulated gate bipolar transistor of the embodiment of the present invention is reduced by about 20% compared to the current density of the trench insulated gate bipolar transistor of the comparative example (e.g., Fig. 10) Part B). In addition, referring to FIGS. 10 and 11 and Table 1, the on-state voltage of the insulated gate bipolar transistor of the embodiment of the present invention is 2.68 V, and the on-voltage of the trench insulated gate bipolar transistor of the comparative example is 2.65. V. It can be seen that the insulated gate bipolar transistor of the embodiment of the present invention does not affect the turn-on voltage of the device while reducing the current density of the device, and the reduction of the current density can reduce the insulating gate bipolar electricity. The probability of failure of a short circuit test in a crystal.

Figure 12 is a diagram showing the safe operating area and conduction voltage of an insulated gate bipolar transistor. This embodiment is tested in the configuration shown in Figure 8, wherein the ratio W2/W1 is from about 0.9/6.0 to about 1.0/5.9, for example about 0.95/5.95, and the second emitter region 180 is in direct contact with the second. An insulated gate bipolar transistor of the trench 120 of side S2 (i.e., the portion of the second emitter region directly contacting the vertical gate 130V of the second side S2) is analyzed. In addition, the trench insulated gate bipolar transistor of the comparative example in this analysis (the trench IGBT of the comparative example) differs from the insulated gate bipolar transistor of the embodiment of the present invention in that the gate structure has only vertical The gate 130V portion does not have a horizontal gate 130P portion, and its second emitter region 180 directly contacts the vertical gate 130V portion of the first side S1. The difference between the horizontal insulated gate bipolar transistor of the comparative example (horizontal IGBT of the comparative example) and the insulated gate bipolar transistor of the embodiment of the present invention is that the gate structure has only the horizontal gate 130P portion, and Does not have a vertical gate 130V portion.

Fig. 12 shows that the trench-type insulated gate bipolar transistor of the comparative example has a low on-voltage (about 2.65 V), but its safe operation area is poor (about 5 μs). The horizontal insulated gate bipolar transistor of the comparative example has a better safe operating region (about 7 μs), but its turn-on voltage is higher (about 3.7 V). It can be seen that the trench-type insulating gate bipolar transistor of the comparative example and the horizontal insulating gate bipolar transistor of the comparative example cannot simultaneously have the above two advantages. In contrast, the insulated gate bipolar transistor of the embodiment of the present invention can combine the advantages of the trench insulated gate bipolar transistor of the comparative example and the horizontal insulated gate bipolar transistor of the comparative example. That is, the insulated gate bipolar transistor of the embodiment of the present invention has a better on-voltage (about 2.68 V) and a preferred safe operation region (about 7 μs). The insulated gate bipolar transistor of the embodiment of the present invention can simultaneously have the above two advantages because it can reduce the current density of the device without affecting its turn-on voltage, so the turn-on voltage can hardly rise. It is similar to the trench insulated gate bipolar transistor of the comparative example. However, the reduced current density of the insulated gate bipolar transistor of the embodiment of the invention can make it have a better safe operating area, even the same as the safe operating area of the horizontal insulated gate bipolar transistor of the comparative example, such as Figure 12 shows.

Fig. 13 is a graph showing the switching performance of the insulated gate bipolar transistor, and Fig. 14 is a partially enlarged view of Fig. 13 in section C. This analysis is simulated by computer software (TCAD). This embodiment is tested in the structure shown in Fig. 8, wherein the ratio of W2/W1 is about 0.9/6.0 to about 1.0/5.9, for example, about 0.95/5.95, and the trench insulating gate of the comparative example is double. The polar transistor (the trench IGBT of the comparative example) is the same as the trench IGBT of the comparative example of the foregoing embodiment. Figure 13, Figure 14, and Table 1 show an insulated gate bipolar device according to an embodiment of the present invention. The insulating gate bipolar of the embodiment of the present invention is applied to the crystal (Example IGBT) and the trench insulated gate bipolar transistor of the comparative example (the trench IGBT of the comparative example) when the same voltage is applied and the voltage is simultaneously turned off. The closing time of the current of the transistor was 295 ns, and the closing time of the trench insulated gate bipolar transistor of the comparative example (the trench IGBT of the comparative example) was 435 ns. It can be seen that the gate structure of the insulated gate bipolar transistor of the embodiment of the invention can greatly reduce the shutdown time of the device.

Figure 15 is an electric field analysis diagram of an insulated gate bipolar transistor. The horizontal axis of the figure represents the direction of the insulating gate bipolar transistor from the upper surface 100A to the lower surface 100B (that is, the direction Y in FIG. 1), and the vertical axis indicates that the insulating gate bipolar transistor is at the position electric field. This embodiment is tested in the structure shown in Fig. 8, wherein the ratio of W2/W1 is about 0.9/6.0 to about 1.0/5.9, for example, about 0.95/5.95, and the trench insulating gate of the comparative example is double. The polar transistor (the trench IGBT of the comparative example) is the same as the trench IGBT of the comparative example of the foregoing embodiment. As can be seen from Fig. 15, the electric field distribution inside the insulated gate bipolar transistor of the embodiment of the present invention is much uniform compared to the trench insulated gate bipolar transistor of the comparative example (the trench IGBT of the comparative example). And the electric field in the interval from point A to point B in Fig. 15 is strong. Since the strong electric field can have the blocking effect of the hole and reduce the closing time, the insulated gate bipolar transistor with strong electric field in this case can greatly reduce the closing time of the device.

Fig. 16 is a graph showing the collapse voltage of the insulated gate bipolar transistor of the embodiment of the present invention and the comparative example in a closed state. This analysis is simulated by computer software (TCAD). This embodiment is tested in the configuration shown in Fig. 8, and wherein the ratio of W2/W1 is from about 0.9/6.0 to about 1.0/5.9, for example, about 0.95/5.95, and the trench insulated gate bipolar transistor of the comparative example (the trench IGBT of the comparative example) is the same as the trench IGBT of the comparative example of the foregoing embodiment. Fig. 16 and Table 1 show that the current breakdown voltage of the insulated gate bipolar transistor of the embodiment of the present invention is 1250 V, and the trench insulated gate bipolar transistor of the comparative example (the trench IGBT of the comparative example) The breakdown voltage is also 1250V. It can be seen that the insulated gate bipolar transistor of the embodiment of the invention does not affect the breakdown voltage of the device while reducing the off time and current density of the device.

Further, Table 1 is tested in the structure shown in Fig. 8, and wherein the ratio of W2/W1 is about 0.9/6.0 to about 1.0/5.9, for example, about 0.95/5.95, and the trench insulation of the comparative example. The gate bipolar transistor (the trench IGBT of the comparative example) is the same as the trench IGBT of the comparative example of the foregoing embodiment. As can be seen from Table 1, the latch up current density of the insulated gate bipolar transistor of the embodiment of the present invention is 1450 A/cm ² , and the trench insulated gate bipolar transistor of the comparative example. The latch current density of the trench IGBT of the comparative example was 1500 A/cm ² . It can be seen that the insulated gate bipolar transistor of the embodiment of the present invention does not affect the latch current density while reducing the turn-off time and current density of the device.

In summary, the insulated gate bipolar transistor of the embodiment of the invention can reduce current density and turn-off loss without affecting its turn-on voltage, breakdown voltage and latch current density. In addition, the reduction of the current density can reduce the failure probability of the short circuit test of the insulated gate bipolar transistor and improve the yield of the device. Moreover, due to the reduction of the closing loss, when the device is turned off, the flowing carrier can be rapidly reduced, so that the switching time of the device can be further shortened, and the performance of the device is greatly improved.

Although the embodiments of the present invention and its advantages are disclosed above, it should be understood that those skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the invention. In addition, the scope of the present invention is not limited to the processes, machines, manufacture, compositions, devices, methods, and steps in the specific embodiments described in the specification. Any one of ordinary skill in the art can. The processes, machines, fabrications, compositions, devices, methods, and procedures that are presently or in the future are understood to be used in accordance with the present invention as long as they can perform substantially the same function or achieve substantially the same results in the embodiments described herein. Accordingly, the scope of the invention includes the above-described processes, machines, manufactures, compositions, devices, methods, and steps. In addition, the scope of each of the claims constitutes an individual embodiment, and the scope of the invention also includes the combination of the scope of the application and the embodiments.

100‧‧‧Substrate

100A‧‧‧Upper surface

100B‧‧‧ lower surface

110‧‧‧First emitter area/layer

130‧‧‧ gate structure

130P‧‧‧Horizontal gate section

130V‧‧‧vertical gate

160‧‧‧ gate dielectric layer

170‧‧‧gate electrode

180‧‧‧second emitter area

190‧‧‧Interlayer dielectric layer

200‧‧‧Contact opening

210‧‧‧The third emitter area

220‧‧ ‧ emitter electrode

250‧‧‧ heavily doped buffer layer

260‧‧‧ Collector Zone/Layer

255/270‧‧‧First Conductive Drift Zone/Layer

280‧‧ ‧ collector electrode

300‧‧‧Insulated gate bipolar transistor

S1‧‧‧ first side

S2‧‧‧ second side

W1‧‧‧Width

W2‧‧‧Width

Claims (15)

An insulated gate bipolar transistor includes: a collector electrode; a collector layer electrically connected to the collector electrode and having a second conductivity type; and a first conductivity type drift layer disposed on the collector a layer, wherein the first conductivity type is different from the second conductivity type; a first emitter layer is disposed on the first conductivity type drift layer and has the second conductivity type; a trench Extending from the surface of the first emitter layer into the first conductive type drift layer, wherein the trench has a first side and a second side opposite to each other; a gate electrode is filled in the trench and extends On the surface of the first emitter layer, wherein the gate electrodes on the first side and the second side have different extension distances on the surface of the first emitter layer; a gate dielectric layer is provided Between the gate electrode and the trench, and between the gate electrode and the first emitter layer; a second emitter region disposed in the first emitter layer on both sides of the gate electrode The second emitter region has the first conductivity type; an interlayer dielectric layer is disposed on the first emitter layer; and an emitter electrode, and A first emitter layer and the second radio of region coupling, wherein the interlayer dielectric layer system is provided on the gate electrode and the emission between the source electrode. The insulated gate bipolar transistor of claim 1, wherein the second emitter region on the second side of the trench directly contacts the trench. An insulated gate bipolar transistor according to claim 1 of the patent application, The second emitter region located on the first side of the trench is spaced apart from the trench by a width that is 0.05-0.2 times the width of the first emitter region. The insulated gate bipolar transistor of claim 1, wherein the gate electrode on the second side has a distance of zero on a surface of the first emitter layer. The insulated gate bipolar transistor of claim 1, wherein the gate electrode comprises amorphous germanium, a germanium germanium or a combination thereof. The insulated gate bipolar transistor according to claim 1, further comprising a heavily doped buffer layer having the first conductivity type and disposed between the first conductivity type drift layer and the collector layer. A method for manufacturing an insulated gate bipolar transistor, comprising: providing a substrate having a first conductivity type and having an upper surface and a lower surface; forming a first emitter region having a second conductivity type, and Extending from the upper surface of the substrate into the substrate, and the second conductivity type is different from the first conductivity type; forming a trench extending from the upper surface of the substrate through the first emitter region to the In the substrate, the trench has a first side and a second side opposite to each other; a gate structure is formed, including a gate dielectric layer and a gate electrode, wherein the gate electrode is filled in the trench And extending to the upper surface of the substrate, wherein the gate electrodes on the first side and the second side have different extension distances on the upper surface of the substrate, and the gate dielectric layer is disposed on the gate Between the electrode and the trench, and between the gate electrode and the first emitter region; Forming a second emitter region in the first emitter region on both sides of the gate electrode, wherein the second emitter region has the first conductivity type; forming an interlayer dielectric layer on the gate electrode; Forming an emitter electrode, the emitter electrode is electrically connected to the first emitter region and the second emitter region, and the interlayer dielectric layer is disposed between the gate electrode and the emitter electrode; forming a a collector region having the second conductivity type and extending into the substrate from a lower surface of the substrate, wherein the substrate is not formed with the first emitter region, the second emitter region, and a portion of the collector region As a first conductivity type drift region; and forming a collector electrode, the collector electrode is electrically connected to the collector region. The method for fabricating an insulated gate bipolar transistor according to claim 7, wherein the method for forming the gate structure comprises: forming a dielectric material layer on a sidewall and a bottom of the trench and the substrate Forming a conductive layer on the dielectric material layer and filling the trench; and patterning the dielectric material layer and the conductive layer to form the gate dielectric layer and the gate electrode, respectively . The method of fabricating an insulated gate bipolar transistor according to claim 7, wherein the second emitter region on the second side of the trench directly contacts the trench. The method for manufacturing an insulated gate bipolar transistor according to claim 7, wherein the second emitter region on the first side of the trench is spaced apart from the trench by a width, the width being the first The width of the emitter area is 0.05-0.2 Times. The method of manufacturing an insulated gate bipolar transistor according to claim 7, wherein the gate electrode on the second side has an extension distance of 0 on the upper surface of the substrate. The method of manufacturing an insulated gate bipolar transistor according to claim 7, wherein the gate electrode comprises an amorphous germanium, a germanium germanium or a combination thereof. The method for manufacturing an insulated gate bipolar transistor according to claim 7, further comprising forming a heavily doped buffer layer between the first conductivity type drift region and the collector region, wherein the heavily doped The buffer layer has the first conductivity type. A method for fabricating an insulated gate bipolar transistor includes: providing a substrate having a second conductivity type, wherein the substrate serves as a collector region; forming an epitaxial layer on the substrate, the epitaxial layer having a first conductivity type, and the first conductivity type is different from the second conductivity type; forming a first emitter region extending from the surface of the epitaxial layer into the epitaxial layer and having the second conductivity type Forming a trench extending from the surface of the first emitter region through the first emitter region to the epitaxial layer, wherein the trench has a first side and a second side opposite; Forming a gate structure including a gate dielectric layer and a gate electrode, wherein the gate electrode is filled in the trench and extends to a surface of the first emitter region, wherein the first side and the gate The gate electrode of the second side is in the first emitter region The extension distance on the surface is different, and the gate dielectric layer is disposed between the gate electrode and the trench, and between the gate electrode and the first emitter region; forming a second emitter region In the first emitter region on both sides of the gate electrode, wherein the second emitter region has the first conductivity type, wherein the epitaxial layer is not formed with the first emitter region and the second emitter a portion of the region serves as a first conductivity type drift region; an interlayer dielectric layer is formed on the gate electrode; an emitter electrode is formed, the emitter electrode and the first emitter region, the second emitter region Electrically connected, and the interlayer dielectric layer is disposed between the gate electrode and the emitter electrode; and a collector electrode is electrically connected to the collector region. The method for manufacturing an insulated gate bipolar transistor according to claim 14, further comprising forming a heavily doped buffer layer on the substrate before the epitaxial layer, wherein the heavily doped buffer layer has the The first conductivity type.