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US20140110777A1 - Trench gate metal oxide semiconductor field effect transistor and fabricating method thereof - Google Patents

Trench gate metal oxide semiconductor field effect transistor and fabricating method thereof Download PDF

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Publication number
US20140110777A1
US20140110777A1 US13/654,432 US201213654432A US2014110777A1 US 20140110777 A1 US20140110777 A1 US 20140110777A1 US 201213654432 A US201213654432 A US 201213654432A US 2014110777 A1 US2014110777 A1 US 2014110777A1
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Prior art keywords
trench
layer
substrate
field effect
effect transistor
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US13/654,432
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Chun-Hong Peng
Yu-Hsi LAI
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US13/654,432 priority Critical patent/US20140110777A1/en
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LAI, YU-HSI, PENG, Chun-hong
Publication of US20140110777A1 publication Critical patent/US20140110777A1/en
Priority to US14/754,636 priority patent/US9525037B2/en
Abandoned legal-status Critical Current

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    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/663—Vertical DMOS [VDMOS] FETs having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS
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    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
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Definitions

  • the present invention relates to a semiconductor device and a fabricating method thereof, and more particularly to a trench gate metal oxide semiconductor field effect transistor and a fabricating method thereof.
  • a conventional trench gate metal oxide semiconductor field effect transistor comprises a gate structure, which is disposed within a trench.
  • a trench is firstly formed in a semiconductor substrate, and then a gate dielectric layer is formed on a sidewall of the trench by thermal oxidation. Then, a polysilicon semiconductor material is filled into the trench. After a planarization process is performed, a polysilicon gate is formed in the trench.
  • the size of the polysilicon gate is reduced.
  • a metal contact plug is formed on the polysilicon gate in the subsequent process.
  • the size reduction of the polysilicon gate may result in misalignment between the polysilicon gate and the metal contact plug. If the metal contact plug is deviated because of misalignment, the metal contact plug and the neighboring circuits may be suffered from charge breakdown.
  • the present invention provides a trench gate metal oxide semiconductor field effect transistor.
  • the trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate.
  • the substrate has a trench.
  • the trench is extended downwardly from a surface of the substrate.
  • the gate includes an insertion portion and a symmetrical protrusion portion.
  • the insertion portion is embedded in the trench.
  • the symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.
  • the symmetrical protrusion portion is wider than the trench.
  • the gate is a T-shaped gate, which is symmetrical with respect to a central line of the trench.
  • the trench has a width smaller than or equal to 0.8 ⁇ m and a depth of about 1.6 ⁇ m.
  • the trench gate metal oxide semiconductor field effect transistor includes a dielectric material layer and a contact plug.
  • the dielectric material layer is disposed over the surface of the substrate and the gate.
  • the contact plug is penetrated through the dielectric material layer and electrically contacted with the symmetrical protrusion portion of the gate.
  • the trench gate metal oxide semiconductor field effect transistor includes a first-conductive doped region, a second-conductive doped region, a gate dielectric layer, and a source region.
  • the first-conductive doped region is formed in the substrate.
  • the second-conductive doped region is formed in the substrate.
  • a P/N junction is formed between the first-conductive doped region and the second-conductive doped region.
  • the trench is extended downwardly from the surface of the trench, penetrated through the first-conductive doped region and the P/N junction, and inserted into the second-conductive doped region.
  • the gate dielectric layer is formed on a sidewall of the trench.
  • the source region is formed in the substrate and located beside the gate dielectric layer.
  • the first-conductive doped region is a P-type body region
  • the second-conductive doped region is an N-type well region
  • the trench gate metal oxide semiconductor field effect transistor further includes an N-type buried layer, which is disposed under the second-conductive doped region.
  • the source region is an N-type well region, and the source region is extended from the surface of the substrate into the first-conductive doped region.
  • the present invention provides a method for fabricating a trench gate metal oxide semiconductor field effect transistor.
  • the method includes the following steps. Firstly, a substrate is provided. Then, a hard mask layer is formed on the substrate. Then, an etching process is performed to remove a part of the hard mask layer and form a trench in the substrate. Then, an etching back process is performed to remove a part of the hard mask layer. Then, a conductive layer is formed on the hard mask layer and filled into the trench. Then, a planarization process is performed to remove the conductive layer by using the hard mask layer as a stop layer.
  • the method before the hard mask layer is formed, the method further includes a step of forming a pad silicon oxide layer on the substrate.
  • the method further includes a step of forming a sacrificial layer on the hard mask layer.
  • the method before the conductive layer is formed, the method further comprises a step of forming a gate dielectric layer on a sidewall of the trench by a thermal oxidation process.
  • the hard mask layer is a silicon oxide layer or a silicon nitride layer.
  • FIGS. 1A ⁇ 1F are schematic cross-sectional views illustrating a method for fabricating a trench gate metal oxide semiconductor field effect transistor according to an embodiment of the present invention
  • FIGS. 2A ⁇ 2E are schematic cross-sectional views illustrating a method for fabricating a trench gate metal oxide semiconductor field effect transistor according to another embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view illustrating an optional step of the method for fabricating the trench gate metal oxide semiconductor field effect transistor of the present invention.
  • FIGS. 1A ⁇ 1F are schematic cross-sectional views illustrating a method for fabricating a trench gate metal oxide semiconductor field effect transistor according to an embodiment of the present invention.
  • the method for fabricating the trench gate metal oxide semiconductor field effect transistor 100 comprises the following steps.
  • a substrate 101 is provided.
  • the substrate 101 is a silicon substrate.
  • the substrate 101 comprises a first-conductive doped region 101 a , a second-conductive doped region 101 b , a source region 120 , and a second-conductive deep well region 101 c.
  • the first-conductive doped region 101 a , the second-conductive doped region 101 b , the source region 120 and the second-conductive deep well region 101 c are formed in the substrate 101 by a plurality of ion implantation processes.
  • the second-conductive doped region 101 b is formed in the substrate 101 .
  • the first-conductive doped region 101 a is disposed over the second-conductive doped region 101 b , and extended downwardly from a surface 101 d of the substrate 101 to be contacted with the second-conductive doped region 101 b . Consequently, a P/N junction 102 is formed between the first-conductive doped region 101 a and the second-conductive doped region 101 b .
  • the source region 120 is extended downwardly from the surface 101 d of the substrate 101 , and formed in the first-conductive doped region 101 a .
  • the second-conductive deep well region 101 c is formed in the substrate 101 , and extended downwardly from the surface 101 d of the substrate 101 , serving as the drain of the trench gate metal oxide semiconductor field effect transistor 100 .
  • the second-conductive deep well region 101 c is contacted with the second-conductive doped region 101 b .
  • a buried layer 119 with the same conductivity as the second-conductive doped region 101 b is disposed under the second-conductive doped region 101 b.
  • the second-conductive doped region 101 b is an N-type well region with a lower dopant concentration.
  • the first-conductive doped region 101 a is a P-type body region.
  • the source region 120 is an N-type well region with a higher dopant concentration.
  • the second-conductive deep well region 101 c is an N-type deep well region.
  • the second-conductive deep well region 101 c is isolated from the first-conductive doped region 101 a through a shallow trench isolation structure 103 .
  • the buried layer 119 is an N-type doped region with a higher dopant concentration.
  • the buried layer 119 is disposed under the second-conductive doped region 101 b and contacted with the second-conductive deep well region 101 c .
  • an N-type well region 101 e with a dopant concentration greater than that of the N-type (second-conductive) deep well region 101 c maybe formed in the N-type (second-conductive) deep well region 101 c , and extended downwardly from the surface 101 d of the substrate 101 .
  • a pad silicon oxide layer 104 , a hard mask layer 105 and a patterned photoresist layer 106 are formed on the surface 101 d of the substrate 101 to cover the second-conductive deep well region 101 c , the source region 120 and the first-conductive doped region 101 a .
  • the hard mask layer 105 is made of silicon nitride.
  • the hard mask layer 105 may be made of silicon oxide.
  • an etching process 107 is performed to remove a part of the hard mask layer 105 , a part of the pad silicon oxide layer 104 and a part of the substrate 101 . Consequently, a trench 108 is formed in the substrate 101 .
  • the trench 108 is extended downwardly from the surface 101 d of the substrate 101 , penetrated through the source region 120 , and extended into the second-conductive doped region 101 b .
  • the etching process 107 is a dry etching process.
  • the trench 108 has a width smaller than or equal to 0.8 ⁇ m and a depth of about 1.6 ⁇ m.
  • a thermal oxidation process is performed to form a gate dielectric layer 109 on a sidewall 108 a of the trench 108 (see FIG. 1D ).
  • a conductive layer preferably a polysilicon layer 110
  • a planarization process 111 is performed to partially remove the polysilicon layer 110 .
  • a patterned photoresist layer 112 is formed on the polysilicon layer 110 .
  • another etching process 113 is performed to remove a part of the planarized polysilicon layer 110 . Consequently, a T-shaped portion of the planarized polysilicon layer 110 is remained and serves as a T-shaped polysilicon gate 114 of the trench gate metal oxide semiconductor field effect transistor 100 (see FIG. 1E ).
  • the T-shaped polysilicon gate 114 comprises an insertion portion 114 a and a protrusion portion 114 b .
  • the insertion portion 114 a is embedded in the trench 108 .
  • the protrusion portion 114 b is protruded over the surface 101 d of the substrate 101 and externally and transversely extended from a central line 108 b of the trench 108 .
  • a metal interconnection process is performed. Consequently, a dielectric material layer 117 is firstly formed over the surface 101 d of the substrate 101 and the polysilicon gate 114 , and then a plurality of metal contact plugs 118 are formed in the dielectric material layer 117 . Meanwhile, the trench gate metal oxide semiconductor field effect transistor 100 is produced. The resulting structure of the trench gate metal oxide semiconductor field effect transistor 100 is shown in FIG. 1F .
  • the transversely-extending width of the protrusion portion 114 b is greater than the width of the insertion portion 114 a . Consequently, the protrusion portion 114 b can provide a larger process window for the subsequently forming of the metal contact plug 118 on the polysilicon gate 114 .
  • the above-mentioned method for fabricating the trench gate metal oxide semiconductor field effect transistor 100 still has some drawbacks. For example, since two photolithography and etching processes are required to form the polysilicon gate 114 , every misalignment error of the photomask may further decrease the alignment accuracy. Moreover, during the performing of the etching process 113 , the surface 101 d of the substrate 101 is still completely covered by the planarized polysilicon layer 110 . Since the alignment mark for the etching process 113 is possibly hindered by the planarized polysilicon layer 110 , the misalignment error of the photomask is thereby increased.
  • the protrusion portion 114 b of the polysilicon gate 114 may be unexpectedly and asymmetrically extended in the transverse direction. If the (alignment) process errors in the process of forming the metal contact plug 118 are taken into consideration, the total cumulative misalignment error of the semiconductor device is very large. Under this circumstance, the metal contact plug 118 and the neighboring circuits may be suffered from charge breakdown.
  • the method of forming the polysilicon gate 114 needs to be further improved.
  • FIGS. 2A ⁇ 2E are schematic cross-sectional views illustrating a method for fabricating a trench gate metal oxide semiconductor field effect transistor according to another embodiment of the present invention.
  • the method for fabricating the trench gate metal oxide semiconductor field effect transistor 200 comprises the following steps.
  • FIGS. 1A , 1 B and 1 C are sequentially performed.
  • the trench 108 is formed (see FIG. 1C )
  • the remaining hard mask layer 105 is not removed immediately.
  • an etching back process 215 is performed to remove the patterned photoresist layer 106 and a part of the hard mask layer 105 , and a part of the pad silicon oxide layer 104 at an entrance 108 c of the trench 108 that is exposed.
  • the hard mask layer 105 is made of silicon nitride, and the etching back process 215 is a wet etching process by using a phosphoric acid solution as an etchant solution to remove a part of the hard mask layer 105 .
  • the hard mask layer 105 is made of silicon dioxide, and the etching back process 215 is a wet etching process by using a buffer oxide etcher (BOE) solution as an etchant solution to remove a part of the hard mask layer 105 .
  • BOE buffer oxide etcher
  • another silicon dioxide layer 316 may be optionally formed on the hard mask layer 105 (see FIG. 3 ).
  • the silicon dioxide layer 316 is served as a sacrificial layer for the etching back process 215 in order to adjust the etching depth and range of the etching back process 215 .
  • a thermal oxidation process is performed to form a gate dielectric layer 109 on a sidewall 108 a of the trench 108 (see FIG. 2B ).
  • a polysilicon layer 110 is formed on the remaining hard mask layer 105 and the exposed pad silicon oxide layer 104 , and filled into the trench 108 .
  • a planarization process 111 e.g. a chemical mechanical polishing process
  • a planarization process 111 is performed to remove the polysilicon layer 110 by using the hard mask layer 105 as a polish stop layer.
  • a T-shaped polysilicon gate 214 is formed (see FIG. 2D ).
  • the T-shaped polysilicon gate 214 is configured symmetrical with respect to a central line 108 b of the trench 108 .
  • the T-shaped polysilicon gate 214 comprises an insertion portion 214 a and a symmetrical protrusion portion 214 b .
  • the insertion portion 214 a is embedded in the trench 108 .
  • the symmetrical protrusion portion 214 b is protruded over the surface 101 d of the substrate 101 , symmetrical with respect to the central line 108 b of the trench 108 , and externally and transversely extended from the central line 108 b of the trench 108 .
  • a metal interconnection process is performed. Consequently, a dielectric material layer 117 is firstly formed over the surface 101 d of the substrate 101 and the polysilicon gate 214 , and then a plurality of metal contact plugs 118 are formed in the dielectric material layer 117 . Meanwhile, the trench gate metal oxide semiconductor field effect transistor 200 is produced. The resulting structure of the trench gate metal oxide semiconductor field effect transistor 200 is shown in FIG. 2E .
  • the structure of the polysilicon gate 214 of the trench gate metal oxide semiconductor field effect transistor 200 is improved in comparison to the trench gate MOSFET 100 shown in FIGS. 1A-1F .
  • a part of the hard mask layer 105 at the entrance 108 c of the trench 108 is firstly removed by an etching back process (e.g. an anisotropic etching process) (see FIG. 2A ), then the polysilicon layer 110 is filled into the trench 108 , and finally a planarization process is performed.
  • an etching back process e.g. an anisotropic etching process
  • the symmetrical protrusion portion 214 b of the polysilicon gate 214 can be symmetrically configured with respect to the central line 108 b of the trench 108 and transversely extended from the central line 108 b of the trench 108 (see FIG. 2D ).
  • the symmetrical protrusion portion 114 b can provide a larger process window for subsequently forming of the metal contact plug 118 on the polysilicon gate 214 . Consequently, even if the feature size of the semiconductor device is shrunken down, the misalignment error thereof will be largely reduced.
  • the fabricating method of the present invention only a single photolithography and etching process is sufficient to form a polysilicon gate, instead of requiring two photolithography and etching processes to form the same. Consequently, the fabricating method of the present invention is simplified, the photomask number is reduced, and the misalignment error of the semiconductor device is largely reduced. Since the misalignment error is largely reduced, the symmetrical protrusion portion of the polysilicon gate is no longer unexpectedly and asymmetrically extended in the transverse direction, and the total cumulative misalignment error of the semiconductor device is reduced.
  • the symmetrical protrusion portion of the polysilicon gate can provide a larger process window for subsequently forming the metal contact plug on the polysilicon gate. Consequently, even if the feature size of the device is shrunken down, the misalignment error will be largely reduced.
  • the symmetrical protrusion portion of the polysilicon gate is formed by etching back the hard mask layer to widen the entrance of the trench and then filling the polysilicon layer. Consequently, it is not necessary to perform an additional photolithography and etching process. In other words, the fabricating method of the present invention is simplified and cost-effective. Since it is not necessary to repeatedly use the photomask for alignment, the precision of the alignment between the metal contact plug and the polysilicon gate is enhanced.

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Abstract

A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly to a trench gate metal oxide semiconductor field effect transistor and a fabricating method thereof.
    • BACKGROUND OF THE INVENTION
  • A conventional trench gate metal oxide semiconductor field effect transistor comprises a gate structure, which is disposed within a trench. For fabricating the conventional trench gate metal oxide semiconductor field effect transistor, a trench is firstly formed in a semiconductor substrate, and then a gate dielectric layer is formed on a sidewall of the trench by thermal oxidation. Then, a polysilicon semiconductor material is filled into the trench. After a planarization process is performed, a polysilicon gate is formed in the trench.
  • Recently, since the integrated circuit becomes more complicated, the feature size and wiring space of the semiconductor device are gradually decreased, and the size of the polysilicon gate is reduced. After the polysilicon gate is formed, a metal contact plug is formed on the polysilicon gate in the subsequent process. As known, the size reduction of the polysilicon gate may result in misalignment between the polysilicon gate and the metal contact plug. If the metal contact plug is deviated because of misalignment, the metal contact plug and the neighboring circuits may be suffered from charge breakdown.
  • Therefore, there is a need of providing an improved trench gate metal oxide semiconductor field effect transistor and a fabricating method thereof in order to obviate the drawbacks encountered from the prior art.
    • SUMMARY OF THE INVENTION
  • In accordance with an aspect, the present invention provides a trench gate metal oxide semiconductor field effect transistor. The trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.
  • In an embodiment, the symmetrical protrusion portion is wider than the trench.
  • In an embodiment, the gate is a T-shaped gate, which is symmetrical with respect to a central line of the trench.
  • In an embodiment, the trench has a width smaller than or equal to 0.8 μm and a depth of about 1.6 μm.
  • In an embodiment, the trench gate metal oxide semiconductor field effect transistor includes a dielectric material layer and a contact plug. The dielectric material layer is disposed over the surface of the substrate and the gate. The contact plug is penetrated through the dielectric material layer and electrically contacted with the symmetrical protrusion portion of the gate.
  • In an embodiment, the trench gate metal oxide semiconductor field effect transistor includes a first-conductive doped region, a second-conductive doped region, a gate dielectric layer, and a source region. The first-conductive doped region is formed in the substrate. The second-conductive doped region is formed in the substrate. A P/N junction is formed between the first-conductive doped region and the second-conductive doped region. The trench is extended downwardly from the surface of the trench, penetrated through the first-conductive doped region and the P/N junction, and inserted into the second-conductive doped region. The gate dielectric layer is formed on a sidewall of the trench. The source region is formed in the substrate and located beside the gate dielectric layer.
  • In an embodiment, the first-conductive doped region is a P-type body region, and the second-conductive doped region is an N-type well region.
  • In an embodiment, the trench gate metal oxide semiconductor field effect transistor further includes an N-type buried layer, which is disposed under the second-conductive doped region.
  • In an embodiment, the source region is an N-type well region, and the source region is extended from the surface of the substrate into the first-conductive doped region.
  • In accordance with an aspect, the present invention provides a method for fabricating a trench gate metal oxide semiconductor field effect transistor. The method includes the following steps. Firstly, a substrate is provided. Then, a hard mask layer is formed on the substrate. Then, an etching process is performed to remove a part of the hard mask layer and form a trench in the substrate. Then, an etching back process is performed to remove a part of the hard mask layer. Then, a conductive layer is formed on the hard mask layer and filled into the trench. Then, a planarization process is performed to remove the conductive layer by using the hard mask layer as a stop layer.
  • In an embodiment, before the hard mask layer is formed, the method further includes a step of forming a pad silicon oxide layer on the substrate.
  • In an embodiment, after the hard mask layer is formed, the method further includes a step of forming a sacrificial layer on the hard mask layer.
  • In an embodiment, before the conductive layer is formed, the method further comprises a step of forming a gate dielectric layer on a sidewall of the trench by a thermal oxidation process.
  • In an embodiment, the hard mask layer is a silicon oxide layer or a silicon nitride layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
  • FIGS. 1A˜1F are schematic cross-sectional views illustrating a method for fabricating a trench gate metal oxide semiconductor field effect transistor according to an embodiment of the present invention;
  • FIGS. 2A˜2E are schematic cross-sectional views illustrating a method for fabricating a trench gate metal oxide semiconductor field effect transistor according to another embodiment of the present invention; and
  • FIG. 3 is a schematic cross-sectional view illustrating an optional step of the method for fabricating the trench gate metal oxide semiconductor field effect transistor of the present invention.
    •  DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
  • FIGS. 1A˜1F are schematic cross-sectional views illustrating a method for fabricating a trench gate metal oxide semiconductor field effect transistor according to an embodiment of the present invention. The method for fabricating the trench gate metal oxide semiconductor field effect transistor 100 comprises the following steps.
  • Firstly, as shown in FIG. 1A, a substrate 101 is provided. In an embodiment, the substrate 101 is a silicon substrate. In addition, the substrate 101 comprises a first-conductive doped region 101 a, a second-conductive doped region 101 b, a source region 120, and a second-conductive deep well region 101 c.
  • The first-conductive doped region 101 a, the second-conductive doped region 101 b, the source region 120 and the second-conductive deep well region 101 c are formed in the substrate 101 by a plurality of ion implantation processes. The second-conductive doped region 101 b is formed in the substrate 101. The first-conductive doped region 101 a is disposed over the second-conductive doped region 101 b, and extended downwardly from a surface 101 d of the substrate 101 to be contacted with the second-conductive doped region 101 b. Consequently, a P/N junction 102 is formed between the first-conductive doped region 101 a and the second-conductive doped region 101 b. The source region 120 is extended downwardly from the surface 101 d of the substrate 101, and formed in the first-conductive doped region 101 a. The second-conductive deep well region 101 c is formed in the substrate 101, and extended downwardly from the surface 101 d of the substrate 101, serving as the drain of the trench gate metal oxide semiconductor field effect transistor 100. Moreover, the second-conductive deep well region 101 c is contacted with the second-conductive doped region 101 b. Furthermore, a buried layer 119 with the same conductivity as the second-conductive doped region 101 b is disposed under the second-conductive doped region 101 b.
  • In this embodiment, the second-conductive doped region 101 b is an N-type well region with a lower dopant concentration. The first-conductive doped region 101 a is a P-type body region. The source region 120 is an N-type well region with a higher dopant concentration. The second-conductive deep well region 101 c is an N-type deep well region. The second-conductive deep well region 101 c is isolated from the first-conductive doped region 101 a through a shallow trench isolation structure 103. The buried layer 119 is an N-type doped region with a higher dopant concentration. The buried layer 119 is disposed under the second-conductive doped region 101 b and contacted with the second-conductive deep well region 101 c. Preferably, an N-type well region 101 e with a dopant concentration greater than that of the N-type (second-conductive) deep well region 101 c, maybe formed in the N-type (second-conductive) deep well region 101 c, and extended downwardly from the surface 101 d of the substrate 101.
  • Then, as shown in FIG. 1B, by film deposition processes or any other suitable processes, a pad silicon oxide layer 104, a hard mask layer 105 and a patterned photoresist layer 106 are formed on the surface 101 d of the substrate 101 to cover the second-conductive deep well region 101 c, the source region 120 and the first-conductive doped region 101 a. For example, the hard mask layer 105 is made of silicon nitride. Alternatively, the hard mask layer 105 may be made of silicon oxide.
  • Then, as shown in FIG. 1C, by using the patterned photoresist layer 106 as an etching mask, an etching process 107 is performed to remove a part of the hard mask layer 105, a part of the pad silicon oxide layer 104 and a part of the substrate 101. Consequently, a trench 108 is formed in the substrate 101. The trench 108 is extended downwardly from the surface 101 d of the substrate 101, penetrated through the source region 120, and extended into the second-conductive doped region 101 b. For example, the etching process 107 is a dry etching process. The trench 108 has a width smaller than or equal to 0.8 μm and a depth of about 1.6 μm.
  • After the patterned photoresist layer 106 and the remaining hard mask layer 105 are removed, a thermal oxidation process is performed to form a gate dielectric layer 109 on a sidewall 108 a of the trench 108 (see FIG. 1D). Then, a conductive layer, preferably a polysilicon layer 110, is formed on the pad silicon oxide layer 104, and filled into the trench 108. Then, a planarization process 111 (e.g. a chemical mechanical polishing process) is performed to partially remove the polysilicon layer 110.
  • After the planarization process 111 is performed, a patterned photoresist layer 112 is formed on the polysilicon layer 110. By using the pad silicon oxide layer 104 as an etch stop layer, another etching process 113 is performed to remove a part of the planarized polysilicon layer 110. Consequently, a T-shaped portion of the planarized polysilicon layer 110 is remained and serves as a T-shaped polysilicon gate 114 of the trench gate metal oxide semiconductor field effect transistor 100(see FIG. 1E). The T-shaped polysilicon gate 114 comprises an insertion portion 114 a and a protrusion portion 114 b. The insertion portion 114 a is embedded in the trench 108. The protrusion portion 114 b is protruded over the surface 101 d of the substrate 101 and externally and transversely extended from a central line 108 b of the trench 108.
  • Then, a metal interconnection process is performed. Consequently, a dielectric material layer 117 is firstly formed over the surface 101 d of the substrate 101 and the polysilicon gate 114, and then a plurality of metal contact plugs 118 are formed in the dielectric material layer 117. Meanwhile, the trench gate metal oxide semiconductor field effect transistor 100 is produced. The resulting structure of the trench gate metal oxide semiconductor field effect transistor 100 is shown in FIG. 1F.
  • Please refer to FIG. 1F again. In the T-shaped polysilicon gate 114, the transversely-extending width of the protrusion portion 114 b is greater than the width of the insertion portion 114 a. Consequently, the protrusion portion 114 b can provide a larger process window for the subsequently forming of the metal contact plug 118 on the polysilicon gate 114.
  • However, the above-mentioned method for fabricating the trench gate metal oxide semiconductor field effect transistor 100 still has some drawbacks. For example, since two photolithography and etching processes are required to form the polysilicon gate 114, every misalignment error of the photomask may further decrease the alignment accuracy. Moreover, during the performing of the etching process 113, the surface 101 d of the substrate 101 is still completely covered by the planarized polysilicon layer 110. Since the alignment mark for the etching process 113 is possibly hindered by the planarized polysilicon layer 110, the misalignment error of the photomask is thereby increased. Due to the misalignment error of the photomask, the protrusion portion 114 b of the polysilicon gate 114 may be unexpectedly and asymmetrically extended in the transverse direction. If the (alignment) process errors in the process of forming the metal contact plug 118 are taken into consideration, the total cumulative misalignment error of the semiconductor device is very large. Under this circumstance, the metal contact plug 118 and the neighboring circuits may be suffered from charge breakdown.
  • For solving the above drawbacks, the method of forming the polysilicon gate 114 needs to be further improved.
  • FIGS. 2A˜2E are schematic cross-sectional views illustrating a method for fabricating a trench gate metal oxide semiconductor field effect transistor according to another embodiment of the present invention. The method for fabricating the trench gate metal oxide semiconductor field effect transistor 200 comprises the following steps.
  • Firstly, the steps as shown in FIGS. 1A, 1B and 1C are sequentially performed. After the trench 108 is formed (see FIG. 1C), the remaining hard mask layer 105 is not removed immediately. On the other hand, as shown in FIG. 2A according to the embodiment of present invention, after the patterned photoresist layer 106 is removed, an etching back process 215 is performed to remove the patterned photoresist layer 106 and a part of the hard mask layer 105, and a part of the pad silicon oxide layer 104 at an entrance 108 c of the trench 108 that is exposed. In an embodiment, the hard mask layer 105 is made of silicon nitride, and the etching back process 215 is a wet etching process by using a phosphoric acid solution as an etchant solution to remove a part of the hard mask layer 105. Alternatively, in another embodiment, the hard mask layer 105 is made of silicon dioxide, and the etching back process 215 is a wet etching process by using a buffer oxide etcher (BOE) solution as an etchant solution to remove a part of the hard mask layer 105.
  • Furthermore, for improved control of the etching back process 215, before the patterned photoresist layer 106 is formed, another silicon dioxide layer 316 may be optionally formed on the hard mask layer 105 (see FIG. 3). The silicon dioxide layer 316 is served as a sacrificial layer for the etching back process 215 in order to adjust the etching depth and range of the etching back process 215.
  • Then, a thermal oxidation process is performed to form a gate dielectric layer 109 on a sidewall 108 a of the trench 108 (see FIG. 2B). Then, as shown in FIG. 2C, a polysilicon layer 110 is formed on the remaining hard mask layer 105 and the exposed pad silicon oxide layer 104, and filled into the trench 108.
  • Then, a planarization process 111 (e.g. a chemical mechanical polishing process) is performed to remove the polysilicon layer 110 by using the hard mask layer 105 as a polish stop layer. After the remaining hard mask layer 105 is removed, a T-shaped polysilicon gate 214 is formed (see FIG. 2D). The T-shaped polysilicon gate 214 is configured symmetrical with respect to a central line 108 b of the trench 108. The T-shaped polysilicon gate 214 comprises an insertion portion 214 a and a symmetrical protrusion portion 214 b. The insertion portion 214 a is embedded in the trench 108. The symmetrical protrusion portion 214 b is protruded over the surface 101 d of the substrate 101, symmetrical with respect to the central line 108 b of the trench 108, and externally and transversely extended from the central line 108 b of the trench 108.
  • Then, a metal interconnection process is performed. Consequently, a dielectric material layer 117 is firstly formed over the surface 101 d of the substrate 101 and the polysilicon gate 214, and then a plurality of metal contact plugs 118 are formed in the dielectric material layer 117. Meanwhile, the trench gate metal oxide semiconductor field effect transistor 200 is produced. The resulting structure of the trench gate metal oxide semiconductor field effect transistor 200 is shown in FIG. 2E.
  • From the above discussions, the structure of the polysilicon gate 214 of the trench gate metal oxide semiconductor field effect transistor 200 is improved in comparison to the trench gate MOSFET 100 shown in FIGS. 1A-1F. For forming the polysilicon gate 214, a part of the hard mask layer 105 at the entrance 108 c of the trench 108 is firstly removed by an etching back process (e.g. an anisotropic etching process) (see FIG. 2A), then the polysilicon layer 110 is filled into the trench 108, and finally a planarization process is performed. Consequently, the symmetrical protrusion portion 214 b of the polysilicon gate 214 can be symmetrically configured with respect to the central line 108 b of the trench 108 and transversely extended from the central line 108 b of the trench 108 (see FIG. 2D). The symmetrical protrusion portion 114 b can provide a larger process window for subsequently forming of the metal contact plug 118 on the polysilicon gate 214. Consequently, even if the feature size of the semiconductor device is shrunken down, the misalignment error thereof will be largely reduced.
  • Moreover, according to the embodiments of the fabricating method of the present invention, only a single photolithography and etching process is sufficient to form a polysilicon gate, instead of requiring two photolithography and etching processes to form the same. Consequently, the fabricating method of the present invention is simplified, the photomask number is reduced, and the misalignment error of the semiconductor device is largely reduced. Since the misalignment error is largely reduced, the symmetrical protrusion portion of the polysilicon gate is no longer unexpectedly and asymmetrically extended in the transverse direction, and the total cumulative misalignment error of the semiconductor device is reduced.
  • From the above discussions, the present invention provides a trench gate metal oxide semiconductor field effect transistor and a fabricating method thereof. The fabricating method comprises the following steps. Firstly, a substrate is provided. Then, a hard mask layer is formed on the substrate. Then, an etching process is performed to remove a part of the hard mask layer and form a trench in the substrate. Then, an etching back process is performed to remove a part of the hard mask layer. Then, a polysilicon layer is formed on the hard mask layer and filled into the trench. Then, by using the hard mask layer as a stop layer, a planarization process is performed to remove the polysilicon layer. Consequently, a polysilicon gate with the symmetrical protrusion portion is formed.
  • The symmetrical protrusion portion of the polysilicon gate can provide a larger process window for subsequently forming the metal contact plug on the polysilicon gate. Consequently, even if the feature size of the device is shrunken down, the misalignment error will be largely reduced.
  • From the above descriptions, the symmetrical protrusion portion of the polysilicon gate is formed by etching back the hard mask layer to widen the entrance of the trench and then filling the polysilicon layer. Consequently, it is not necessary to perform an additional photolithography and etching process. In other words, the fabricating method of the present invention is simplified and cost-effective. Since it is not necessary to repeatedly use the photomask for alignment, the precision of the alignment between the metal contact plug and the polysilicon gate is enhanced.
  • While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.

Claims (14)

1. A trench gate metal oxide semiconductor field effect transistor, comprising:
a substrate having a trench formed therein, wherein the trench is extended downwardly from a surface of the substrate; and
a gate comprising an insertion portion and a symmetrical protrusion portion, wherein the insertion portion is embedded in the trench, and the symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.
2. The trench gate metal oxide semiconductor field effect transistor according to claim 1, wherein the symmetrical protrusion portion is wider than the trench.
3. The trench gate metal oxide semiconductor field effect transistor according to claim 1, wherein the gate is a T-shaped gate, which is symmetrical with respect to a central line of the trench.
4. The trench gate metal oxide semiconductor field effect transistor according to claim 1, wherein the trench has a width smaller than or equal to 0.8 μm and a depth of about 1.6 μm.
5. The trench gate metal oxide semiconductor field effect transistor according to claim 1, further comprising:
a dielectric material layer disposed over the surface of the substrate and the gate; and
at least one contact plug penetrated through the dielectric material layer and electrically contacted with the symmetrical protrusion portion of the gate.
6. The trench gate metal oxide semiconductor field effect transistor according to claim 1, further comprising:
a first-conductive doped region formed in the substrate;
a second-conductive doped region formed in the substrate, wherein a P/N junction is formed between the first-conductive doped region and the second-conductive doped region, the trench is extended downwardly from the surface of the trench, penetrated through the first-conductive doped region and the P/N junction, and inserted into the second-conductive doped region;
a gate dielectric layer formed on a sidewall of the trench; and
a source region formed in the substrate and located beside the gate dielectric layer.
7. The trench gate metal oxide semiconductor field effect transistor according to claim 6, wherein the first-conductive doped region is a P-type body region, and the second-conductive doped region is an N-type well region.
8. The trench gate metal oxide semiconductor field effect transistor according to claim 6, further comprising an N-type buried layer, which is disposed under the second-conductive doped region.
9. The trench gate metal oxide semiconductor field effect transistor according to claim 6, wherein the source region is an N-type well region, and the source region is extended from the surface of the substrate into the first-conductive doped region.
10. A method for fabricating a trench gate metal oxide semiconductor field effect transistor, the method comprising steps of:
providing a substrate;
forming a hard mask layer on the substrate;
performing an etching process to remove a part of the hard mask layer and forming a trench in the substrate;
performing an etching back process to remove a part of the hard mask layer;
forming a conductive layer on the hard mask layer, and filling the polysilicon layer into the trench; and
performing a planarization process to remove the conductive layer by using the hard mask layer as a stop layer.
11. The method according to claim 10, wherein before the hard mask layer is formed, the method further comprises a step of forming a pad silicon oxide layer on the substrate.
12. The method according to claim 10, wherein after the hard mask layer is formed, the method further comprises a step of forming a sacrificial layer on the hard mask layer.
13. The method according to claim 10, wherein before the conductive layer is formed, the method further comprises a step of forming a gate dielectric layer on a sidewall of the trench by a thermal oxidation process.
14. The method according to claim 10, wherein the hard mask layer is a silicon oxide layer or a silicon nitride layer.
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